diff --git a/src/hg_mp/drx_top/huagao_mipi_top.v b/src/hg_mp/drx_top/huagao_mipi_top.v index c98d920..5ce6234 100644 --- a/src/hg_mp/drx_top/huagao_mipi_top.v +++ b/src/hg_mp/drx_top/huagao_mipi_top.v @@ -349,7 +349,7 @@ wire O_clk_lp_p_sync; wire O_clk_lp_n_sync; cdc_sync # ( .DEPTH (20), - .WIDTH (13) + .WIDTH (1) ) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */ .to_clk (clk_ubus ), .rest_n (rst_n ), @@ -359,7 +359,7 @@ cdc_sync # ( cdc_sync # ( .DEPTH (20), - .WIDTH (13) + .WIDTH (1) ) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */ .to_clk (clk_ubus ), .rest_n (rst_n ), @@ -565,6 +565,17 @@ reg frame_start_sync_d2_a/* synthesis syn_preserve=1 */; reg BUSY_MIPI_sync_d0;//synthesis keep reg BUSY_MIPI_sync_d1;//synthesis keep +wire BUSY_MIPI_sync; + +cdc_sync # ( + .DEPTH (13), + .WIDTH (1) +) u1_BUSY_MIPI ( + .to_clk (clk_ubus ), + .rest_n (rst_n ), + .signal_from(BUSY_MIPI ), + .signal_to (BUSY_MIPI_sync) +); always @ (posedge clk_ubus ) begin if (~rst_n) begin @@ -576,7 +587,7 @@ always @ (posedge clk_ubus ) begin BUSY_MIPI_sync_d1 <= 1'b0; end else begin - BUSY_MIPI_sync_d0 <= BUSY_MIPI; + BUSY_MIPI_sync_d0 <= BUSY_MIPI_sync; BUSY_MIPI_sync_d1 <= BUSY_MIPI_sync_d0; end end @@ -1717,8 +1728,8 @@ always @(*) begin end assign debug[0] = a_vs ; -assign debug[1] = debug_1[3]; -assign debug[2] = debug_1[2] ; +assign debug[1] = BUSY_MIPI; +assign debug[2] = BUSY_MIPI_sync ; assign debug[3] = debug_1[1]; assign debug[4] = debug_1[0] ; assign debug[5] = FV_MIPI ; diff --git a/src/prj/td_project/hg_anlogic.sdc b/src/prj/td_project/hg_anlogic.sdc index caf27f7..ed190c9 100644 --- a/src/prj/td_project/hg_anlogic.sdc +++ b/src/prj/td_project/hg_anlogic.sdc @@ -10,25 +10,22 @@ create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]} create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}] create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}] create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}] -set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}] +#set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}] #set_input_delay -clock [get_clocks {clock_source}] 12.5 [get_ports {a_ad_sdi b_ad_sdi clock_source global_reset_n gpio_trigger onoff_in paper_in rxd_dsp scan_in}] #set_input_delay -clock [get_clocks {a_lvds_clk_p}] 6.25 [get_ports {a_lvds_clk_p a_lvds_data_p a_lvds_data_p[0] a_lvds_data_p[1] a_lvds_data_p[2] a_lvds_data_p[3] a_lvds_data_p[4]}] #set_input_delay -clock [get_clocks {b_lvds_clk_p}] 6.25 [get_ports {b_lvds_clk_p b_lvds_data_p b_lvds_data_p[0] b_lvds_data_p[1] b_lvds_data_p[2] b_lvds_data_p[3] b_lvds_data_p[4]}] -set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[3]}] -to [get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d}] -set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[1]}] -to [get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2}] +#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[3]}] -to [get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d}] +#set_false_path -setup -from [get_pins {u_pll/pll_inst.clkc[1]}] -to [get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2}] #create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -edges {1 2 3} -edge_shift {0 -6.944 -13.889} [get_pins {u_pll/pll_inst.clkc[4]}] -#set_false_path -setup -from [get_regs{u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d_reg_syn_5}] -to [get_regs {sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[41]_syn_8}] create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4 -phase 0 [get_pins {u_pll/pll_inst.clkc[4]}] -set_false_path -from [get_regs {BUSY_MIPI}] -to [get_regs {BUSY_MIPI_sync_d0}] -set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}] -set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}] -#set_false_path -from [get_nets {u_bus_top/start_sp_a_tmp[*]}] -to [get_regs {u_bus_top/start_sp_a_sync1d_48m[*]}] -#set_false_path -from [get_nets {u_bus_top/start_sp_b_tmp[*]}] -to [get_regs {u_bus_top/start_sp_b_sync1d_48m[*]}] +#set_false_path -from [get_nets {u1_BUSY_MIPI/signal_from[*]}] -to [get_regs {u1_BUSY_MIPI/temp[*]}] +#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}] +#set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}] set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}] set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}] \ No newline at end of file diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_151123.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_151123.log new file mode 100644 index 0000000..60ab697 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_151123.log @@ -0,0 +1,2007 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:11:23 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.399135s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (100.3%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs BUSY_MIPI" +RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17745 instances +RUN-0007 : 7435 luts, 9087 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20323 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13378 nets have 2 pins +RUN-1001 : 5502 nets have [3 - 5] pins +RUN-1001 : 1031 nets have [6 - 10] pins +RUN-1001 : 159 nets have [11 - 20] pins +RUN-1001 : 179 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2012 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17743 instances, 7435 luts, 9087 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5941 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.139951s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.1%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.925461s wall, 1.875000s user + 0.046875s system = 1.921875s CPU (99.8%) + +PHY-3001 : Found 1219 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.03672e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17743. +PHY-3001 : Level 1 #clusters 2001. +PHY-3001 : End clustering; 0.131089s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (119.2%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28172e+06, overlap = 450.688 +PHY-3002 : Step(2): len = 1.17432e+06, overlap = 496.219 +PHY-3002 : Step(3): len = 856653, overlap = 576.094 +PHY-3002 : Step(4): len = 786084, overlap = 628.906 +PHY-3002 : Step(5): len = 595952, overlap = 759.281 +PHY-3002 : Step(6): len = 521360, overlap = 797.906 +PHY-3002 : Step(7): len = 440616, overlap = 913.812 +PHY-3002 : Step(8): len = 411923, overlap = 929.219 +PHY-3002 : Step(9): len = 368492, overlap = 1011.84 +PHY-3002 : Step(10): len = 344447, overlap = 1045.5 +PHY-3002 : Step(11): len = 308507, overlap = 1078.34 +PHY-3002 : Step(12): len = 283987, overlap = 1137.59 +PHY-3002 : Step(13): len = 260945, overlap = 1173.41 +PHY-3002 : Step(14): len = 239493, overlap = 1234.88 +PHY-3002 : Step(15): len = 224806, overlap = 1281.34 +PHY-3002 : Step(16): len = 206499, overlap = 1315.41 +PHY-3002 : Step(17): len = 190194, overlap = 1348.53 +PHY-3002 : Step(18): len = 172136, overlap = 1365.78 +PHY-3002 : Step(19): len = 161542, overlap = 1372.78 +PHY-3002 : Step(20): len = 146202, overlap = 1401.66 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10457e-06 +PHY-3002 : Step(21): len = 146798, overlap = 1396 +PHY-3002 : Step(22): len = 172633, overlap = 1332.34 +PHY-3002 : Step(23): len = 178535, overlap = 1234.84 +PHY-3002 : Step(24): len = 185020, overlap = 1204.31 +PHY-3002 : Step(25): len = 187522, overlap = 1183.28 +PHY-3002 : Step(26): len = 188298, overlap = 1152.5 +PHY-3002 : Step(27): len = 187442, overlap = 1116.62 +PHY-3002 : Step(28): len = 187095, overlap = 1079.91 +PHY-3002 : Step(29): len = 187618, overlap = 1077.53 +PHY-3002 : Step(30): len = 186342, overlap = 1047.97 +PHY-3002 : Step(31): len = 187852, overlap = 1046.09 +PHY-3002 : Step(32): len = 185978, overlap = 1058.34 +PHY-3002 : Step(33): len = 184677, overlap = 1048.94 +PHY-3002 : Step(34): len = 181811, overlap = 1031.5 +PHY-3002 : Step(35): len = 181702, overlap = 1027.47 +PHY-3002 : Step(36): len = 179387, overlap = 1046.06 +PHY-3002 : Step(37): len = 178992, overlap = 1058.69 +PHY-3002 : Step(38): len = 176523, overlap = 1062.59 +PHY-3002 : Step(39): len = 176436, overlap = 1064.91 +PHY-3002 : Step(40): len = 173457, overlap = 1072.81 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20914e-06 +PHY-3002 : Step(41): len = 177308, overlap = 1065.06 +PHY-3002 : Step(42): len = 190276, overlap = 1080.53 +PHY-3002 : Step(43): len = 194494, overlap = 1081.88 +PHY-3002 : Step(44): len = 197374, overlap = 1069.81 +PHY-3002 : Step(45): len = 198039, overlap = 1057.97 +PHY-3002 : Step(46): len = 198583, overlap = 1045.69 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.41828e-06 +PHY-3002 : Step(47): len = 205524, overlap = 1006.62 +PHY-3002 : Step(48): len = 221752, overlap = 868.594 +PHY-3002 : Step(49): len = 231082, overlap = 802.812 +PHY-3002 : Step(50): len = 239235, overlap = 809.188 +PHY-3002 : Step(51): len = 243212, overlap = 792.156 +PHY-3002 : Step(52): len = 244863, overlap = 759.938 +PHY-3002 : Step(53): len = 244837, overlap = 739.594 +PHY-3002 : Step(54): len = 243958, overlap = 733.281 +PHY-3002 : Step(55): len = 242207, overlap = 716.531 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.83657e-06 +PHY-3002 : Step(56): len = 257674, overlap = 678.75 +PHY-3002 : Step(57): len = 281477, overlap = 595.875 +PHY-3002 : Step(58): len = 290479, overlap = 533.531 +PHY-3002 : Step(59): len = 294876, overlap = 530.156 +PHY-3002 : Step(60): len = 292681, overlap = 540 +PHY-3002 : Step(61): len = 290012, overlap = 548.75 +PHY-3002 : Step(62): len = 286094, overlap = 558.438 +PHY-3002 : Step(63): len = 285239, overlap = 556.75 +PHY-3002 : Step(64): len = 286116, overlap = 564 +PHY-3002 : Step(65): len = 287019, overlap = 557.344 +PHY-3002 : Step(66): len = 286138, overlap = 561.25 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76731e-05 +PHY-3002 : Step(67): len = 304136, overlap = 548.594 +PHY-3002 : Step(68): len = 321073, overlap = 520.75 +PHY-3002 : Step(69): len = 326901, overlap = 462.375 +PHY-3002 : Step(70): len = 328175, overlap = 440.594 +PHY-3002 : Step(71): len = 326166, overlap = 419.219 +PHY-3002 : Step(72): len = 325697, overlap = 391.344 +PHY-3002 : Step(73): len = 325583, overlap = 378.188 +PHY-3002 : Step(74): len = 327742, overlap = 371.938 +PHY-3002 : Step(75): len = 326770, overlap = 377.25 +PHY-3002 : Step(76): len = 326758, overlap = 373.531 +PHY-3002 : Step(77): len = 326655, overlap = 382.125 +PHY-3002 : Step(78): len = 328557, overlap = 385.25 +PHY-3002 : Step(79): len = 327968, overlap = 384.719 +PHY-3002 : Step(80): len = 327971, overlap = 385.906 +PHY-3002 : Step(81): len = 328104, overlap = 396.406 +PHY-3002 : Step(82): len = 328472, overlap = 390.531 +PHY-3002 : Step(83): len = 328239, overlap = 387.719 +PHY-3002 : Step(84): len = 329143, overlap = 393.812 +PHY-3002 : Step(85): len = 327973, overlap = 397.875 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.53463e-05 +PHY-3002 : Step(86): len = 345898, overlap = 359.469 +PHY-3002 : Step(87): len = 359117, overlap = 339.75 +PHY-3002 : Step(88): len = 360816, overlap = 334.688 +PHY-3002 : Step(89): len = 361674, overlap = 334.812 +PHY-3002 : Step(90): len = 361511, overlap = 325.656 +PHY-3002 : Step(91): len = 362609, overlap = 312.125 +PHY-3002 : Step(92): len = 361131, overlap = 312.438 +PHY-3002 : Step(93): len = 361755, overlap = 315.188 +PHY-3002 : Step(94): len = 362466, overlap = 298.281 +PHY-3002 : Step(95): len = 363451, overlap = 296.312 +PHY-3002 : Step(96): len = 361923, overlap = 299.594 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.06925e-05 +PHY-3002 : Step(97): len = 380686, overlap = 280.875 +PHY-3002 : Step(98): len = 393877, overlap = 282.906 +PHY-3002 : Step(99): len = 391804, overlap = 268.094 +PHY-3002 : Step(100): len = 393310, overlap = 250.5 +PHY-3002 : Step(101): len = 394805, overlap = 250.688 +PHY-3002 : Step(102): len = 397473, overlap = 253 +PHY-3002 : Step(103): len = 394544, overlap = 256.438 +PHY-3002 : Step(104): len = 394989, overlap = 257.156 +PHY-3002 : Step(105): len = 396401, overlap = 240.719 +PHY-3002 : Step(106): len = 397811, overlap = 239 +PHY-3002 : Step(107): len = 396411, overlap = 242.188 +PHY-3002 : Step(108): len = 397568, overlap = 223.469 +PHY-3002 : Step(109): len = 399560, overlap = 225.5 +PHY-3002 : Step(110): len = 400464, overlap = 210.938 +PHY-3002 : Step(111): len = 398255, overlap = 214.312 +PHY-3002 : Step(112): len = 398369, overlap = 214.938 +PHY-3002 : Step(113): len = 399100, overlap = 209.25 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141385 +PHY-3002 : Step(114): len = 415646, overlap = 186.344 +PHY-3002 : Step(115): len = 424994, overlap = 208.875 +PHY-3002 : Step(116): len = 421927, overlap = 213.625 +PHY-3002 : Step(117): len = 421730, overlap = 206.906 +PHY-3002 : Step(118): len = 426278, overlap = 188.875 +PHY-3002 : Step(119): len = 429889, overlap = 188 +PHY-3002 : Step(120): len = 426628, overlap = 190.188 +PHY-3002 : Step(121): len = 427999, overlap = 193.25 +PHY-3002 : Step(122): len = 431889, overlap = 189.969 +PHY-3002 : Step(123): len = 435532, overlap = 192.469 +PHY-3002 : Step(124): len = 432226, overlap = 190 +PHY-3002 : Step(125): len = 432069, overlap = 180.531 +PHY-3002 : Step(126): len = 434337, overlap = 182.5 +PHY-3002 : Step(127): len = 436053, overlap = 179.25 +PHY-3002 : Step(128): len = 433744, overlap = 172.312 +PHY-3002 : Step(129): len = 433743, overlap = 176.469 +PHY-3002 : Step(130): len = 435984, overlap = 177.688 +PHY-3002 : Step(131): len = 437181, overlap = 180 +PHY-3002 : Step(132): len = 434829, overlap = 179.125 +PHY-3002 : Step(133): len = 434539, overlap = 181.906 +PHY-3002 : Step(134): len = 436034, overlap = 184.469 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00028277 +PHY-3002 : Step(135): len = 446842, overlap = 173.188 +PHY-3002 : Step(136): len = 456483, overlap = 164.562 +PHY-3002 : Step(137): len = 457435, overlap = 166.531 +PHY-3002 : Step(138): len = 458660, overlap = 169.531 +PHY-3002 : Step(139): len = 462075, overlap = 163.125 +PHY-3002 : Step(140): len = 464987, overlap = 160.781 +PHY-3002 : Step(141): len = 463523, overlap = 163.281 +PHY-3002 : Step(142): len = 463423, overlap = 163.469 +PHY-3002 : Step(143): len = 464548, overlap = 158.156 +PHY-3002 : Step(144): len = 466447, overlap = 164.5 +PHY-3002 : Step(145): len = 466639, overlap = 155.094 +PHY-3002 : Step(146): len = 468136, overlap = 162.219 +PHY-3002 : Step(147): len = 468952, overlap = 161.062 +PHY-3002 : Step(148): len = 469376, overlap = 160.781 +PHY-3002 : Step(149): len = 468182, overlap = 167.469 +PHY-3002 : Step(150): len = 468430, overlap = 166.562 +PHY-3002 : Step(151): len = 469025, overlap = 160.844 +PHY-3002 : Step(152): len = 469376, overlap = 158.219 +PHY-3002 : Step(153): len = 468892, overlap = 157.344 +PHY-3002 : Step(154): len = 469813, overlap = 158.219 +PHY-3002 : Step(155): len = 470872, overlap = 155.562 +PHY-3002 : Step(156): len = 471704, overlap = 155.844 +PHY-3002 : Step(157): len = 470506, overlap = 155.469 +PHY-3002 : Step(158): len = 470267, overlap = 156.344 +PHY-3002 : Step(159): len = 470463, overlap = 162.594 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000563391 +PHY-3002 : Step(160): len = 476929, overlap = 161.812 +PHY-3002 : Step(161): len = 484567, overlap = 151.156 +PHY-3002 : Step(162): len = 486813, overlap = 149.281 +PHY-3002 : Step(163): len = 488813, overlap = 149.875 +PHY-3002 : Step(164): len = 490570, overlap = 140.344 +PHY-3002 : Step(165): len = 491244, overlap = 141.281 +PHY-3002 : Step(166): len = 490396, overlap = 141.625 +PHY-3002 : Step(167): len = 490181, overlap = 141.156 +PHY-3002 : Step(168): len = 490945, overlap = 140.75 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0011016 +PHY-3002 : Step(169): len = 496449, overlap = 127.094 +PHY-3002 : Step(170): len = 504286, overlap = 130.031 +PHY-3002 : Step(171): len = 506351, overlap = 122.312 +PHY-3002 : Step(172): len = 507900, overlap = 123.844 +PHY-3002 : Step(173): len = 509788, overlap = 120.188 +PHY-3002 : Step(174): len = 511974, overlap = 114.219 +PHY-3002 : Step(175): len = 512667, overlap = 116.344 +PHY-3002 : Step(176): len = 513356, overlap = 115.906 +PHY-3002 : Step(177): len = 514345, overlap = 110.969 +PHY-3002 : Step(178): len = 514859, overlap = 111.062 +PHY-3002 : Step(179): len = 514889, overlap = 109.375 +PHY-3002 : Step(180): len = 514907, overlap = 107.562 +PHY-3002 : Step(181): len = 515226, overlap = 113.094 +PHY-3002 : Step(182): len = 515315, overlap = 115.344 +PHY-3002 : Step(183): len = 515218, overlap = 112.844 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0019155 +PHY-3002 : Step(184): len = 518415, overlap = 110.375 +PHY-3002 : Step(185): len = 524256, overlap = 105.188 +PHY-3002 : Step(186): len = 525904, overlap = 103.719 +PHY-3002 : Step(187): len = 527046, overlap = 101.125 +PHY-3002 : Step(188): len = 528391, overlap = 103.469 +PHY-3002 : Step(189): len = 529211, overlap = 107.188 +PHY-3002 : Step(190): len = 529278, overlap = 108.062 +PHY-3002 : Step(191): len = 529454, overlap = 108.406 +PHY-3002 : Step(192): len = 530029, overlap = 109.812 +PHY-3002 : Step(193): len = 530358, overlap = 111.219 +PHY-3002 : Step(194): len = 530896, overlap = 109.219 +PHY-3002 : Step(195): len = 531644, overlap = 108.031 +PHY-3002 : Step(196): len = 532126, overlap = 108.594 +PHY-3002 : Step(197): len = 532260, overlap = 108.688 +PHY-3002 : Step(198): len = 532185, overlap = 107.188 +PHY-3002 : Step(199): len = 532272, overlap = 106.312 +PHY-3002 : Step(200): len = 532808, overlap = 102.562 +PHY-3002 : Step(201): len = 533198, overlap = 103.875 +PHY-3002 : Step(202): len = 533068, overlap = 102.125 +PHY-3002 : Step(203): len = 533068, overlap = 102.125 +PHY-3002 : Step(204): len = 533123, overlap = 103.125 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.011102s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (422.2%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 714624, over cnt = 1568(4%), over = 7178, worst = 44 +PHY-1001 : End global iterations; 0.708577s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (127.9%) + +PHY-1001 : Congestion index: top1 = 75.67, top5 = 59.90, top10 = 51.49, top15 = 46.05. +PHY-3001 : End congestion estimation; 0.941062s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (122.9%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.880195s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (99.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126945 +PHY-3002 : Step(205): len = 651620, overlap = 56.3125 +PHY-3002 : Step(206): len = 653297, overlap = 65.5 +PHY-3002 : Step(207): len = 647753, overlap = 69.3438 +PHY-3002 : Step(208): len = 641445, overlap = 63.8438 +PHY-3002 : Step(209): len = 635799, overlap = 61.0312 +PHY-3002 : Step(210): len = 633738, overlap = 62.5938 +PHY-3002 : Step(211): len = 633098, overlap = 61.125 +PHY-3002 : Step(212): len = 632272, overlap = 56.75 +PHY-3002 : Step(213): len = 630468, overlap = 53.875 +PHY-3002 : Step(214): len = 627875, overlap = 48.125 +PHY-3002 : Step(215): len = 624830, overlap = 45.5312 +PHY-3002 : Step(216): len = 622143, overlap = 43.75 +PHY-3002 : Step(217): len = 620834, overlap = 37.25 +PHY-3002 : Step(218): len = 619641, overlap = 35.625 +PHY-3002 : Step(219): len = 618180, overlap = 34.1562 +PHY-3002 : Step(220): len = 618174, overlap = 37.2188 +PHY-3002 : Step(221): len = 617188, overlap = 36.9062 +PHY-3002 : Step(222): len = 615032, overlap = 38.0625 +PHY-3002 : Step(223): len = 612216, overlap = 38.9688 +PHY-3002 : Step(224): len = 610202, overlap = 35.9688 +PHY-3002 : Step(225): len = 608415, overlap = 36.0312 +PHY-3002 : Step(226): len = 606921, overlap = 38.9062 +PHY-3002 : Step(227): len = 605497, overlap = 37.1562 +PHY-3002 : Step(228): len = 603987, overlap = 36.625 +PHY-3002 : Step(229): len = 602886, overlap = 37.875 +PHY-3002 : Step(230): len = 601605, overlap = 36.7812 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025389 +PHY-3002 : Step(231): len = 605623, overlap = 35.1875 +PHY-3002 : Step(232): len = 608395, overlap = 33.9375 +PHY-3002 : Step(233): len = 609611, overlap = 32.0938 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000434206 +PHY-3002 : Step(234): len = 618373, overlap = 34.3438 +PHY-3002 : Step(235): len = 633524, overlap = 31.4062 +PHY-3002 : Step(236): len = 634716, overlap = 31.9062 +PHY-3002 : Step(237): len = 635266, overlap = 28.625 +PHY-3002 : Step(238): len = 635530, overlap = 26.0938 +PHY-3002 : Step(239): len = 634102, overlap = 28.7812 +PHY-3002 : Step(240): len = 634254, overlap = 30.9062 +PHY-3002 : Step(241): len = 634458, overlap = 33 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 48/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 719896, over cnt = 2733(7%), over = 11815, worst = 44 +PHY-1001 : End global iterations; 1.733155s wall, 2.265625s user + 0.062500s system = 2.328125s CPU (134.3%) + +PHY-1001 : Congestion index: top1 = 83.60, top5 = 64.83, top10 = 56.55, top15 = 51.64. +PHY-3001 : End congestion estimation; 1.996035s wall, 2.531250s user + 0.062500s system = 2.593750s CPU (129.9%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.878762s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000107045 +PHY-3002 : Step(242): len = 629397, overlap = 229.344 +PHY-3002 : Step(243): len = 630978, overlap = 186.312 +PHY-3002 : Step(244): len = 623229, overlap = 162.406 +PHY-3002 : Step(245): len = 618172, overlap = 145.188 +PHY-3002 : Step(246): len = 613147, overlap = 126.312 +PHY-3002 : Step(247): len = 610145, overlap = 125.594 +PHY-3002 : Step(248): len = 605265, overlap = 124.156 +PHY-3002 : Step(249): len = 603035, overlap = 127.125 +PHY-3002 : Step(250): len = 600841, overlap = 120.906 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000214089 +PHY-3002 : Step(251): len = 601155, overlap = 118.719 +PHY-3002 : Step(252): len = 603472, overlap = 114.906 +PHY-3002 : Step(253): len = 605803, overlap = 105.031 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000428178 +PHY-3002 : Step(254): len = 611464, overlap = 95.9688 +PHY-3002 : Step(255): len = 619589, overlap = 83.3125 +PHY-3002 : Step(256): len = 625102, overlap = 79.1562 +PHY-3002 : Step(257): len = 627521, overlap = 76.625 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.446648s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.4%) + +RUN-1004 : used memory is 581 MB, reserved memory is 562 MB, peak memory is 718 MB +OPT-1001 : Total overflow 384.84 peak overflow 3.47 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1093/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 724368, over cnt = 3038(8%), over = 10466, worst = 26 +PHY-1001 : End global iterations; 1.180350s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (149.6%) + +PHY-1001 : Congestion index: top1 = 70.22, top5 = 56.96, top10 = 50.61, top15 = 46.87. +PHY-1001 : End incremental global routing; 1.529250s wall, 2.078125s user + 0.031250s system = 2.109375s CPU (137.9%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.909130s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.7%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17607 has valid locations, 349 needs to be replaced +PHY-3001 : design contains 18041 instances, 7532 luts, 9288 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6063 pins +PHY-3001 : Found 1231 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 650874 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16601/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738040, over cnt = 3068(8%), over = 10637, worst = 26 +PHY-1001 : End global iterations; 0.237710s wall, 0.312500s user + 0.031250s system = 0.343750s CPU (144.6%) + +PHY-1001 : Congestion index: top1 = 69.94, top5 = 57.07, top10 = 50.94, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.492813s wall, 0.546875s user + 0.046875s system = 0.593750s CPU (120.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86082, tnet num: 20443, tinst num: 18041, tnode num: 116915, tedge num: 138008. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.439860s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.8%) + +RUN-1004 : used memory is 623 MB, reserved memory is 609 MB, peak memory is 719 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.392960s wall, 2.343750s user + 0.046875s system = 2.390625s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(258): len = 650035, overlap = 0.125 +PHY-3002 : Step(259): len = 649700, overlap = 0.125 +PHY-3002 : Step(260): len = 649450, overlap = 0.125 +PHY-3002 : Step(261): len = 649177, overlap = 0.125 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16724/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 735584, over cnt = 3070(8%), over = 10643, worst = 26 +PHY-1001 : End global iterations; 0.187437s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (133.4%) + +PHY-1001 : Congestion index: top1 = 70.19, top5 = 57.15, top10 = 50.97, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.437338s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (114.3%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.923707s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.8%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000334276 +PHY-3002 : Step(262): len = 649093, overlap = 79.4375 +PHY-3002 : Step(263): len = 649168, overlap = 78.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000668551 +PHY-3002 : Step(264): len = 649153, overlap = 79.0312 +PHY-3002 : Step(265): len = 649644, overlap = 78.625 +PHY-3001 : Final: Len = 649644, Over = 78.625 +PHY-3001 : End incremental placement; 4.906077s wall, 5.171875s user + 0.390625s system = 5.562500s CPU (113.4%) + +OPT-1001 : Total overflow 390.09 peak overflow 3.47 +OPT-1001 : End high-fanout net optimization; 7.887640s wall, 8.765625s user + 0.437500s system = 9.203125s CPU (116.7%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 740. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16679/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738800, over cnt = 3016(8%), over = 9702, worst = 26 +PHY-1002 : len = 785712, over cnt = 1985(5%), over = 4886, worst = 21 +PHY-1002 : len = 825896, over cnt = 801(2%), over = 1646, worst = 16 +PHY-1002 : len = 844056, over cnt = 213(0%), over = 333, worst = 11 +PHY-1002 : len = 848840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.705324s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (139.3%) + +PHY-1001 : Congestion index: top1 = 57.22, top5 = 49.72, top10 = 45.96, top15 = 43.61. +OPT-1001 : End congestion update; 1.976310s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (134.4%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.830106s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 115 cells processed and 15100 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 1084 slack improved +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved +OPT-1001 : End bottleneck based optimization; 3.116328s wall, 3.796875s user + 0.000000s system = 3.796875s CPU (121.8%) + +OPT-1001 : Current memory(MB): used = 699, reserve = 688, peak = 740. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16775/20623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849680, over cnt = 74(0%), over = 94, worst = 4 +PHY-1002 : len = 849528, over cnt = 33(0%), over = 36, worst = 3 +PHY-1002 : len = 849784, over cnt = 8(0%), over = 8, worst = 1 +PHY-1002 : len = 849832, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 849848, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.741530s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.1%) + +PHY-1001 : Congestion index: top1 = 56.90, top5 = 49.64, top10 = 45.91, top15 = 43.56. +OPT-1001 : End congestion update; 1.014185s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (101.7%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.812035s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.1%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 4450 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.944631s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (100.4%) + +OPT-1001 : Current memory(MB): used = 711, reserve = 698, peak = 740. +OPT-1001 : End physical optimization; 14.710933s wall, 16.328125s user + 0.484375s system = 16.812500s CPU (114.3%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7532 LUT to BLE ... +SYN-4008 : Packed 7532 LUT and 3133 SEQ to BLE. +SYN-4003 : Packing 6157 remaining SEQ's ... +SYN-4005 : Packed 3725 SEQ with LUT/SLICE +SYN-4006 : 977 single LUT's are left +SYN-4006 : 2432 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9964/13787 primitive instances ... +PHY-3001 : End packing; 1.630661s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.7%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6874 instances +RUN-1001 : 3363 mslices, 3363 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17618 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10005 nets have 2 pins +RUN-1001 : 5769 nets have [3 - 5] pins +RUN-1001 : 1139 nets have [6 - 10] pins +RUN-1001 : 345 nets have [11 - 20] pins +RUN-1001 : 327 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6872 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3573 pins +PHY-3001 : Found 490 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 662223, Over = 253.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 7617/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 811720, over cnt = 1957(5%), over = 3182, worst = 8 +PHY-1002 : len = 819944, over cnt = 1208(3%), over = 1726, worst = 6 +PHY-1002 : len = 834160, over cnt = 468(1%), over = 625, worst = 5 +PHY-1002 : len = 841744, over cnt = 134(0%), over = 157, worst = 4 +PHY-1002 : len = 844704, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.624611s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (133.7%) + +PHY-1001 : Congestion index: top1 = 58.53, top5 = 50.73, top10 = 46.56, top15 = 43.91. +PHY-3001 : End congestion estimation; 2.026671s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (127.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6872, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.668316s wall, 1.640625s user + 0.015625s system = 1.656250s CPU (99.3%) + +RUN-1004 : used memory is 620 MB, reserved memory is 614 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.565617s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.65564e-05 +PHY-3002 : Step(266): len = 649520, overlap = 250 +PHY-3002 : Step(267): len = 642403, overlap = 253.75 +PHY-3002 : Step(268): len = 637448, overlap = 255 +PHY-3002 : Step(269): len = 634168, overlap = 254 +PHY-3002 : Step(270): len = 632517, overlap = 259.25 +PHY-3002 : Step(271): len = 631073, overlap = 264.75 +PHY-3002 : Step(272): len = 627992, overlap = 264.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.31129e-05 +PHY-3002 : Step(273): len = 630887, overlap = 259.75 +PHY-3002 : Step(274): len = 634775, overlap = 254 +PHY-3002 : Step(275): len = 634921, overlap = 251.25 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000186226 +PHY-3002 : Step(276): len = 644232, overlap = 241.25 +PHY-3002 : Step(277): len = 652624, overlap = 229.25 +PHY-3002 : Step(278): len = 652092, overlap = 229.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.366228s wall, 0.375000s user + 0.453125s system = 0.828125s CPU (226.1%) + +PHY-3001 : Trial Legalized: Len = 732801 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 884/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849856, over cnt = 2629(7%), over = 4435, worst = 8 +PHY-1002 : len = 866496, over cnt = 1574(4%), over = 2279, worst = 6 +PHY-1002 : len = 885736, over cnt = 545(1%), over = 755, worst = 6 +PHY-1002 : len = 895568, over cnt = 99(0%), over = 127, worst = 5 +PHY-1002 : len = 897712, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.374093s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (149.4%) + +PHY-1001 : Congestion index: top1 = 56.34, top5 = 49.93, top10 = 46.51, top15 = 44.33. +PHY-3001 : End congestion estimation; 2.848469s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (141.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.873141s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165 +PHY-3002 : Step(279): len = 706565, overlap = 45.75 +PHY-3002 : Step(280): len = 692044, overlap = 70.5 +PHY-3002 : Step(281): len = 678987, overlap = 101.75 +PHY-3002 : Step(282): len = 671353, overlap = 129 +PHY-3002 : Step(283): len = 666387, overlap = 147 +PHY-3002 : Step(284): len = 664006, overlap = 154.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033 +PHY-3002 : Step(285): len = 669536, overlap = 153.25 +PHY-3002 : Step(286): len = 675137, overlap = 150.25 +PHY-3002 : Step(287): len = 677080, overlap = 152.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00064827 +PHY-3002 : Step(288): len = 680934, overlap = 147.75 +PHY-3002 : Step(289): len = 688915, overlap = 146.25 +PHY-3002 : Step(290): len = 698496, overlap = 140.25 +PHY-3002 : Step(291): len = 700456, overlap = 140.75 +PHY-3002 : Step(292): len = 701680, overlap = 142.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.034174s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.4%) + +PHY-3001 : Legalized: Len = 728102, Over = 0 +PHY-3001 : Spreading special nets. 443 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.101574s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (107.7%) + +PHY-3001 : 628 instances has been re-located, deltaX = 184, deltaY = 381, maxDist = 2. +PHY-3001 : Final: Len = 737976, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6875, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.912395s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (99.7%) + +RUN-1004 : used memory is 627 MB, reserved memory is 637 MB, peak memory is 740 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 3082/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 863136, over cnt = 2610(7%), over = 4296, worst = 6 +PHY-1002 : len = 879048, over cnt = 1415(4%), over = 2042, worst = 6 +PHY-1002 : len = 895448, over cnt = 542(1%), over = 771, worst = 5 +PHY-1002 : len = 904664, over cnt = 130(0%), over = 187, worst = 5 +PHY-1002 : len = 907272, over cnt = 11(0%), over = 19, worst = 5 +PHY-1001 : End global iterations; 2.155579s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (147.9%) + +PHY-1001 : Congestion index: top1 = 56.10, top5 = 49.56, top10 = 46.28, top15 = 44.25. +PHY-1001 : End incremental global routing; 2.554094s wall, 3.578125s user + 0.015625s system = 3.593750s CPU (140.7%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 1.189777s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (99.8%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6782 has valid locations, 30 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 741838 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16076/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 911648, over cnt = 110(0%), over = 130, worst = 5 +PHY-1002 : len = 911776, over cnt = 60(0%), over = 65, worst = 3 +PHY-1002 : len = 912328, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 912392, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 912456, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.981605s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (103.5%) + +PHY-1001 : Congestion index: top1 = 56.19, top5 = 49.69, top10 = 46.41, top15 = 44.36. +PHY-3001 : End congestion estimation; 1.330569s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (102.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74012, tnet num: 17472, tinst num: 6900, tnode num: 96587, tedge num: 124127. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.890483s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.0%) + +RUN-1004 : used memory is 663 MB, reserved memory is 654 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.784800s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(293): len = 740891, overlap = 0.5 +PHY-3002 : Step(294): len = 740538, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16066/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910472, over cnt = 75(0%), over = 95, worst = 6 +PHY-1002 : len = 910680, over cnt = 32(0%), over = 34, worst = 2 +PHY-1002 : len = 911064, over cnt = 9(0%), over = 9, worst = 1 +PHY-1002 : len = 911200, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 911216, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.780775s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (110.1%) + +PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.69, top10 = 46.41, top15 = 44.34. +PHY-3001 : End congestion estimation; 1.092915s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (107.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.854265s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160642 +PHY-3002 : Step(295): len = 740237, overlap = 1.75 +PHY-3002 : Step(296): len = 740365, overlap = 2 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005623s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (277.9%) + +PHY-3001 : Legalized: Len = 740500, Over = 0 +PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060464s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.4%) + +PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 2. +PHY-3001 : Final: Len = 740436, Over = 0 +PHY-3001 : End incremental placement; 6.583526s wall, 6.671875s user + 0.109375s system = 6.781250s CPU (103.0%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 10.890732s wall, 11.937500s user + 0.140625s system = 12.078125s CPU (110.9%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 739, peak = 750. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16051/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910608, over cnt = 64(0%), over = 75, worst = 3 +PHY-1002 : len = 910552, over cnt = 29(0%), over = 30, worst = 2 +PHY-1002 : len = 910712, over cnt = 5(0%), over = 5, worst = 1 +PHY-1002 : len = 910776, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 910792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.769467s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (107.6%) + +PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.74, top10 = 46.39, top15 = 44.32. +OPT-1001 : End congestion update; 1.084132s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (105.2%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.750899s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.9%) + +OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 743728, Over = 0 +PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062464s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%) + +PHY-3001 : 20 instances has been re-located, deltaX = 9, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 744032, Over = 0 +PHY-3001 : End incremental legalization; 0.382632s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (102.1%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 10363 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748708, Over = 0 +PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059686s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%) + +PHY-3001 : 18 instances has been re-located, deltaX = 7, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 749102, Over = 0 +PHY-3001 : End incremental legalization; 0.382319s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (126.7%) + +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 30 cells processed and 9680 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748964, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060248s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.8%) + +PHY-3001 : 6 instances has been re-located, deltaX = 5, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 749362, Over = 0 +PHY-3001 : End incremental legalization; 0.380496s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.7%) + +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 649 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750417, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060261s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.7%) + +PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 750441, Over = 0 +PHY-3001 : End incremental legalization; 0.380501s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.6%) + +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 1081 slack improved +OPT-1001 : End bottleneck based optimization; 3.921905s wall, 4.250000s user + 0.015625s system = 4.265625s CPU (108.8%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 739, peak = 750. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15658/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 921656, over cnt = 225(0%), over = 304, worst = 9 +PHY-1002 : len = 921944, over cnt = 124(0%), over = 136, worst = 4 +PHY-1002 : len = 922344, over cnt = 84(0%), over = 89, worst = 2 +PHY-1002 : len = 923408, over cnt = 19(0%), over = 19, worst = 1 +PHY-1002 : len = 923864, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.880676s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (108.2%) + +PHY-1001 : Congestion index: top1 = 56.08, top5 = 49.86, top10 = 46.58, top15 = 44.47. +OPT-1001 : End congestion update; 1.196873s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (107.0%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.720543s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.8%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750211, Over = 0 +PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061601s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.5%) + +PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 9, maxDist = 2. +PHY-3001 : Final: Len = 750501, Over = 0 +PHY-3001 : End incremental legalization; 0.418706s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (123.1%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.490705s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (107.3%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 739, peak = 750. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.720212s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.8%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16067/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 923880, over cnt = 30(0%), over = 31, worst = 2 +PHY-1002 : len = 923824, over cnt = 13(0%), over = 13, worst = 1 +PHY-1002 : len = 923856, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 923856, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 923904, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.771391s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (105.3%) + +PHY-1001 : Congestion index: top1 = 56.12, top5 = 49.87, top10 = 46.62, top15 = 44.51. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.720983s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.7%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.620690 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 221ps with logic level 1 +OPT-1001 : End physical optimization; 21.991099s wall, 23.546875s user + 0.171875s system = 23.718750s CPU (107.9%) + +RUN-1003 : finish command "place" in 65.719581s wall, 92.062500s user + 6.062500s system = 98.125000s CPU (149.3%) + +RUN-1004 : used memory is 687 MB, reserved memory is 692 MB, peak memory is 750 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.690312s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (174.7%) + +RUN-1004 : used memory is 687 MB, reserved memory is 693 MB, peak memory is 750 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6908 instances +RUN-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17653 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10002 nets have 2 pins +RUN-1001 : 5782 nets have [3 - 5] pins +RUN-1001 : 1143 nets have [6 - 10] pins +RUN-1001 : 352 nets have [11 - 20] pins +RUN-1001 : 345 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.621382s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.3%) + +RUN-1004 : used memory is 672 MB, reserved memory is 667 MB, peak memory is 750 MB +PHY-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 858424, over cnt = 2701(7%), over = 4497, worst = 8 +PHY-1002 : len = 877136, over cnt = 1568(4%), over = 2249, worst = 6 +PHY-1002 : len = 892488, over cnt = 746(2%), over = 1063, worst = 6 +PHY-1002 : len = 907912, over cnt = 24(0%), over = 37, worst = 6 +PHY-1002 : len = 908592, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.008554s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (135.0%) + +PHY-1001 : Congestion index: top1 = 55.41, top5 = 49.60, top10 = 46.25, top15 = 44.10. +PHY-1001 : End global routing; 3.336918s wall, 4.343750s user + 0.031250s system = 4.375000s CPU (131.1%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 724, reserve = 716, peak = 750. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 996, reserve = 992, peak = 996. +PHY-1001 : End build detailed router design. 4.054723s wall, 4.015625s user + 0.031250s system = 4.046875s CPU (99.8%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 265920, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 5.101504s wall, 5.109375s user + 0.000000s system = 5.109375s CPU (100.2%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 265976, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.429054s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.3%) + +PHY-1001 : Current memory(MB): used = 1032, reserve = 1028, peak = 1032. +PHY-1001 : End phase 1; 5.543166s wall, 5.546875s user + 0.000000s system = 5.546875s CPU (100.1%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 43% nets. +PHY-1001 : Routed 51% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.34276e+06, over cnt = 1866(0%), over = 1879, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1048, reserve = 1043, peak = 1048. +PHY-1001 : End initial routed; 29.452309s wall, 63.062500s user + 0.421875s system = 63.484375s CPU (215.5%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.293287s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.1%) + +PHY-1001 : Current memory(MB): used = 1059, reserve = 1055, peak = 1059. +PHY-1001 : End phase 2; 32.745664s wall, 66.359375s user + 0.421875s system = 66.781250s CPU (203.9%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.157970s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.9%) + +PHY-1022 : len = 2.34276e+06, over cnt = 1867(0%), over = 1880, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.424325s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.31113e+06, over cnt = 653(0%), over = 655, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.141479s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (206.7%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.31112e+06, over cnt = 129(0%), over = 129, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.649938s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (161.1%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.31181e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.342092s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (132.5%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.3119e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.228770s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.3%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 5; 0.196746s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (95.3%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.254970s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.3%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 2.231009s wall, 2.187500s user + 0.046875s system = 2.234375s CPU (100.2%) + +PHY-1001 : Current memory(MB): used = 1161, reserve = 1160, peak = 1161. +PHY-1001 : End phase 3; 8.875374s wall, 10.578125s user + 0.046875s system = 10.625000s CPU (119.7%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.136773s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.8%) + +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.385560s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.3%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.339349s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.1%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 2.328728s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1170, reserve = 1169, peak = 1170. +PHY-1001 : End phase 4; 6.081603s wall, 6.078125s user + 0.000000s system = 6.078125s CPU (99.9%) + +PHY-1003 : Routed, final wirelength = 2.31198e+06 +PHY-1001 : Current memory(MB): used = 1172, reserve = 1171, peak = 1172. +PHY-1001 : End export database. 0.152270s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.4%) + +PHY-1001 : End detail routing; 57.851217s wall, 93.140625s user + 0.500000s system = 93.640625s CPU (161.9%) + +RUN-1003 : finish command "route" in 63.877355s wall, 100.171875s user + 0.531250s system = 100.703125s CPU (157.7%) + +RUN-1004 : used memory is 1097 MB, reserved memory is 1094 MB, peak memory is 1172 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10272 out of 19600 52.41% +#reg 9440 out of 19600 48.16% +#le 12642 + #lut only 3202 out of 12642 25.33% + #reg only 2370 out of 12642 18.75% + #lut® 7070 out of 12642 55.92% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1411 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 67 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_275.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_295.f0 3 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P16 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE + debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P110 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12642 |9245 |1027 |9472 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |534 |414 |23 |439 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |105 |89 |4 |93 |4 |0 | +| U_crc16_24b |crc16_24b |35 |35 |0 |21 |0 |0 | +| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 | +| exdev_ctl_a |exdev_ctl |783 |363 |96 |589 |0 |0 | +| u_ADconfig |AD_config |196 |132 |25 |142 |0 |0 | +| u_gen_sp |gen_sp |263 |146 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |755 |389 |96 |568 |0 |0 | +| u_ADconfig |AD_config |179 |143 |25 |128 |0 |0 | +| u_gen_sp |gen_sp |258 |158 |71 |122 |0 |0 | +| sampling_fe_a |sampling_fe |3082 |2473 |306 |2092 |25 |0 | +| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 | +| u_ad_sampling |ad_sampling |178 |118 |17 |140 |0 |0 | +| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_sort |sort |2866 |2347 |289 |1914 |25 |0 | +| rddpram_ctl |rddpram_ctl |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer |data_prebuffer |2426 |2024 |253 |1569 |22 |0 | +| channelPart |channel_part_8478 |130 |125 |3 |122 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |0 | +| ram_switch |ram_switch |1920 |1590 |197 |1175 |0 |0 | +| adc_addr_gen |adc_addr_gen |231 |204 |27 |126 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 | +| insert |insert |949 |648 |170 |655 |0 |0 | +| ram_switch_state |ram_switch_state |740 |738 |0 |394 |0 |0 | +| read_ram_i |read_ram |283 |235 |44 |196 |0 |0 | +| read_ram_addr |read_ram_addr |227 |187 |40 |156 |0 |0 | +| read_ram_data |read_ram_data |53 |46 |4 |37 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |334 |244 |36 |271 |3 |0 | +| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3369 |2673 |349 |2099 |25 |1 | +| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |182 |111 |17 |148 |0 |0 | +| u_sort |sort_rev |3150 |2545 |332 |1916 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2693 |2207 |290 |1564 |22 |1 | +| channelPart |channel_part_8478 |233 |230 |3 |142 |0 |0 | +| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 | +| ram_switch |ram_switch |1998 |1643 |197 |1130 |0 |0 | +| adc_addr_gen |adc_addr_gen |213 |186 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |4 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |4 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 | +| insert |insert |974 |648 |170 |672 |0 |0 | +| ram_switch_state |ram_switch_state |811 |809 |0 |352 |0 |0 | +| read_ram_i |read_ram_rev |364 |251 |81 |211 |0 |0 | +| read_ram_addr |read_ram_addr_rev |297 |212 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |67 |39 |8 |49 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9940 + #2 2 3914 + #3 3 1327 + #4 4 538 + #5 5-10 1208 + #6 11-50 607 + #7 51-100 22 + #8 >500 1 + Average 2.90 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.077175s wall, 3.578125s user + 0.015625s system = 3.593750s CPU (173.0%) + +RUN-1004 : used memory is 1099 MB, reserved memory is 1096 MB, peak memory is 1172 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.604151s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.3%) + +RUN-1004 : used memory is 1103 MB, reserved memory is 1101 MB, peak memory is 1172 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.486056s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (99.9%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1104 MB, peak memory is 1172 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6906 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17653, pip num: 172714 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 565 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 480236 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.682061s wall, 58.875000s user + 0.109375s system = 58.984375s CPU (609.2%) + +RUN-1004 : used memory is 1273 MB, reserved memory is 1269 MB, peak memory is 1388 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_151123.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_152650.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_152650.log new file mode 100644 index 0000000..ba044e4 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_152650.log @@ -0,0 +1,2162 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:26:50 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(763) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(771) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(774) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(945) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1034) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1335) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1346) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1364) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1546) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1942) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.410502s wall, 2.312500s user + 0.093750s system = 2.406250s CPU (99.8%) + +RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u2_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u2_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17752 instances +RUN-0007 : 7412 luts, 9117 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20330 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13386 nets have 2 pins +RUN-1001 : 5497 nets have [3 - 5] pins +RUN-1001 : 1035 nets have [6 - 10] pins +RUN-1001 : 158 nets have [11 - 20] pins +RUN-1001 : 180 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 791 +RUN-1001 : No | No | Yes | 2044 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17750 instances, 7412 luts, 9117 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84963, tnet num: 20152, tinst num: 17750, tnode num: 115271, tedge num: 136352. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.191568s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (99.7%) + +RUN-1004 : used memory is 539 MB, reserved memory is 516 MB, peak memory is 539 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20152 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.989386s wall, 1.875000s user + 0.109375s system = 1.984375s CPU (99.7%) + +PHY-3001 : Found 1218 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.13451e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17750. +PHY-3001 : Level 1 #clusters 2036. +PHY-3001 : End clustering; 0.128196s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.5%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.29668e+06, overlap = 498.375 +PHY-3002 : Step(2): len = 1.20862e+06, overlap = 541.688 +PHY-3002 : Step(3): len = 830423, overlap = 653.156 +PHY-3002 : Step(4): len = 766733, overlap = 675.812 +PHY-3002 : Step(5): len = 594906, overlap = 785.25 +PHY-3002 : Step(6): len = 532554, overlap = 842.844 +PHY-3002 : Step(7): len = 453300, overlap = 932.281 +PHY-3002 : Step(8): len = 419118, overlap = 998.625 +PHY-3002 : Step(9): len = 372626, overlap = 1075.41 +PHY-3002 : Step(10): len = 341527, overlap = 1098.22 +PHY-3002 : Step(11): len = 298919, overlap = 1150.06 +PHY-3002 : Step(12): len = 279310, overlap = 1193.19 +PHY-3002 : Step(13): len = 245923, overlap = 1249.94 +PHY-3002 : Step(14): len = 231418, overlap = 1303.28 +PHY-3002 : Step(15): len = 212562, overlap = 1327.47 +PHY-3002 : Step(16): len = 199404, overlap = 1356.69 +PHY-3002 : Step(17): len = 181012, overlap = 1402.03 +PHY-3002 : Step(18): len = 169724, overlap = 1409.81 +PHY-3002 : Step(19): len = 149892, overlap = 1457.56 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.28308e-06 +PHY-3002 : Step(20): len = 146877, overlap = 1401.22 +PHY-3002 : Step(21): len = 177878, overlap = 1323.62 +PHY-3002 : Step(22): len = 184547, overlap = 1243.41 +PHY-3002 : Step(23): len = 188843, overlap = 1140.34 +PHY-3002 : Step(24): len = 186079, overlap = 1098.25 +PHY-3002 : Step(25): len = 188005, overlap = 1089.31 +PHY-3002 : Step(26): len = 189501, overlap = 1087.25 +PHY-3002 : Step(27): len = 189141, overlap = 1069.88 +PHY-3002 : Step(28): len = 187765, overlap = 1065.62 +PHY-3002 : Step(29): len = 184308, overlap = 1067.16 +PHY-3002 : Step(30): len = 184335, overlap = 1068 +PHY-3002 : Step(31): len = 183494, overlap = 1072.22 +PHY-3002 : Step(32): len = 182000, overlap = 1074 +PHY-3002 : Step(33): len = 181602, overlap = 1093.97 +PHY-3002 : Step(34): len = 181809, overlap = 1105.16 +PHY-3002 : Step(35): len = 181545, overlap = 1099.12 +PHY-3002 : Step(36): len = 180088, overlap = 1067.88 +PHY-3002 : Step(37): len = 180945, overlap = 1035.44 +PHY-3002 : Step(38): len = 180524, overlap = 1031.94 +PHY-3002 : Step(39): len = 180752, overlap = 1036.69 +PHY-3002 : Step(40): len = 178006, overlap = 1045.62 +PHY-3002 : Step(41): len = 177015, overlap = 1045.22 +PHY-3002 : Step(42): len = 174932, overlap = 1042.31 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.56617e-06 +PHY-3002 : Step(43): len = 179871, overlap = 1022.66 +PHY-3002 : Step(44): len = 191140, overlap = 993.031 +PHY-3002 : Step(45): len = 197837, overlap = 955.719 +PHY-3002 : Step(46): len = 202657, overlap = 940.188 +PHY-3002 : Step(47): len = 204264, overlap = 931.25 +PHY-3002 : Step(48): len = 204512, overlap = 927.969 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.13233e-06 +PHY-3002 : Step(49): len = 211560, overlap = 918.125 +PHY-3002 : Step(50): len = 226451, overlap = 880 +PHY-3002 : Step(51): len = 236186, overlap = 841.219 +PHY-3002 : Step(52): len = 241719, overlap = 784.625 +PHY-3002 : Step(53): len = 243280, overlap = 754.875 +PHY-3002 : Step(54): len = 243958, overlap = 737.938 +PHY-3002 : Step(55): len = 243705, overlap = 749.719 +PHY-3002 : Step(56): len = 242538, overlap = 725.75 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.02647e-05 +PHY-3002 : Step(57): len = 256349, overlap = 715.844 +PHY-3002 : Step(58): len = 282397, overlap = 621.562 +PHY-3002 : Step(59): len = 298118, overlap = 540 +PHY-3002 : Step(60): len = 304256, overlap = 515.75 +PHY-3002 : Step(61): len = 301834, overlap = 518.062 +PHY-3002 : Step(62): len = 299158, overlap = 481.344 +PHY-3002 : Step(63): len = 293974, overlap = 486.969 +PHY-3002 : Step(64): len = 293757, overlap = 489.062 +PHY-3002 : Step(65): len = 294747, overlap = 489.875 +PHY-3002 : Step(66): len = 295324, overlap = 474.938 +PHY-3002 : Step(67): len = 293905, overlap = 471 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.05293e-05 +PHY-3002 : Step(68): len = 313522, overlap = 437.188 +PHY-3002 : Step(69): len = 325652, overlap = 404.312 +PHY-3002 : Step(70): len = 327942, overlap = 400.094 +PHY-3002 : Step(71): len = 331073, overlap = 392.438 +PHY-3002 : Step(72): len = 330989, overlap = 372.375 +PHY-3002 : Step(73): len = 333419, overlap = 376.875 +PHY-3002 : Step(74): len = 333581, overlap = 380.438 +PHY-3002 : Step(75): len = 333473, overlap = 372.906 +PHY-3002 : Step(76): len = 333265, overlap = 384.781 +PHY-3002 : Step(77): len = 335075, overlap = 365.344 +PHY-3002 : Step(78): len = 334761, overlap = 361.188 +PHY-3002 : Step(79): len = 335309, overlap = 359.625 +PHY-3002 : Step(80): len = 333208, overlap = 369.406 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.10587e-05 +PHY-3002 : Step(81): len = 353639, overlap = 322.312 +PHY-3002 : Step(82): len = 365825, overlap = 315.875 +PHY-3002 : Step(83): len = 365948, overlap = 306.438 +PHY-3002 : Step(84): len = 367318, overlap = 315.5 +PHY-3002 : Step(85): len = 369184, overlap = 299.5 +PHY-3002 : Step(86): len = 372448, overlap = 287.469 +PHY-3002 : Step(87): len = 370244, overlap = 278.188 +PHY-3002 : Step(88): len = 375018, overlap = 279 +PHY-3002 : Step(89): len = 379690, overlap = 288.531 +PHY-3002 : Step(90): len = 382412, overlap = 283.25 +PHY-3002 : Step(91): len = 378844, overlap = 280.969 +PHY-3002 : Step(92): len = 377913, overlap = 281.062 +PHY-3002 : Step(93): len = 378088, overlap = 281.125 +PHY-3002 : Step(94): len = 378859, overlap = 267.406 +PHY-3002 : Step(95): len = 375929, overlap = 251.188 +PHY-3002 : Step(96): len = 375227, overlap = 248.75 +PHY-3002 : Step(97): len = 375470, overlap = 240.875 +PHY-3002 : Step(98): len = 375606, overlap = 236.5 +PHY-3002 : Step(99): len = 373462, overlap = 234.375 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.21173e-05 +PHY-3002 : Step(100): len = 391844, overlap = 211.5 +PHY-3002 : Step(101): len = 400510, overlap = 208.312 +PHY-3002 : Step(102): len = 397152, overlap = 202.594 +PHY-3002 : Step(103): len = 398085, overlap = 198.656 +PHY-3002 : Step(104): len = 401552, overlap = 187.719 +PHY-3002 : Step(105): len = 404403, overlap = 189.469 +PHY-3002 : Step(106): len = 403025, overlap = 187.938 +PHY-3002 : Step(107): len = 404618, overlap = 187 +PHY-3002 : Step(108): len = 407232, overlap = 181.5 +PHY-3002 : Step(109): len = 408931, overlap = 180.906 +PHY-3002 : Step(110): len = 408322, overlap = 193.344 +PHY-3002 : Step(111): len = 408419, overlap = 195.969 +PHY-3002 : Step(112): len = 408744, overlap = 197.062 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000164235 +PHY-3002 : Step(113): len = 422104, overlap = 187.719 +PHY-3002 : Step(114): len = 430192, overlap = 180.438 +PHY-3002 : Step(115): len = 430626, overlap = 186.469 +PHY-3002 : Step(116): len = 431399, overlap = 184.906 +PHY-3002 : Step(117): len = 432087, overlap = 180.438 +PHY-3002 : Step(118): len = 433506, overlap = 175.625 +PHY-3002 : Step(119): len = 434279, overlap = 179.594 +PHY-3002 : Step(120): len = 437289, overlap = 176.469 +PHY-3002 : Step(121): len = 438828, overlap = 183 +PHY-3002 : Step(122): len = 439280, overlap = 179.594 +PHY-3002 : Step(123): len = 438960, overlap = 180.812 +PHY-3002 : Step(124): len = 440630, overlap = 176.656 +PHY-3002 : Step(125): len = 440646, overlap = 175.531 +PHY-3002 : Step(126): len = 441317, overlap = 177.625 +PHY-3002 : Step(127): len = 440515, overlap = 170.875 +PHY-3002 : Step(128): len = 441071, overlap = 172.969 +PHY-3002 : Step(129): len = 440967, overlap = 173.688 +PHY-3002 : Step(130): len = 441484, overlap = 173.344 +PHY-3002 : Step(131): len = 440797, overlap = 173.594 +PHY-3002 : Step(132): len = 441311, overlap = 174.656 +PHY-3002 : Step(133): len = 440972, overlap = 168.969 +PHY-3002 : Step(134): len = 441289, overlap = 164 +PHY-3002 : Step(135): len = 441764, overlap = 174.781 +PHY-3002 : Step(136): len = 442649, overlap = 169.75 +PHY-3002 : Step(137): len = 441950, overlap = 176.281 +PHY-3002 : Step(138): len = 441912, overlap = 177.625 +PHY-3002 : Step(139): len = 441566, overlap = 173.375 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000325394 +PHY-3002 : Step(140): len = 450867, overlap = 170.625 +PHY-3002 : Step(141): len = 458108, overlap = 168.531 +PHY-3002 : Step(142): len = 459708, overlap = 168.688 +PHY-3002 : Step(143): len = 460716, overlap = 165.344 +PHY-3002 : Step(144): len = 462441, overlap = 160.094 +PHY-3002 : Step(145): len = 464123, overlap = 162.188 +PHY-3002 : Step(146): len = 464166, overlap = 162.219 +PHY-3002 : Step(147): len = 464704, overlap = 168.219 +PHY-3002 : Step(148): len = 465483, overlap = 164.156 +PHY-3002 : Step(149): len = 466067, overlap = 165 +PHY-3002 : Step(150): len = 465497, overlap = 163.281 +PHY-3002 : Step(151): len = 465527, overlap = 165.094 +PHY-3002 : Step(152): len = 465956, overlap = 163.062 +PHY-3002 : Step(153): len = 466153, overlap = 163.25 +PHY-3002 : Step(154): len = 465877, overlap = 163.625 +PHY-3002 : Step(155): len = 465821, overlap = 163.344 +PHY-3002 : Step(156): len = 466149, overlap = 163.719 +PHY-3002 : Step(157): len = 466541, overlap = 162 +PHY-3002 : Step(158): len = 466310, overlap = 162.656 +PHY-3002 : Step(159): len = 466398, overlap = 158.906 +PHY-3002 : Step(160): len = 466813, overlap = 167.031 +PHY-3002 : Step(161): len = 467199, overlap = 170.906 +PHY-3002 : Step(162): len = 467006, overlap = 170.406 +PHY-3002 : Step(163): len = 467049, overlap = 171.875 +PHY-3002 : Step(164): len = 467823, overlap = 172.562 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000606063 +PHY-3002 : Step(165): len = 472864, overlap = 168.781 +PHY-3002 : Step(166): len = 479695, overlap = 165.406 +PHY-3002 : Step(167): len = 480950, overlap = 156.812 +PHY-3002 : Step(168): len = 482004, overlap = 152.25 +PHY-3002 : Step(169): len = 483928, overlap = 150.031 +PHY-3002 : Step(170): len = 485146, overlap = 151.062 +PHY-3002 : Step(171): len = 485056, overlap = 147.781 +PHY-3002 : Step(172): len = 485227, overlap = 149.781 +PHY-3002 : Step(173): len = 486857, overlap = 147 +PHY-3002 : Step(174): len = 488160, overlap = 146.375 +PHY-3002 : Step(175): len = 487858, overlap = 143.906 +PHY-3002 : Step(176): len = 487899, overlap = 144.25 +PHY-3002 : Step(177): len = 488988, overlap = 143.594 +PHY-3002 : Step(178): len = 489500, overlap = 140.438 +PHY-3002 : Step(179): len = 489355, overlap = 142.062 +PHY-3002 : Step(180): len = 489444, overlap = 138.844 +PHY-3002 : Step(181): len = 490520, overlap = 141.219 +PHY-3002 : Step(182): len = 491553, overlap = 142.031 +PHY-3002 : Step(183): len = 491742, overlap = 142.062 +PHY-3002 : Step(184): len = 491896, overlap = 142.969 +PHY-3002 : Step(185): len = 492289, overlap = 145.75 +PHY-3002 : Step(186): len = 492379, overlap = 145.625 +PHY-3002 : Step(187): len = 492383, overlap = 148.5 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00101035 +PHY-3002 : Step(188): len = 495608, overlap = 148.969 +PHY-3002 : Step(189): len = 500866, overlap = 147.312 +PHY-3002 : Step(190): len = 502515, overlap = 154.719 +PHY-3002 : Step(191): len = 503256, overlap = 154.469 +PHY-3002 : Step(192): len = 504084, overlap = 149.875 +PHY-3002 : Step(193): len = 504487, overlap = 146 +PHY-3002 : Step(194): len = 504759, overlap = 145.406 +PHY-3002 : Step(195): len = 505356, overlap = 141.344 +PHY-3002 : Step(196): len = 506338, overlap = 145.062 +PHY-3002 : Step(197): len = 506960, overlap = 145.719 +PHY-3002 : Step(198): len = 507461, overlap = 148.781 +PHY-3002 : Step(199): len = 508259, overlap = 147.219 +PHY-3002 : Step(200): len = 508926, overlap = 145.688 +PHY-3002 : Step(201): len = 509216, overlap = 145.656 +PHY-3002 : Step(202): len = 509527, overlap = 145.688 +PHY-3002 : Step(203): len = 510007, overlap = 150.969 +PHY-3002 : Step(204): len = 510430, overlap = 148.312 +PHY-3002 : Step(205): len = 510595, overlap = 148.188 +PHY-3002 : Step(206): len = 510660, overlap = 147.594 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00167078 +PHY-3002 : Step(207): len = 513698, overlap = 146.844 +PHY-3002 : Step(208): len = 519489, overlap = 155.281 +PHY-3002 : Step(209): len = 520765, overlap = 153 +PHY-3002 : Step(210): len = 521457, overlap = 147.656 +PHY-3002 : Step(211): len = 522503, overlap = 144.844 +PHY-3002 : Step(212): len = 523396, overlap = 143.906 +PHY-3002 : Step(213): len = 523970, overlap = 145.188 +PHY-3002 : Step(214): len = 524787, overlap = 145.125 +PHY-3002 : Step(215): len = 525929, overlap = 146.594 +PHY-3002 : Step(216): len = 526589, overlap = 146.906 +PHY-3002 : Step(217): len = 526799, overlap = 147.656 +PHY-3002 : Step(218): len = 526934, overlap = 147.656 +PHY-3002 : Step(219): len = 527120, overlap = 148.094 +PHY-3002 : Step(220): len = 527273, overlap = 148.094 +PHY-3002 : Step(221): len = 527677, overlap = 142.062 +PHY-3002 : Step(222): len = 528668, overlap = 133.031 +PHY-3002 : Step(223): len = 529075, overlap = 132.719 +PHY-3002 : Step(224): len = 529282, overlap = 132.594 +PHY-3002 : Step(225): len = 529548, overlap = 137.719 +PHY-3002 : Step(226): len = 529763, overlap = 138.562 +PHY-3002 : Step(227): len = 530173, overlap = 129.781 +PHY-3002 : Step(228): len = 530662, overlap = 127.844 +PHY-3002 : Step(229): len = 530940, overlap = 131.469 +PHY-3002 : Step(230): len = 530940, overlap = 131.469 +PHY-3002 : Step(231): len = 530953, overlap = 133.25 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00286093 +PHY-3002 : Step(232): len = 533238, overlap = 127.312 +PHY-3002 : Step(233): len = 538009, overlap = 126.094 +PHY-3002 : Step(234): len = 539343, overlap = 125.594 +PHY-3002 : Step(235): len = 540569, overlap = 122.156 +PHY-3002 : Step(236): len = 541846, overlap = 124.438 +PHY-3002 : Step(237): len = 542527, overlap = 123.062 +PHY-3002 : Step(238): len = 542841, overlap = 124.031 +PHY-3002 : Step(239): len = 543304, overlap = 119.656 +PHY-3002 : Step(240): len = 544211, overlap = 117.688 +PHY-3002 : Step(241): len = 544626, overlap = 117.688 +PHY-3002 : Step(242): len = 545003, overlap = 117.156 +PHY-3002 : Step(243): len = 545268, overlap = 118.219 +PHY-3002 : Step(244): len = 545741, overlap = 115.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.014207s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (110.0%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20330. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 708872, over cnt = 1587(4%), over = 7097, worst = 45 +PHY-1001 : End global iterations; 0.693570s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (139.7%) + +PHY-1001 : Congestion index: top1 = 77.54, top5 = 59.32, top10 = 50.70, top15 = 45.54. +PHY-3001 : End congestion estimation; 0.908505s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (129.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20152 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.856448s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.3%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000149725 +PHY-3002 : Step(245): len = 641248, overlap = 79.9688 +PHY-3002 : Step(246): len = 639620, overlap = 76.125 +PHY-3002 : Step(247): len = 630833, overlap = 71.5312 +PHY-3002 : Step(248): len = 628031, overlap = 64.6875 +PHY-3002 : Step(249): len = 629711, overlap = 53.3438 +PHY-3002 : Step(250): len = 629036, overlap = 48.25 +PHY-3002 : Step(251): len = 626235, overlap = 41.625 +PHY-3002 : Step(252): len = 623557, overlap = 41.0938 +PHY-3002 : Step(253): len = 622308, overlap = 34.4062 +PHY-3002 : Step(254): len = 620448, overlap = 33.7188 +PHY-3002 : Step(255): len = 618163, overlap = 34.25 +PHY-3002 : Step(256): len = 616369, overlap = 36.9062 +PHY-3002 : Step(257): len = 614681, overlap = 36.7188 +PHY-3002 : Step(258): len = 613587, overlap = 38.2812 +PHY-3002 : Step(259): len = 612572, overlap = 37 +PHY-3002 : Step(260): len = 611443, overlap = 36.75 +PHY-3002 : Step(261): len = 610540, overlap = 37.5938 +PHY-3002 : Step(262): len = 608105, overlap = 38.25 +PHY-3002 : Step(263): len = 606362, overlap = 38.4062 +PHY-3002 : Step(264): len = 604444, overlap = 39.0938 +PHY-3002 : Step(265): len = 602320, overlap = 41.5625 +PHY-3002 : Step(266): len = 601601, overlap = 43.0938 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00029945 +PHY-3002 : Step(267): len = 603683, overlap = 44.75 +PHY-3002 : Step(268): len = 606381, overlap = 44.8438 +PHY-3002 : Step(269): len = 610731, overlap = 45.9062 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000534931 +PHY-3002 : Step(270): len = 619067, overlap = 46.4062 +PHY-3002 : Step(271): len = 633757, overlap = 40.25 +PHY-3002 : Step(272): len = 641012, overlap = 36.8125 +PHY-3002 : Step(273): len = 638931, overlap = 37.8438 +PHY-3002 : Step(274): len = 637314, overlap = 41.1562 +PHY-3002 : Step(275): len = 634912, overlap = 40.375 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 82/20330. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 723128, over cnt = 2648(7%), over = 11246, worst = 29 +PHY-1001 : End global iterations; 1.673458s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (130.7%) + +PHY-1001 : Congestion index: top1 = 82.44, top5 = 64.23, top10 = 56.01, top15 = 51.42. +PHY-3001 : End congestion estimation; 1.933166s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (126.9%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20152 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.882406s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123765 +PHY-3002 : Step(276): len = 629203, overlap = 234.438 +PHY-3002 : Step(277): len = 627399, overlap = 177.406 +PHY-3002 : Step(278): len = 617225, overlap = 165.406 +PHY-3002 : Step(279): len = 610749, overlap = 152.781 +PHY-3002 : Step(280): len = 604532, overlap = 140.062 +PHY-3002 : Step(281): len = 601488, overlap = 131.5 +PHY-3002 : Step(282): len = 596916, overlap = 127.438 +PHY-3002 : Step(283): len = 593491, overlap = 125.406 +PHY-3002 : Step(284): len = 590752, overlap = 123.031 +PHY-3002 : Step(285): len = 587648, overlap = 120.656 +PHY-3002 : Step(286): len = 584070, overlap = 123.812 +PHY-3002 : Step(287): len = 583042, overlap = 124.188 +PHY-3002 : Step(288): len = 580447, overlap = 123.719 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000247531 +PHY-3002 : Step(289): len = 581277, overlap = 119.844 +PHY-3002 : Step(290): len = 584142, overlap = 112.031 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000422689 +PHY-3002 : Step(291): len = 586141, overlap = 107.656 +PHY-3002 : Step(292): len = 592794, overlap = 99.5312 +PHY-3002 : Step(293): len = 598766, overlap = 93.7188 +PHY-3002 : Step(294): len = 598273, overlap = 93.3438 +PHY-3002 : Step(295): len = 598463, overlap = 87.2188 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000779392 +PHY-3002 : Step(296): len = 601927, overlap = 80.3438 +PHY-3002 : Step(297): len = 606811, overlap = 79.7188 +PHY-3002 : Step(298): len = 612474, overlap = 74.4062 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84963, tnet num: 20152, tinst num: 17750, tnode num: 115271, tedge num: 136352. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.436145s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (100.1%) + +RUN-1004 : used memory is 583 MB, reserved memory is 565 MB, peak memory is 719 MB +OPT-1001 : Total overflow 410.84 peak overflow 2.31 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 777/20330. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 711208, over cnt = 2929(8%), over = 10475, worst = 29 +PHY-1001 : End global iterations; 1.226154s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (146.5%) + +PHY-1001 : Congestion index: top1 = 66.34, top5 = 55.13, top10 = 49.78, top15 = 46.37. +PHY-1001 : End incremental global routing; 1.562860s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (136.0%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20152 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.935420s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.2%) + +OPT-1001 : 50 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17615 has valid locations, 322 needs to be replaced +PHY-3001 : design contains 18022 instances, 7499 luts, 9302 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6089 pins +PHY-3001 : Found 1225 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 636288 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16633/20602. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 727432, over cnt = 2982(8%), over = 10494, worst = 29 +PHY-1001 : End global iterations; 0.246820s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (113.9%) + +PHY-1001 : Congestion index: top1 = 66.42, top5 = 55.34, top10 = 49.97, top15 = 46.60. +PHY-3001 : End congestion estimation; 0.498602s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (109.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86089, tnet num: 20424, tinst num: 18022, tnode num: 116984, tedge num: 138060. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.469054s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.0%) + +RUN-1004 : used memory is 626 MB, reserved memory is 621 MB, peak memory is 722 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20424 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.428369s wall, 2.390625s user + 0.046875s system = 2.437500s CPU (100.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(299): len = 635335, overlap = 0 +PHY-3002 : Step(300): len = 634912, overlap = 0 +PHY-3002 : Step(301): len = 634677, overlap = 0 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16753/20602. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 724968, over cnt = 2983(8%), over = 10600, worst = 29 +PHY-1001 : End global iterations; 0.188114s wall, 0.250000s user + 0.031250s system = 0.281250s CPU (149.5%) + +PHY-1001 : Congestion index: top1 = 67.50, top5 = 55.71, top10 = 50.29, top15 = 46.87. +PHY-3001 : End congestion estimation; 0.450544s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (121.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20424 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.019743s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (99.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000416343 +PHY-3002 : Step(302): len = 634391, overlap = 76.1562 +PHY-3002 : Step(303): len = 634312, overlap = 76.0938 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000832686 +PHY-3002 : Step(304): len = 634602, overlap = 76.2188 +PHY-3002 : Step(305): len = 635114, overlap = 76 +PHY-3001 : Final: Len = 635114, Over = 76 +PHY-3001 : End incremental placement; 5.037353s wall, 5.171875s user + 0.234375s system = 5.406250s CPU (107.3%) + +OPT-1001 : Total overflow 417.03 peak overflow 2.31 +OPT-1001 : End high-fanout net optimization; 8.218311s wall, 8.984375s user + 0.265625s system = 9.250000s CPU (112.6%) + +OPT-1001 : Current memory(MB): used = 725, reserve = 712, peak = 741. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16681/20602. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 726392, over cnt = 2939(8%), over = 9630, worst = 29 +PHY-1002 : len = 776456, over cnt = 1942(5%), over = 4637, worst = 20 +PHY-1002 : len = 812376, over cnt = 862(2%), over = 1864, worst = 18 +PHY-1002 : len = 837472, over cnt = 207(0%), over = 412, worst = 15 +PHY-1002 : len = 843048, over cnt = 34(0%), over = 61, worst = 7 +PHY-1001 : End global iterations; 1.733051s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (134.3%) + +PHY-1001 : Congestion index: top1 = 56.83, top5 = 50.28, top10 = 46.51, top15 = 44.16. +OPT-1001 : End congestion update; 2.009482s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (129.9%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20424 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.815558s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (99.6%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 118 cells processed and 15150 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 63 cells processed and 5318 slack improved +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 950 slack improved +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 696 slack improved +OPT-1001 : End bottleneck based optimization; 3.246558s wall, 3.828125s user + 0.015625s system = 3.843750s CPU (118.4%) + +OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 741. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16701/20607. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 843904, over cnt = 131(0%), over = 199, worst = 7 +PHY-1002 : len = 843976, over cnt = 72(0%), over = 92, worst = 7 +PHY-1002 : len = 844624, over cnt = 25(0%), over = 25, worst = 1 +PHY-1002 : len = 844880, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 845024, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.756065s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (109.5%) + +PHY-1001 : Congestion index: top1 = 56.25, top5 = 49.85, top10 = 46.23, top15 = 43.94. +OPT-1001 : End congestion update; 1.093337s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20429 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 1.202020s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (67.6%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 3250 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.407330s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (86.3%) + +OPT-1001 : Current memory(MB): used = 714, reserve = 702, peak = 741. +OPT-1001 : End physical optimization; 15.618525s wall, 16.671875s user + 0.328125s system = 17.000000s CPU (108.8%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7499 LUT to BLE ... +SYN-4008 : Packed 7499 LUT and 3133 SEQ to BLE. +SYN-4003 : Packing 6174 remaining SEQ's ... +SYN-4005 : Packed 3809 SEQ with LUT/SLICE +SYN-4006 : 856 single LUT's are left +SYN-4006 : 2365 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9864/13749 primitive instances ... +PHY-3001 : End packing; 1.616332s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.5%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6852 instances +RUN-1001 : 3352 mslices, 3352 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17603 nets +RUN-6002 WARNING: There are 2 undriven nets. +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 10022 nets have 2 pins +RUN-1001 : 5755 nets have [3 - 5] pins +RUN-1001 : 1142 nets have [6 - 10] pins +RUN-1001 : 304 nets have [11 - 20] pins +RUN-1001 : 348 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6850 instances, 6704 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3619 pins +PHY-3001 : Found 494 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 644886, Over = 256.75 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 7517/17603. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 794184, over cnt = 1938(5%), over = 3245, worst = 8 +PHY-1002 : len = 802096, over cnt = 1241(3%), over = 1837, worst = 8 +PHY-1002 : len = 812960, over cnt = 682(1%), over = 959, worst = 8 +PHY-1002 : len = 823096, over cnt = 267(0%), over = 360, worst = 5 +PHY-1002 : len = 829912, over cnt = 27(0%), over = 37, worst = 5 +PHY-1001 : End global iterations; 1.595358s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (132.2%) + +PHY-1001 : Congestion index: top1 = 57.16, top5 = 50.04, top10 = 46.23, top15 = 43.78. +PHY-3001 : End congestion estimation; 1.991645s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (125.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73964, tnet num: 17425, tinst num: 6850, tnode num: 96626, tedge num: 124147. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.623445s wall, 1.593750s user + 0.031250s system = 1.625000s CPU (100.1%) + +RUN-1004 : used memory is 621 MB, reserved memory is 614 MB, peak memory is 741 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17425 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.499353s wall, 2.453125s user + 0.046875s system = 2.500000s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.04659e-05 +PHY-3002 : Step(306): len = 632281, overlap = 258.75 +PHY-3002 : Step(307): len = 625056, overlap = 255.75 +PHY-3002 : Step(308): len = 620249, overlap = 259.5 +PHY-3002 : Step(309): len = 617163, overlap = 266.25 +PHY-3002 : Step(310): len = 614797, overlap = 269.25 +PHY-3002 : Step(311): len = 612499, overlap = 268.25 +PHY-3002 : Step(312): len = 609844, overlap = 268.75 +PHY-3002 : Step(313): len = 608081, overlap = 261.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100932 +PHY-3002 : Step(314): len = 611423, overlap = 244.75 +PHY-3002 : Step(315): len = 615397, overlap = 235.75 +PHY-3002 : Step(316): len = 615684, overlap = 234.5 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000196323 +PHY-3002 : Step(317): len = 624974, overlap = 223.25 +PHY-3002 : Step(318): len = 635950, overlap = 212.25 +PHY-3002 : Step(319): len = 636323, overlap = 201.25 +PHY-3002 : Step(320): len = 636310, overlap = 205.5 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.386176s wall, 0.421875s user + 0.609375s system = 1.031250s CPU (267.0%) + +PHY-3001 : Trial Legalized: Len = 721114 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 693/17603. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 840032, over cnt = 2658(7%), over = 4505, worst = 8 +PHY-1002 : len = 857024, over cnt = 1585(4%), over = 2400, worst = 8 +PHY-1002 : len = 875592, over cnt = 639(1%), over = 941, worst = 8 +PHY-1002 : len = 882632, over cnt = 365(1%), over = 506, worst = 7 +PHY-1002 : len = 892680, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.383133s wall, 3.406250s user + 0.046875s system = 3.453125s CPU (144.9%) + +PHY-1001 : Congestion index: top1 = 54.96, top5 = 49.48, top10 = 46.65, top15 = 44.72. +PHY-3001 : End congestion estimation; 2.843759s wall, 3.843750s user + 0.046875s system = 3.890625s CPU (136.8%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17425 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.859049s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163716 +PHY-3002 : Step(321): len = 691556, overlap = 45 +PHY-3002 : Step(322): len = 675220, overlap = 73 +PHY-3002 : Step(323): len = 662721, overlap = 98 +PHY-3002 : Step(324): len = 654311, overlap = 115 +PHY-3002 : Step(325): len = 649034, overlap = 132.25 +PHY-3002 : Step(326): len = 645569, overlap = 146 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000327433 +PHY-3002 : Step(327): len = 650732, overlap = 139.5 +PHY-3002 : Step(328): len = 656671, overlap = 139.75 +PHY-3002 : Step(329): len = 658604, overlap = 142.5 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000654866 +PHY-3002 : Step(330): len = 663207, overlap = 140.5 +PHY-3002 : Step(331): len = 675628, overlap = 136 +PHY-3002 : Step(332): len = 678749, overlap = 142 +PHY-3002 : Step(333): len = 680933, overlap = 146 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.034451s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.7%) + +PHY-3001 : Legalized: Len = 712030, Over = 0 +PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.102042s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (91.9%) + +PHY-3001 : 651 instances has been re-located, deltaX = 214, deltaY = 367, maxDist = 3. +PHY-3001 : Final: Len = 722246, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73964, tnet num: 17425, tinst num: 6853, tnode num: 96626, tedge num: 124147. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.847331s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.7%) + +RUN-1004 : used memory is 634 MB, reserved memory is 641 MB, peak memory is 741 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 3610/17603. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 853480, over cnt = 2507(7%), over = 4055, worst = 7 +PHY-1002 : len = 867416, over cnt = 1503(4%), over = 2170, worst = 7 +PHY-1002 : len = 886152, over cnt = 510(1%), over = 688, worst = 5 +PHY-1002 : len = 893472, over cnt = 150(0%), over = 202, worst = 4 +PHY-1002 : len = 896960, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.997102s wall, 2.921875s user + 0.046875s system = 2.968750s CPU (148.7%) + +PHY-1001 : Congestion index: top1 = 52.61, top5 = 47.97, top10 = 45.29, top15 = 43.51. +PHY-1001 : End incremental global routing; 2.375470s wall, 3.312500s user + 0.046875s system = 3.359375s CPU (141.4%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17425 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.877690s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.7%) + +OPT-1001 : 6 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6759 has valid locations, 28 needs to be replaced +PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 726795 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16049/17623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 901768, over cnt = 90(0%), over = 104, worst = 4 +PHY-1002 : len = 901888, over cnt = 38(0%), over = 38, worst = 1 +PHY-1002 : len = 902208, over cnt = 11(0%), over = 11, worst = 1 +PHY-1002 : len = 902368, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 902400, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.836024s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (102.8%) + +PHY-1001 : Congestion index: top1 = 52.91, top5 = 48.12, top10 = 45.41, top15 = 43.64. +PHY-3001 : End congestion estimation; 1.155949s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (102.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74187, tnet num: 17445, tinst num: 6875, tnode num: 96902, tedge num: 124432. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.859241s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (100.0%) + +RUN-1004 : used memory is 692 MB, reserved memory is 687 MB, peak memory is 741 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.755083s wall, 2.718750s user + 0.031250s system = 2.750000s CPU (99.8%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(334): len = 725851, overlap = 0 +PHY-3002 : Step(335): len = 725414, overlap = 0 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16042/17623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 900856, over cnt = 78(0%), over = 97, worst = 4 +PHY-1002 : len = 901088, over cnt = 34(0%), over = 38, worst = 4 +PHY-1002 : len = 901320, over cnt = 6(0%), over = 6, worst = 1 +PHY-1002 : len = 901440, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.600870s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.4%) + +PHY-1001 : Congestion index: top1 = 52.67, top5 = 48.05, top10 = 45.39, top15 = 43.62. +PHY-3001 : End congestion estimation; 0.911833s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.015599s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000620034 +PHY-3002 : Step(336): len = 725351, overlap = 1.25 +PHY-3002 : Step(337): len = 725138, overlap = 1.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005748s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 725426, Over = 0 +PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059553s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.7%) + +PHY-3001 : 3 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1. +PHY-3001 : Final: Len = 725478, Over = 0 +PHY-3001 : End incremental placement; 6.318475s wall, 6.437500s user + 0.171875s system = 6.609375s CPU (104.6%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 10.058432s wall, 11.218750s user + 0.218750s system = 11.437500s CPU (113.7%) + +OPT-1001 : Current memory(MB): used = 750, reserve = 741, peak = 753. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16031/17623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 901200, over cnt = 71(0%), over = 84, worst = 3 +PHY-1002 : len = 901392, over cnt = 37(0%), over = 42, worst = 2 +PHY-1002 : len = 901688, over cnt = 12(0%), over = 16, worst = 2 +PHY-1002 : len = 901816, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.595730s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (107.5%) + +PHY-1001 : Congestion index: top1 = 52.76, top5 = 48.05, top10 = 45.38, top15 = 43.60. +OPT-1001 : End congestion update; 0.910298s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (103.0%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.717847s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%) + +OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 731702, Over = 0 +PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061780s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%) + +PHY-3001 : 28 instances has been re-located, deltaX = 24, deltaY = 17, maxDist = 3. +PHY-3001 : Final: Len = 732542, Over = 0 +PHY-3001 : End incremental legalization; 0.418512s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.8%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 52 cells processed and 16093 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 734062, Over = 0 +PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060584s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.2%) + +PHY-3001 : 18 instances has been re-located, deltaX = 10, deltaY = 15, maxDist = 3. +PHY-3001 : Final: Len = 734502, Over = 0 +PHY-3001 : End incremental legalization; 0.383669s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (101.8%) + +OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 23 cells processed and 5635 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6790 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6878 instances, 6729 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 734798, Over = 0 +PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060149s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.9%) + +PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1. +PHY-3001 : Final: Len = 734806, Over = 0 +PHY-3001 : End incremental legalization; 0.418780s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.0%) + +OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 3 cells processed and 530 slack improved +OPT-1001 : End bottleneck based optimization; 3.321202s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (103.5%) + +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 15670/17626. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 911528, over cnt = 192(0%), over = 257, worst = 6 +PHY-1002 : len = 912136, over cnt = 86(0%), over = 95, worst = 3 +PHY-1002 : len = 912808, over cnt = 30(0%), over = 32, worst = 2 +PHY-1002 : len = 912952, over cnt = 21(0%), over = 21, worst = 1 +PHY-1002 : len = 913264, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.838105s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (106.3%) + +PHY-1001 : Congestion index: top1 = 52.28, top5 = 47.98, top10 = 45.39, top15 = 43.66. +OPT-1001 : End congestion update; 1.162496s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (104.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.753217s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.6%) + +OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6790 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6878 instances, 6729 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 734878, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.058837s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%) + +PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 8, maxDist = 2. +PHY-3001 : Final: Len = 735176, Over = 0 +PHY-3001 : End incremental legalization; 0.378253s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.1%) + +OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 14 cells processed and 1050 slack improved +OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.430035s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (102.2%) + +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.724881s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.2%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16026/17626. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 913544, over cnt = 48(0%), over = 50, worst = 2 +PHY-1002 : len = 913400, over cnt = 31(0%), over = 32, worst = 2 +PHY-1002 : len = 913664, over cnt = 8(0%), over = 8, worst = 1 +PHY-1002 : len = 913792, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.813495s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.9%) + +PHY-1001 : Congestion index: top1 = 52.48, top5 = 48.05, top10 = 45.38, top15 = 43.65. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.719880s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.8%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 71 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.034483 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 71ps with logic level 1 +RUN-1001 : extra opt step will be enabled to improve QoR +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6790 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6878 instances, 6729 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 500 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 735176, Over = 0 +PHY-3001 : End spreading; 0.058772s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%) + +PHY-3001 : Final: Len = 735176, Over = 0 +PHY-3001 : End incremental legalization; 0.384219s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (134.2%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.727285s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.0%) + +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16068/17626. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.135700s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%) + +PHY-1001 : Congestion index: top1 = 52.48, top5 = 48.05, top10 = 45.38, top15 = 43.65. +OPT-1001 : End congestion update; 0.447892s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.7%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.901256s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.6%) + +OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.360494s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.9%) + +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16068/17626. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.134481s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.6%) + +PHY-1001 : Congestion index: top1 = 52.48, top5 = 48.05, top10 = 45.38, top15 = 43.65. +OPT-1001 : End congestion update; 0.449155s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.4%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.898834s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.8%) + +OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End bottleneck based optimization; 1.507315s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (99.5%) + +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.902586s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.4%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : Start congestion recovery ... +RUN-1002 : start command "set_param place ofv 80" +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17446 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.907723s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.8%) + +RUN-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Reuse net number 16068/17626. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.144712s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.2%) + +PHY-1001 : Congestion index: top1 = 52.48, top5 = 48.05, top10 = 45.38, top15 = 43.65. +RUN-1001 : End congestion update; 0.492614s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.5%) + +RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952 +OPT-1001 : End congestion recovery; 1.403628s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.2%) + +OPT-1001 : Current memory(MB): used = 751, reserve = 741, peak = 754. +OPT-1001 : End physical optimization; 26.931276s wall, 28.343750s user + 0.265625s system = 28.609375s CPU (106.2%) + +RUN-1003 : finish command "place" in 72.142155s wall, 99.578125s user + 6.656250s system = 106.234375s CPU (147.3%) + +RUN-1004 : used memory is 661 MB, reserved memory is 646 MB, peak memory is 754 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.712440s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (172.5%) + +RUN-1004 : used memory is 661 MB, reserved memory is 647 MB, peak memory is 754 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6880 instances +RUN-1001 : 3366 mslices, 3363 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17626 nets +RUN-6002 WARNING: There are 2 undriven nets. +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 10011 nets have 2 pins +RUN-1001 : 5762 nets have [3 - 5] pins +RUN-1001 : 1147 nets have [6 - 10] pins +RUN-1001 : 313 nets have [11 - 20] pins +RUN-1001 : 365 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74223, tnet num: 17448, tinst num: 6878, tnode num: 96949, tedge num: 124479. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.602261s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%) + +RUN-1004 : used memory is 672 MB, reserved memory is 667 MB, peak memory is 754 MB +PHY-1001 : 3366 mslices, 3363 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17448 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[28] is skipped due to 0 input or output +PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 846472, over cnt = 2680(7%), over = 4407, worst = 8 +PHY-1002 : len = 863776, over cnt = 1658(4%), over = 2390, worst = 8 +PHY-1002 : len = 884872, over cnt = 497(1%), over = 699, worst = 7 +PHY-1002 : len = 896184, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 896392, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.857664s wall, 4.078125s user + 0.031250s system = 4.109375s CPU (143.8%) + +PHY-1001 : Congestion index: top1 = 52.44, top5 = 47.52, top10 = 44.97, top15 = 43.25. +PHY-1001 : End global routing; 3.186258s wall, 4.390625s user + 0.046875s system = 4.437500s CPU (139.3%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 724, reserve = 720, peak = 754. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-5010 Similar messages will be suppressed. +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 998, reserve = 995, peak = 998. +PHY-1001 : End build detailed router design. 4.040437s wall, 4.000000s user + 0.015625s system = 4.015625s CPU (99.4%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 264448, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 4.984964s wall, 4.984375s user + 0.000000s system = 4.984375s CPU (100.0%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 264504, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.439998s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.4%) + +PHY-1001 : Current memory(MB): used = 1034, reserve = 1032, peak = 1034. +PHY-1001 : End phase 1; 5.437970s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (100.0%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 45% nets. +PHY-1001 : Routed 52% nets. +PHY-1001 : Routed 61% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.30799e+06, over cnt = 1851(0%), over = 1861, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1050, reserve = 1044, peak = 1050. +PHY-1001 : End initial routed; 23.772016s wall, 57.015625s user + 0.265625s system = 57.281250s CPU (241.0%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16547(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.664 | -0.664 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.332304s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.9%) + +PHY-1001 : Current memory(MB): used = 1058, reserve = 1053, peak = 1058. +PHY-1001 : End phase 2; 27.104379s wall, 60.343750s user + 0.265625s system = 60.609375s CPU (223.6%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.137400s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.0%) + +PHY-1022 : len = 2.30799e+06, over cnt = 1851(0%), over = 1861, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.404244s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.5%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.27812e+06, over cnt = 658(0%), over = 658, worst = 1, crit = 0 +PHY-1001 : End DR Iter 1; 1.298544s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (168.5%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.27471e+06, over cnt = 91(0%), over = 91, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.877446s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (126.4%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.2753e+06, over cnt = 19(0%), over = 19, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.286962s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (119.8%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.27522e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.212126s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.8%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.27524e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 5; 0.172810s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.5%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16547(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.661 | -0.661 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.397397s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (100.3%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 415 nets +PHY-1001 : End commit to database; 2.266752s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1160, reserve = 1159, peak = 1160. +PHY-1001 : End phase 3; 9.318319s wall, 10.468750s user + 0.015625s system = 10.484375s CPU (112.5%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.144857s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.1%) + +PHY-1022 : len = 2.27524e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.410165s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.0%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16547(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.661 | -0.661 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.282964s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.9%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 415 nets +PHY-1001 : End commit to database; 2.320186s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.3%) + +PHY-1001 : Current memory(MB): used = 1169, reserve = 1169, peak = 1169. +PHY-1001 : End phase 4; 6.045150s wall, 6.046875s user + 0.000000s system = 6.046875s CPU (100.0%) + +PHY-1003 : Routed, final wirelength = 2.27524e+06 +PHY-1001 : Current memory(MB): used = 1171, reserve = 1171, peak = 1171. +PHY-1001 : End export database. 0.064420s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.0%) + +PHY-1001 : End detail routing; 52.418014s wall, 86.781250s user + 0.296875s system = 87.078125s CPU (166.1%) + +RUN-1003 : finish command "route" in 58.279395s wall, 93.843750s user + 0.343750s system = 94.187500s CPU (161.6%) + +RUN-1004 : used memory is 1097 MB, reserved memory is 1094 MB, peak memory is 1171 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10256 out of 19600 52.33% +#reg 9447 out of 19600 48.20% +#le 12547 + #lut only 3100 out of 12547 24.71% + #reg only 2291 out of 12547 18.26% + #lut® 7156 out of 12547 57.03% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1816 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1397 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1357 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1007 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 135 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_298.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg48_syn_242.f1 3 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P146 LVCMOS33 N/A N/A NONE + paper_in INPUT P107 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P140 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE + debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P104 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P173 LVCMOS33 8 N/A NONE + paper_out OUTPUT P83 LVCMOS25 8 N/A NONE + scan_out OUTPUT P32 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P39 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12547 |9229 |1027 |9479 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |434 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |99 |94 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |27 |27 |0 |18 |0 |0 | +| U_ecc_gen |ecc_gen |7 |7 |0 |6 |0 |0 | +| exdev_ctl_a |exdev_ctl |786 |370 |96 |583 |0 |0 | +| u_ADconfig |AD_config |200 |142 |25 |148 |0 |0 | +| u_gen_sp |gen_sp |270 |159 |71 |119 |0 |0 | +| exdev_ctl_b |exdev_ctl |738 |387 |96 |556 |0 |0 | +| u_ADconfig |AD_config |167 |127 |25 |124 |0 |0 | +| u_gen_sp |gen_sp |254 |153 |71 |115 |0 |0 | +| sampling_fe_a |sampling_fe |3032 |2448 |306 |2091 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 | +| u_ad_sampling |ad_sampling |190 |120 |17 |151 |0 |0 | +| u0_soft_n |cdc_sync |8 |6 |0 |8 |0 |0 | +| u_sort |sort |2811 |2314 |289 |1909 |25 |0 | +| rddpram_ctl |rddpram_ctl |5 |2 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 | +| u0_wrsoft_n |cdc_sync |5 |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |2364 |1994 |253 |1556 |22 |0 | +| channelPart |channel_part_8478 |149 |143 |3 |142 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |0 | +| ram_switch |ram_switch |1833 |1528 |197 |1140 |0 |0 | +| adc_addr_gen |adc_addr_gen |216 |184 |27 |118 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |16 |11 |3 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| insert |insert |918 |647 |170 |626 |0 |0 | +| ram_switch_state |ram_switch_state |699 |697 |0 |396 |0 |0 | +| read_ram_i |read_ram |290 |242 |44 |200 |0 |0 | +| read_ram_addr |read_ram_addr |219 |179 |40 |149 |0 |0 | +| read_ram_data |read_ram_data |67 |60 |4 |47 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |346 |239 |36 |280 |3 |0 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3307 |2616 |349 |2071 |25 |1 | +| u0_soft_n |cdc_sync |6 |5 |0 |6 |0 |0 | +| u_ad_sampling |ad_sampling |176 |100 |17 |143 |0 |0 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_sort |sort_rev |3096 |2503 |332 |1893 |25 |1 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2661 |2179 |290 |1547 |22 |1 | +| channelPart |channel_part_8478 |244 |241 |3 |145 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 | +| ram_switch |ram_switch |1970 |1611 |197 |1124 |0 |0 | +| adc_addr_gen |adc_addr_gen |206 |179 |27 |100 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |7 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |14 |11 |3 |4 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 | +| insert |insert |964 |634 |170 |652 |0 |0 | +| ram_switch_state |ram_switch_state |800 |798 |0 |372 |0 |0 | +| read_ram_i |read_ram_rev |355 |247 |81 |203 |0 |0 | +| read_ram_addr |read_ram_addr_rev |289 |204 |73 |156 |0 |0 | +| read_ram_data |read_ram_data_rev |66 |43 |8 |47 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9949 + #2 2 3874 + #3 3 1323 + #4 4 562 + #5 5-10 1206 + #6 11-50 593 + #7 51-100 23 + #8 >500 1 + Average 2.91 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.120583s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (171.7%) + +RUN-1004 : used memory is 1098 MB, reserved memory is 1096 MB, peak memory is 1171 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74223, tnet num: 17448, tinst num: 6878, tnode num: 96949, tedge num: 124479. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.633594s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.4%) + +RUN-1004 : used memory is 1103 MB, reserved memory is 1101 MB, peak memory is 1171 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17448 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.513898s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (99.1%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1103 MB, peak memory is 1171 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6878 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17626, pip num: 172421 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 565 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3253 valid insts, and 478895 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.541638s wall, 57.781250s user + 0.203125s system = 57.984375s CPU (607.7%) + +RUN-1004 : used memory is 1271 MB, reserved memory is 1266 MB, peak memory is 1386 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_152650.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_153553.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_153553.log new file mode 100644 index 0000000..0075ed0 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_153553.log @@ -0,0 +1,2004 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:35:53 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.418542s wall, 2.296875s user + 0.125000s system = 2.421875s CPU (100.1%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17745 instances +RUN-0007 : 7435 luts, 9087 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20323 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13378 nets have 2 pins +RUN-1001 : 5502 nets have [3 - 5] pins +RUN-1001 : 1031 nets have [6 - 10] pins +RUN-1001 : 159 nets have [11 - 20] pins +RUN-1001 : 179 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2012 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17743 instances, 7435 luts, 9087 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5941 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.144737s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.6%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.928969s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.6%) + +PHY-3001 : Found 1219 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.03672e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17743. +PHY-3001 : Level 1 #clusters 2001. +PHY-3001 : End clustering; 0.126114s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (161.1%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28172e+06, overlap = 450.688 +PHY-3002 : Step(2): len = 1.17432e+06, overlap = 496.219 +PHY-3002 : Step(3): len = 856653, overlap = 576.094 +PHY-3002 : Step(4): len = 786084, overlap = 628.906 +PHY-3002 : Step(5): len = 595952, overlap = 759.281 +PHY-3002 : Step(6): len = 521360, overlap = 797.906 +PHY-3002 : Step(7): len = 440616, overlap = 913.812 +PHY-3002 : Step(8): len = 411923, overlap = 929.219 +PHY-3002 : Step(9): len = 368492, overlap = 1011.84 +PHY-3002 : Step(10): len = 344447, overlap = 1045.5 +PHY-3002 : Step(11): len = 308507, overlap = 1078.34 +PHY-3002 : Step(12): len = 283987, overlap = 1137.59 +PHY-3002 : Step(13): len = 260945, overlap = 1173.41 +PHY-3002 : Step(14): len = 239493, overlap = 1234.88 +PHY-3002 : Step(15): len = 224806, overlap = 1281.34 +PHY-3002 : Step(16): len = 206499, overlap = 1315.41 +PHY-3002 : Step(17): len = 190194, overlap = 1348.53 +PHY-3002 : Step(18): len = 172136, overlap = 1365.78 +PHY-3002 : Step(19): len = 161542, overlap = 1372.78 +PHY-3002 : Step(20): len = 146202, overlap = 1401.66 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10457e-06 +PHY-3002 : Step(21): len = 146798, overlap = 1396 +PHY-3002 : Step(22): len = 172633, overlap = 1332.34 +PHY-3002 : Step(23): len = 178535, overlap = 1234.84 +PHY-3002 : Step(24): len = 185020, overlap = 1204.31 +PHY-3002 : Step(25): len = 187522, overlap = 1183.28 +PHY-3002 : Step(26): len = 188298, overlap = 1152.5 +PHY-3002 : Step(27): len = 187442, overlap = 1116.62 +PHY-3002 : Step(28): len = 187095, overlap = 1079.91 +PHY-3002 : Step(29): len = 187618, overlap = 1077.53 +PHY-3002 : Step(30): len = 186342, overlap = 1047.97 +PHY-3002 : Step(31): len = 187852, overlap = 1046.09 +PHY-3002 : Step(32): len = 185978, overlap = 1058.34 +PHY-3002 : Step(33): len = 184677, overlap = 1048.94 +PHY-3002 : Step(34): len = 181811, overlap = 1031.5 +PHY-3002 : Step(35): len = 181702, overlap = 1027.47 +PHY-3002 : Step(36): len = 179387, overlap = 1046.06 +PHY-3002 : Step(37): len = 178992, overlap = 1058.69 +PHY-3002 : Step(38): len = 176523, overlap = 1062.59 +PHY-3002 : Step(39): len = 176436, overlap = 1064.91 +PHY-3002 : Step(40): len = 173457, overlap = 1072.81 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20914e-06 +PHY-3002 : Step(41): len = 177308, overlap = 1065.06 +PHY-3002 : Step(42): len = 190276, overlap = 1080.53 +PHY-3002 : Step(43): len = 194494, overlap = 1081.88 +PHY-3002 : Step(44): len = 197374, overlap = 1069.81 +PHY-3002 : Step(45): len = 198039, overlap = 1057.97 +PHY-3002 : Step(46): len = 198583, overlap = 1045.69 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.41828e-06 +PHY-3002 : Step(47): len = 205524, overlap = 1006.62 +PHY-3002 : Step(48): len = 221752, overlap = 868.594 +PHY-3002 : Step(49): len = 231082, overlap = 802.812 +PHY-3002 : Step(50): len = 239235, overlap = 809.188 +PHY-3002 : Step(51): len = 243212, overlap = 792.156 +PHY-3002 : Step(52): len = 244863, overlap = 759.938 +PHY-3002 : Step(53): len = 244837, overlap = 739.594 +PHY-3002 : Step(54): len = 243958, overlap = 733.281 +PHY-3002 : Step(55): len = 242207, overlap = 716.531 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.83657e-06 +PHY-3002 : Step(56): len = 257674, overlap = 678.75 +PHY-3002 : Step(57): len = 281477, overlap = 595.875 +PHY-3002 : Step(58): len = 290479, overlap = 533.531 +PHY-3002 : Step(59): len = 294876, overlap = 530.156 +PHY-3002 : Step(60): len = 292681, overlap = 540 +PHY-3002 : Step(61): len = 290012, overlap = 548.75 +PHY-3002 : Step(62): len = 286094, overlap = 558.438 +PHY-3002 : Step(63): len = 285239, overlap = 556.75 +PHY-3002 : Step(64): len = 286116, overlap = 564 +PHY-3002 : Step(65): len = 287019, overlap = 557.344 +PHY-3002 : Step(66): len = 286138, overlap = 561.25 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76731e-05 +PHY-3002 : Step(67): len = 304136, overlap = 548.594 +PHY-3002 : Step(68): len = 321073, overlap = 520.75 +PHY-3002 : Step(69): len = 326901, overlap = 462.375 +PHY-3002 : Step(70): len = 328175, overlap = 440.594 +PHY-3002 : Step(71): len = 326166, overlap = 419.219 +PHY-3002 : Step(72): len = 325697, overlap = 391.344 +PHY-3002 : Step(73): len = 325583, overlap = 378.188 +PHY-3002 : Step(74): len = 327742, overlap = 371.938 +PHY-3002 : Step(75): len = 326770, overlap = 377.25 +PHY-3002 : Step(76): len = 326758, overlap = 373.531 +PHY-3002 : Step(77): len = 326655, overlap = 382.125 +PHY-3002 : Step(78): len = 328557, overlap = 385.25 +PHY-3002 : Step(79): len = 327968, overlap = 384.719 +PHY-3002 : Step(80): len = 327971, overlap = 385.906 +PHY-3002 : Step(81): len = 328104, overlap = 396.406 +PHY-3002 : Step(82): len = 328472, overlap = 390.531 +PHY-3002 : Step(83): len = 328239, overlap = 387.719 +PHY-3002 : Step(84): len = 329143, overlap = 393.812 +PHY-3002 : Step(85): len = 327973, overlap = 397.875 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.53463e-05 +PHY-3002 : Step(86): len = 345898, overlap = 359.469 +PHY-3002 : Step(87): len = 359117, overlap = 339.75 +PHY-3002 : Step(88): len = 360816, overlap = 334.688 +PHY-3002 : Step(89): len = 361674, overlap = 334.812 +PHY-3002 : Step(90): len = 361511, overlap = 325.656 +PHY-3002 : Step(91): len = 362609, overlap = 312.125 +PHY-3002 : Step(92): len = 361131, overlap = 312.438 +PHY-3002 : Step(93): len = 361755, overlap = 315.188 +PHY-3002 : Step(94): len = 362466, overlap = 298.281 +PHY-3002 : Step(95): len = 363451, overlap = 296.312 +PHY-3002 : Step(96): len = 361923, overlap = 299.594 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.06925e-05 +PHY-3002 : Step(97): len = 380686, overlap = 280.875 +PHY-3002 : Step(98): len = 393877, overlap = 282.906 +PHY-3002 : Step(99): len = 391804, overlap = 268.094 +PHY-3002 : Step(100): len = 393310, overlap = 250.5 +PHY-3002 : Step(101): len = 394805, overlap = 250.688 +PHY-3002 : Step(102): len = 397473, overlap = 253 +PHY-3002 : Step(103): len = 394544, overlap = 256.438 +PHY-3002 : Step(104): len = 394989, overlap = 257.156 +PHY-3002 : Step(105): len = 396401, overlap = 240.719 +PHY-3002 : Step(106): len = 397811, overlap = 239 +PHY-3002 : Step(107): len = 396411, overlap = 242.188 +PHY-3002 : Step(108): len = 397568, overlap = 223.469 +PHY-3002 : Step(109): len = 399560, overlap = 225.5 +PHY-3002 : Step(110): len = 400464, overlap = 210.938 +PHY-3002 : Step(111): len = 398255, overlap = 214.312 +PHY-3002 : Step(112): len = 398369, overlap = 214.938 +PHY-3002 : Step(113): len = 399100, overlap = 209.25 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141385 +PHY-3002 : Step(114): len = 415646, overlap = 186.344 +PHY-3002 : Step(115): len = 424994, overlap = 208.875 +PHY-3002 : Step(116): len = 421927, overlap = 213.625 +PHY-3002 : Step(117): len = 421730, overlap = 206.906 +PHY-3002 : Step(118): len = 426278, overlap = 188.875 +PHY-3002 : Step(119): len = 429889, overlap = 188 +PHY-3002 : Step(120): len = 426628, overlap = 190.188 +PHY-3002 : Step(121): len = 427999, overlap = 193.25 +PHY-3002 : Step(122): len = 431889, overlap = 189.969 +PHY-3002 : Step(123): len = 435532, overlap = 192.469 +PHY-3002 : Step(124): len = 432226, overlap = 190 +PHY-3002 : Step(125): len = 432069, overlap = 180.531 +PHY-3002 : Step(126): len = 434337, overlap = 182.5 +PHY-3002 : Step(127): len = 436053, overlap = 179.25 +PHY-3002 : Step(128): len = 433744, overlap = 172.312 +PHY-3002 : Step(129): len = 433743, overlap = 176.469 +PHY-3002 : Step(130): len = 435984, overlap = 177.688 +PHY-3002 : Step(131): len = 437181, overlap = 180 +PHY-3002 : Step(132): len = 434829, overlap = 179.125 +PHY-3002 : Step(133): len = 434539, overlap = 181.906 +PHY-3002 : Step(134): len = 436034, overlap = 184.469 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00028277 +PHY-3002 : Step(135): len = 446842, overlap = 173.188 +PHY-3002 : Step(136): len = 456483, overlap = 164.562 +PHY-3002 : Step(137): len = 457435, overlap = 166.531 +PHY-3002 : Step(138): len = 458660, overlap = 169.531 +PHY-3002 : Step(139): len = 462075, overlap = 163.125 +PHY-3002 : Step(140): len = 464987, overlap = 160.781 +PHY-3002 : Step(141): len = 463523, overlap = 163.281 +PHY-3002 : Step(142): len = 463423, overlap = 163.469 +PHY-3002 : Step(143): len = 464548, overlap = 158.156 +PHY-3002 : Step(144): len = 466447, overlap = 164.5 +PHY-3002 : Step(145): len = 466639, overlap = 155.094 +PHY-3002 : Step(146): len = 468136, overlap = 162.219 +PHY-3002 : Step(147): len = 468952, overlap = 161.062 +PHY-3002 : Step(148): len = 469376, overlap = 160.781 +PHY-3002 : Step(149): len = 468182, overlap = 167.469 +PHY-3002 : Step(150): len = 468430, overlap = 166.562 +PHY-3002 : Step(151): len = 469025, overlap = 160.844 +PHY-3002 : Step(152): len = 469376, overlap = 158.219 +PHY-3002 : Step(153): len = 468892, overlap = 157.344 +PHY-3002 : Step(154): len = 469813, overlap = 158.219 +PHY-3002 : Step(155): len = 470872, overlap = 155.562 +PHY-3002 : Step(156): len = 471704, overlap = 155.844 +PHY-3002 : Step(157): len = 470506, overlap = 155.469 +PHY-3002 : Step(158): len = 470267, overlap = 156.344 +PHY-3002 : Step(159): len = 470463, overlap = 162.594 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000563391 +PHY-3002 : Step(160): len = 476929, overlap = 161.812 +PHY-3002 : Step(161): len = 484567, overlap = 151.156 +PHY-3002 : Step(162): len = 486813, overlap = 149.281 +PHY-3002 : Step(163): len = 488813, overlap = 149.875 +PHY-3002 : Step(164): len = 490570, overlap = 140.344 +PHY-3002 : Step(165): len = 491244, overlap = 141.281 +PHY-3002 : Step(166): len = 490396, overlap = 141.625 +PHY-3002 : Step(167): len = 490181, overlap = 141.156 +PHY-3002 : Step(168): len = 490945, overlap = 140.75 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0011016 +PHY-3002 : Step(169): len = 496449, overlap = 127.094 +PHY-3002 : Step(170): len = 504286, overlap = 130.031 +PHY-3002 : Step(171): len = 506351, overlap = 122.312 +PHY-3002 : Step(172): len = 507900, overlap = 123.844 +PHY-3002 : Step(173): len = 509788, overlap = 120.188 +PHY-3002 : Step(174): len = 511974, overlap = 114.219 +PHY-3002 : Step(175): len = 512667, overlap = 116.344 +PHY-3002 : Step(176): len = 513356, overlap = 115.906 +PHY-3002 : Step(177): len = 514345, overlap = 110.969 +PHY-3002 : Step(178): len = 514859, overlap = 111.062 +PHY-3002 : Step(179): len = 514889, overlap = 109.375 +PHY-3002 : Step(180): len = 514907, overlap = 107.562 +PHY-3002 : Step(181): len = 515226, overlap = 113.094 +PHY-3002 : Step(182): len = 515315, overlap = 115.344 +PHY-3002 : Step(183): len = 515218, overlap = 112.844 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0019155 +PHY-3002 : Step(184): len = 518415, overlap = 110.375 +PHY-3002 : Step(185): len = 524256, overlap = 105.188 +PHY-3002 : Step(186): len = 525904, overlap = 103.719 +PHY-3002 : Step(187): len = 527046, overlap = 101.125 +PHY-3002 : Step(188): len = 528391, overlap = 103.469 +PHY-3002 : Step(189): len = 529211, overlap = 107.188 +PHY-3002 : Step(190): len = 529278, overlap = 108.062 +PHY-3002 : Step(191): len = 529454, overlap = 108.406 +PHY-3002 : Step(192): len = 530029, overlap = 109.812 +PHY-3002 : Step(193): len = 530358, overlap = 111.219 +PHY-3002 : Step(194): len = 530896, overlap = 109.219 +PHY-3002 : Step(195): len = 531644, overlap = 108.031 +PHY-3002 : Step(196): len = 532126, overlap = 108.594 +PHY-3002 : Step(197): len = 532260, overlap = 108.688 +PHY-3002 : Step(198): len = 532185, overlap = 107.188 +PHY-3002 : Step(199): len = 532272, overlap = 106.312 +PHY-3002 : Step(200): len = 532808, overlap = 102.562 +PHY-3002 : Step(201): len = 533198, overlap = 103.875 +PHY-3002 : Step(202): len = 533068, overlap = 102.125 +PHY-3002 : Step(203): len = 533068, overlap = 102.125 +PHY-3002 : Step(204): len = 533123, overlap = 103.125 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.010443s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (149.6%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 714624, over cnt = 1568(4%), over = 7178, worst = 44 +PHY-1001 : End global iterations; 0.711692s wall, 0.843750s user + 0.125000s system = 0.968750s CPU (136.1%) + +PHY-1001 : Congestion index: top1 = 75.67, top5 = 59.90, top10 = 51.49, top15 = 46.05. +PHY-3001 : End congestion estimation; 0.943742s wall, 1.078125s user + 0.125000s system = 1.203125s CPU (127.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.882931s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.1%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126945 +PHY-3002 : Step(205): len = 651620, overlap = 56.3125 +PHY-3002 : Step(206): len = 653297, overlap = 65.5 +PHY-3002 : Step(207): len = 647753, overlap = 69.3438 +PHY-3002 : Step(208): len = 641445, overlap = 63.8438 +PHY-3002 : Step(209): len = 635799, overlap = 61.0312 +PHY-3002 : Step(210): len = 633738, overlap = 62.5938 +PHY-3002 : Step(211): len = 633098, overlap = 61.125 +PHY-3002 : Step(212): len = 632272, overlap = 56.75 +PHY-3002 : Step(213): len = 630468, overlap = 53.875 +PHY-3002 : Step(214): len = 627875, overlap = 48.125 +PHY-3002 : Step(215): len = 624830, overlap = 45.5312 +PHY-3002 : Step(216): len = 622143, overlap = 43.75 +PHY-3002 : Step(217): len = 620834, overlap = 37.25 +PHY-3002 : Step(218): len = 619641, overlap = 35.625 +PHY-3002 : Step(219): len = 618180, overlap = 34.1562 +PHY-3002 : Step(220): len = 618174, overlap = 37.2188 +PHY-3002 : Step(221): len = 617188, overlap = 36.9062 +PHY-3002 : Step(222): len = 615032, overlap = 38.0625 +PHY-3002 : Step(223): len = 612216, overlap = 38.9688 +PHY-3002 : Step(224): len = 610202, overlap = 35.9688 +PHY-3002 : Step(225): len = 608415, overlap = 36.0312 +PHY-3002 : Step(226): len = 606921, overlap = 38.9062 +PHY-3002 : Step(227): len = 605497, overlap = 37.1562 +PHY-3002 : Step(228): len = 603987, overlap = 36.625 +PHY-3002 : Step(229): len = 602886, overlap = 37.875 +PHY-3002 : Step(230): len = 601605, overlap = 36.7812 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025389 +PHY-3002 : Step(231): len = 605623, overlap = 35.1875 +PHY-3002 : Step(232): len = 608395, overlap = 33.9375 +PHY-3002 : Step(233): len = 609611, overlap = 32.0938 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000434206 +PHY-3002 : Step(234): len = 618373, overlap = 34.3438 +PHY-3002 : Step(235): len = 633524, overlap = 31.4062 +PHY-3002 : Step(236): len = 634716, overlap = 31.9062 +PHY-3002 : Step(237): len = 635266, overlap = 28.625 +PHY-3002 : Step(238): len = 635530, overlap = 26.0938 +PHY-3002 : Step(239): len = 634102, overlap = 28.7812 +PHY-3002 : Step(240): len = 634254, overlap = 30.9062 +PHY-3002 : Step(241): len = 634458, overlap = 33 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 48/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 719896, over cnt = 2733(7%), over = 11815, worst = 44 +PHY-1001 : End global iterations; 1.713662s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (128.6%) + +PHY-1001 : Congestion index: top1 = 83.60, top5 = 64.83, top10 = 56.55, top15 = 51.64. +PHY-3001 : End congestion estimation; 1.978116s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (124.8%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.079713s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000107045 +PHY-3002 : Step(242): len = 629397, overlap = 229.344 +PHY-3002 : Step(243): len = 630978, overlap = 186.312 +PHY-3002 : Step(244): len = 623229, overlap = 162.406 +PHY-3002 : Step(245): len = 618172, overlap = 145.188 +PHY-3002 : Step(246): len = 613147, overlap = 126.312 +PHY-3002 : Step(247): len = 610145, overlap = 125.594 +PHY-3002 : Step(248): len = 605265, overlap = 124.156 +PHY-3002 : Step(249): len = 603035, overlap = 127.125 +PHY-3002 : Step(250): len = 600841, overlap = 120.906 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000214089 +PHY-3002 : Step(251): len = 601155, overlap = 118.719 +PHY-3002 : Step(252): len = 603472, overlap = 114.906 +PHY-3002 : Step(253): len = 605803, overlap = 105.031 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000428178 +PHY-3002 : Step(254): len = 611464, overlap = 95.9688 +PHY-3002 : Step(255): len = 619589, overlap = 83.3125 +PHY-3002 : Step(256): len = 625102, overlap = 79.1562 +PHY-3002 : Step(257): len = 627521, overlap = 76.625 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.442597s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.6%) + +RUN-1004 : used memory is 583 MB, reserved memory is 564 MB, peak memory is 717 MB +OPT-1001 : Total overflow 384.84 peak overflow 3.47 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1093/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 724368, over cnt = 3038(8%), over = 10466, worst = 26 +PHY-1001 : End global iterations; 1.200636s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (153.6%) + +PHY-1001 : Congestion index: top1 = 70.22, top5 = 56.96, top10 = 50.61, top15 = 46.87. +PHY-1001 : End incremental global routing; 1.546313s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (141.5%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.920467s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.2%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17607 has valid locations, 349 needs to be replaced +PHY-3001 : design contains 18041 instances, 7532 luts, 9288 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6063 pins +PHY-3001 : Found 1231 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 650874 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16601/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738040, over cnt = 3068(8%), over = 10637, worst = 26 +PHY-1001 : End global iterations; 0.234864s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (119.8%) + +PHY-1001 : Congestion index: top1 = 69.94, top5 = 57.07, top10 = 50.94, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.486859s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (109.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86082, tnet num: 20443, tinst num: 18041, tnode num: 116915, tedge num: 138008. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.444983s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.6%) + +RUN-1004 : used memory is 626 MB, reserved memory is 620 MB, peak memory is 721 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.773068s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (100.3%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(258): len = 650035, overlap = 0.125 +PHY-3002 : Step(259): len = 649700, overlap = 0.125 +PHY-3002 : Step(260): len = 649450, overlap = 0.125 +PHY-3002 : Step(261): len = 649177, overlap = 0.125 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16724/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 735584, over cnt = 3070(8%), over = 10643, worst = 26 +PHY-1001 : End global iterations; 0.188028s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (108.0%) + +PHY-1001 : Congestion index: top1 = 70.19, top5 = 57.15, top10 = 50.97, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.441468s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.6%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.008985s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (100.7%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000334276 +PHY-3002 : Step(262): len = 649093, overlap = 79.4375 +PHY-3002 : Step(263): len = 649168, overlap = 78.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000668551 +PHY-3002 : Step(264): len = 649153, overlap = 79.0312 +PHY-3002 : Step(265): len = 649644, overlap = 78.625 +PHY-3001 : Final: Len = 649644, Over = 78.625 +PHY-3001 : End incremental placement; 5.379632s wall, 5.375000s user + 0.218750s system = 5.593750s CPU (104.0%) + +OPT-1001 : Total overflow 390.09 peak overflow 3.47 +OPT-1001 : End high-fanout net optimization; 8.390413s wall, 9.062500s user + 0.281250s system = 9.343750s CPU (111.4%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 739. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16679/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738800, over cnt = 3016(8%), over = 9702, worst = 26 +PHY-1002 : len = 785712, over cnt = 1985(5%), over = 4886, worst = 21 +PHY-1002 : len = 825896, over cnt = 801(2%), over = 1646, worst = 16 +PHY-1002 : len = 844056, over cnt = 213(0%), over = 333, worst = 11 +PHY-1002 : len = 848840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.658320s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (144.2%) + +PHY-1001 : Congestion index: top1 = 57.22, top5 = 49.72, top10 = 45.96, top15 = 43.61. +OPT-1001 : End congestion update; 1.930110s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (138.4%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.847597s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.5%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 115 cells processed and 15100 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 1084 slack improved +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved +OPT-1001 : End bottleneck based optimization; 3.093037s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (123.8%) + +OPT-1001 : Current memory(MB): used = 702, reserve = 691, peak = 739. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16775/20623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849680, over cnt = 74(0%), over = 94, worst = 4 +PHY-1002 : len = 849528, over cnt = 33(0%), over = 36, worst = 3 +PHY-1002 : len = 849784, over cnt = 8(0%), over = 8, worst = 1 +PHY-1002 : len = 849832, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 849848, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.719827s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (102.0%) + +PHY-1001 : Congestion index: top1 = 56.90, top5 = 49.64, top10 = 45.91, top15 = 43.56. +OPT-1001 : End congestion update; 0.988641s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (101.1%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 1.120832s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (72.5%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 4450 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.226938s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (87.0%) + +OPT-1001 : Current memory(MB): used = 713, reserve = 700, peak = 739. +OPT-1001 : End physical optimization; 15.466138s wall, 16.578125s user + 0.359375s system = 16.937500s CPU (109.5%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7532 LUT to BLE ... +SYN-4008 : Packed 7532 LUT and 3133 SEQ to BLE. +SYN-4003 : Packing 6157 remaining SEQ's ... +SYN-4005 : Packed 3725 SEQ with LUT/SLICE +SYN-4006 : 977 single LUT's are left +SYN-4006 : 2432 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9964/13787 primitive instances ... +PHY-3001 : End packing; 1.628531s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.7%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6874 instances +RUN-1001 : 3363 mslices, 3363 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17618 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10005 nets have 2 pins +RUN-1001 : 5769 nets have [3 - 5] pins +RUN-1001 : 1139 nets have [6 - 10] pins +RUN-1001 : 345 nets have [11 - 20] pins +RUN-1001 : 327 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6872 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3573 pins +PHY-3001 : Found 490 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 662223, Over = 253.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 7617/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 811720, over cnt = 1957(5%), over = 3182, worst = 8 +PHY-1002 : len = 819944, over cnt = 1208(3%), over = 1726, worst = 6 +PHY-1002 : len = 834160, over cnt = 468(1%), over = 625, worst = 5 +PHY-1002 : len = 841744, over cnt = 134(0%), over = 157, worst = 4 +PHY-1002 : len = 844704, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.608274s wall, 2.171875s user + 0.031250s system = 2.203125s CPU (137.0%) + +PHY-1001 : Congestion index: top1 = 58.53, top5 = 50.73, top10 = 46.56, top15 = 43.91. +PHY-3001 : End congestion estimation; 2.009608s wall, 2.578125s user + 0.031250s system = 2.609375s CPU (129.8%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6872, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.616340s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.6%) + +RUN-1004 : used memory is 625 MB, reserved memory is 616 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.501083s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.65564e-05 +PHY-3002 : Step(266): len = 649520, overlap = 250 +PHY-3002 : Step(267): len = 642403, overlap = 253.75 +PHY-3002 : Step(268): len = 637448, overlap = 255 +PHY-3002 : Step(269): len = 634168, overlap = 254 +PHY-3002 : Step(270): len = 632517, overlap = 259.25 +PHY-3002 : Step(271): len = 631073, overlap = 264.75 +PHY-3002 : Step(272): len = 627992, overlap = 264.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.31129e-05 +PHY-3002 : Step(273): len = 630887, overlap = 259.75 +PHY-3002 : Step(274): len = 634775, overlap = 254 +PHY-3002 : Step(275): len = 634921, overlap = 251.25 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000186226 +PHY-3002 : Step(276): len = 644232, overlap = 241.25 +PHY-3002 : Step(277): len = 652624, overlap = 229.25 +PHY-3002 : Step(278): len = 652092, overlap = 229.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.368044s wall, 0.390625s user + 0.484375s system = 0.875000s CPU (237.7%) + +PHY-3001 : Trial Legalized: Len = 732801 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 884/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849856, over cnt = 2629(7%), over = 4435, worst = 8 +PHY-1002 : len = 866496, over cnt = 1574(4%), over = 2279, worst = 6 +PHY-1002 : len = 885736, over cnt = 545(1%), over = 755, worst = 6 +PHY-1002 : len = 895568, over cnt = 99(0%), over = 127, worst = 5 +PHY-1002 : len = 897712, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.340125s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (151.6%) + +PHY-1001 : Congestion index: top1 = 56.34, top5 = 49.93, top10 = 46.51, top15 = 44.33. +PHY-3001 : End congestion estimation; 2.803466s wall, 4.015625s user + 0.000000s system = 4.015625s CPU (143.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.871122s wall, 0.828125s user + 0.046875s system = 0.875000s CPU (100.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165 +PHY-3002 : Step(279): len = 706565, overlap = 45.75 +PHY-3002 : Step(280): len = 692044, overlap = 70.5 +PHY-3002 : Step(281): len = 678987, overlap = 101.75 +PHY-3002 : Step(282): len = 671353, overlap = 129 +PHY-3002 : Step(283): len = 666387, overlap = 147 +PHY-3002 : Step(284): len = 664006, overlap = 154.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033 +PHY-3002 : Step(285): len = 669536, overlap = 153.25 +PHY-3002 : Step(286): len = 675137, overlap = 150.25 +PHY-3002 : Step(287): len = 677080, overlap = 152.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00064827 +PHY-3002 : Step(288): len = 680934, overlap = 147.75 +PHY-3002 : Step(289): len = 688915, overlap = 146.25 +PHY-3002 : Step(290): len = 698496, overlap = 140.25 +PHY-3002 : Step(291): len = 700456, overlap = 140.75 +PHY-3002 : Step(292): len = 701680, overlap = 142.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.032862s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (95.1%) + +PHY-3001 : Legalized: Len = 728102, Over = 0 +PHY-3001 : Spreading special nets. 443 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.103064s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (91.0%) + +PHY-3001 : 628 instances has been re-located, deltaX = 184, deltaY = 381, maxDist = 2. +PHY-3001 : Final: Len = 737976, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6875, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.894255s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (100.6%) + +RUN-1004 : used memory is 619 MB, reserved memory is 606 MB, peak memory is 739 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 3082/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 863136, over cnt = 2610(7%), over = 4296, worst = 6 +PHY-1002 : len = 879048, over cnt = 1415(4%), over = 2042, worst = 6 +PHY-1002 : len = 895448, over cnt = 542(1%), over = 771, worst = 5 +PHY-1002 : len = 904664, over cnt = 130(0%), over = 187, worst = 5 +PHY-1002 : len = 907272, over cnt = 11(0%), over = 19, worst = 5 +PHY-1001 : End global iterations; 2.095176s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (149.2%) + +PHY-1001 : Congestion index: top1 = 56.10, top5 = 49.56, top10 = 46.28, top15 = 44.25. +PHY-1001 : End incremental global routing; 2.506964s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (141.5%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.957830s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.5%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6782 has valid locations, 30 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 741838 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16076/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 911648, over cnt = 110(0%), over = 130, worst = 5 +PHY-1002 : len = 911776, over cnt = 60(0%), over = 65, worst = 3 +PHY-1002 : len = 912328, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 912392, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 912456, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.864020s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (106.7%) + +PHY-1001 : Congestion index: top1 = 56.19, top5 = 49.69, top10 = 46.41, top15 = 44.36. +PHY-3001 : End congestion estimation; 1.179332s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (104.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74012, tnet num: 17472, tinst num: 6900, tnode num: 96587, tedge num: 124127. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.871816s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.2%) + +RUN-1004 : used memory is 671 MB, reserved memory is 671 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.762444s wall, 2.734375s user + 0.031250s system = 2.765625s CPU (100.1%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(293): len = 740891, overlap = 0.5 +PHY-3002 : Step(294): len = 740538, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16066/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910472, over cnt = 75(0%), over = 95, worst = 6 +PHY-1002 : len = 910680, over cnt = 32(0%), over = 34, worst = 2 +PHY-1002 : len = 911064, over cnt = 9(0%), over = 9, worst = 1 +PHY-1002 : len = 911200, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 911216, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.752400s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (103.8%) + +PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.69, top10 = 46.41, top15 = 44.34. +PHY-3001 : End congestion estimation; 1.059521s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (103.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.878441s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160642 +PHY-3002 : Step(295): len = 740237, overlap = 1.75 +PHY-3002 : Step(296): len = 740365, overlap = 2 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005665s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 740500, Over = 0 +PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061754s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%) + +PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 2. +PHY-3001 : Final: Len = 740436, Over = 0 +PHY-3001 : End incremental placement; 6.372828s wall, 6.515625s user + 0.125000s system = 6.640625s CPU (104.2%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 10.356587s wall, 11.531250s user + 0.171875s system = 11.703125s CPU (113.0%) + +OPT-1001 : Current memory(MB): used = 736, reserve = 726, peak = 752. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16051/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910608, over cnt = 64(0%), over = 75, worst = 3 +PHY-1002 : len = 910552, over cnt = 29(0%), over = 30, worst = 2 +PHY-1002 : len = 910712, over cnt = 5(0%), over = 5, worst = 1 +PHY-1002 : len = 910776, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 910792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.764570s wall, 0.781250s user + 0.031250s system = 0.812500s CPU (106.3%) + +PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.74, top10 = 46.39, top15 = 44.32. +OPT-1001 : End congestion update; 1.071760s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (103.5%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.733561s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%) + +OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 743728, Over = 0 +PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.067417s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.7%) + +PHY-3001 : 20 instances has been re-located, deltaX = 9, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 744032, Over = 0 +PHY-3001 : End incremental legalization; 0.457865s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (119.4%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 10363 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748708, Over = 0 +PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061525s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.6%) + +PHY-3001 : 18 instances has been re-located, deltaX = 7, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 749102, Over = 0 +PHY-3001 : End incremental legalization; 0.443253s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (116.3%) + +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 30 cells processed and 9680 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748964, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.066486s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.0%) + +PHY-3001 : 6 instances has been re-located, deltaX = 5, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 749362, Over = 0 +PHY-3001 : End incremental legalization; 0.442376s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.9%) + +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 649 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750417, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059873s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%) + +PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 750441, Over = 0 +PHY-3001 : End incremental legalization; 0.383152s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.9%) + +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 1081 slack improved +OPT-1001 : End bottleneck based optimization; 4.195074s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (107.3%) + +OPT-1001 : Current memory(MB): used = 739, reserve = 728, peak = 752. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15658/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 921656, over cnt = 225(0%), over = 304, worst = 9 +PHY-1002 : len = 921944, over cnt = 124(0%), over = 136, worst = 4 +PHY-1002 : len = 922344, over cnt = 84(0%), over = 89, worst = 2 +PHY-1002 : len = 923408, over cnt = 19(0%), over = 19, worst = 1 +PHY-1002 : len = 923864, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.860666s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (108.9%) + +PHY-1001 : Congestion index: top1 = 56.08, top5 = 49.86, top10 = 46.58, top15 = 44.47. +OPT-1001 : End congestion update; 1.172607s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (106.6%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.725378s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.2%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750211, Over = 0 +PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060045s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%) + +PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 9, maxDist = 2. +PHY-3001 : Final: Len = 750501, Over = 0 +PHY-3001 : End incremental legalization; 0.384991s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.4%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.413211s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (104.2%) + +OPT-1001 : Current memory(MB): used = 739, reserve = 728, peak = 752. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.722059s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16067/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 923880, over cnt = 30(0%), over = 31, worst = 2 +PHY-1002 : len = 923824, over cnt = 13(0%), over = 13, worst = 1 +PHY-1002 : len = 923856, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 923856, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 923904, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.736472s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (97.6%) + +PHY-1001 : Congestion index: top1 = 56.12, top5 = 49.87, top10 = 46.62, top15 = 44.51. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.726015s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.620690 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 221ps with logic level 1 +OPT-1001 : End physical optimization; 21.607192s wall, 23.125000s user + 0.218750s system = 23.343750s CPU (108.0%) + +RUN-1003 : finish command "place" in 66.632899s wall, 93.171875s user + 5.703125s system = 98.875000s CPU (148.4%) + +RUN-1004 : used memory is 645 MB, reserved memory is 647 MB, peak memory is 752 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.692280s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (175.4%) + +RUN-1004 : used memory is 646 MB, reserved memory is 648 MB, peak memory is 752 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6908 instances +RUN-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17653 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10002 nets have 2 pins +RUN-1001 : 5782 nets have [3 - 5] pins +RUN-1001 : 1143 nets have [6 - 10] pins +RUN-1001 : 352 nets have [11 - 20] pins +RUN-1001 : 345 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.622371s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.2%) + +RUN-1004 : used memory is 631 MB, reserved memory is 619 MB, peak memory is 752 MB +PHY-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 858424, over cnt = 2701(7%), over = 4497, worst = 8 +PHY-1002 : len = 877136, over cnt = 1568(4%), over = 2249, worst = 6 +PHY-1002 : len = 892488, over cnt = 746(2%), over = 1063, worst = 6 +PHY-1002 : len = 907912, over cnt = 24(0%), over = 37, worst = 6 +PHY-1002 : len = 908592, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.056530s wall, 4.078125s user + 0.093750s system = 4.171875s CPU (136.5%) + +PHY-1001 : Congestion index: top1 = 55.41, top5 = 49.60, top10 = 46.25, top15 = 44.10. +PHY-1001 : End global routing; 3.389888s wall, 4.406250s user + 0.093750s system = 4.500000s CPU (132.7%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 719, reserve = 718, peak = 752. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 996, reserve = 993, peak = 996. +PHY-1001 : End build detailed router design. 3.969810s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (100.0%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 265920, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 5.170731s wall, 5.156250s user + 0.015625s system = 5.171875s CPU (100.0%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 265976, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.424594s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%) + +PHY-1001 : Current memory(MB): used = 1032, reserve = 1030, peak = 1032. +PHY-1001 : End phase 1; 5.607928s wall, 5.593750s user + 0.015625s system = 5.609375s CPU (100.0%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 43% nets. +PHY-1001 : Routed 51% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.34276e+06, over cnt = 1866(0%), over = 1879, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1050, reserve = 1046, peak = 1050. +PHY-1001 : End initial routed; 28.452709s wall, 60.765625s user + 0.250000s system = 61.015625s CPU (214.4%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.288945s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.2%) + +PHY-1001 : Current memory(MB): used = 1061, reserve = 1057, peak = 1061. +PHY-1001 : End phase 2; 31.741720s wall, 64.062500s user + 0.250000s system = 64.312500s CPU (202.6%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.142207s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.9%) + +PHY-1022 : len = 2.34276e+06, over cnt = 1867(0%), over = 1880, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.516182s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (99.9%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.31113e+06, over cnt = 653(0%), over = 655, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.358844s wall, 2.953125s user + 0.031250s system = 2.984375s CPU (219.6%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.31112e+06, over cnt = 129(0%), over = 129, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.787708s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (138.9%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.31181e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.545690s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (111.7%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.3119e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.301372s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (108.9%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 5; 0.266467s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (82.1%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.333170s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.3%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 2.283072s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (99.2%) + +PHY-1001 : Current memory(MB): used = 1163, reserve = 1163, peak = 1163. +PHY-1001 : End phase 3; 9.914007s wall, 11.843750s user + 0.046875s system = 11.890625s CPU (119.9%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.135428s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.8%) + +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.379882s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.7%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.304395s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 2.376257s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (99.9%) + +PHY-1001 : Current memory(MB): used = 1172, reserve = 1172, peak = 1172. +PHY-1001 : End phase 4; 6.087016s wall, 6.078125s user + 0.000000s system = 6.078125s CPU (99.9%) + +PHY-1003 : Routed, final wirelength = 2.31198e+06 +PHY-1001 : Current memory(MB): used = 1174, reserve = 1174, peak = 1174. +PHY-1001 : End export database. 0.059678s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%) + +PHY-1001 : End detail routing; 57.770858s wall, 91.937500s user + 0.359375s system = 92.296875s CPU (159.8%) + +RUN-1003 : finish command "route" in 63.868775s wall, 99.000000s user + 0.500000s system = 99.500000s CPU (155.8%) + +RUN-1004 : used memory is 1100 MB, reserved memory is 1098 MB, peak memory is 1174 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10272 out of 19600 52.41% +#reg 9440 out of 19600 48.16% +#le 12642 + #lut only 3202 out of 12642 25.33% + #reg only 2370 out of 12642 18.75% + #lut® 7070 out of 12642 55.92% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1411 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 67 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_275.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_295.f0 3 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P16 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE + debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P110 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12642 |9245 |1027 |9472 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |534 |414 |23 |439 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |105 |89 |4 |93 |4 |0 | +| U_crc16_24b |crc16_24b |35 |35 |0 |21 |0 |0 | +| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 | +| exdev_ctl_a |exdev_ctl |783 |363 |96 |589 |0 |0 | +| u_ADconfig |AD_config |196 |132 |25 |142 |0 |0 | +| u_gen_sp |gen_sp |263 |146 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |755 |389 |96 |568 |0 |0 | +| u_ADconfig |AD_config |179 |143 |25 |128 |0 |0 | +| u_gen_sp |gen_sp |258 |158 |71 |122 |0 |0 | +| sampling_fe_a |sampling_fe |3082 |2473 |306 |2092 |25 |0 | +| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 | +| u_ad_sampling |ad_sampling |178 |118 |17 |140 |0 |0 | +| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_sort |sort |2866 |2347 |289 |1914 |25 |0 | +| rddpram_ctl |rddpram_ctl |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer |data_prebuffer |2426 |2024 |253 |1569 |22 |0 | +| channelPart |channel_part_8478 |130 |125 |3 |122 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |0 | +| ram_switch |ram_switch |1920 |1590 |197 |1175 |0 |0 | +| adc_addr_gen |adc_addr_gen |231 |204 |27 |126 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 | +| insert |insert |949 |648 |170 |655 |0 |0 | +| ram_switch_state |ram_switch_state |740 |738 |0 |394 |0 |0 | +| read_ram_i |read_ram |283 |235 |44 |196 |0 |0 | +| read_ram_addr |read_ram_addr |227 |187 |40 |156 |0 |0 | +| read_ram_data |read_ram_data |53 |46 |4 |37 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |334 |244 |36 |271 |3 |0 | +| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3369 |2673 |349 |2099 |25 |1 | +| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |182 |111 |17 |148 |0 |0 | +| u_sort |sort_rev |3150 |2545 |332 |1916 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2693 |2207 |290 |1564 |22 |1 | +| channelPart |channel_part_8478 |233 |230 |3 |142 |0 |0 | +| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 | +| ram_switch |ram_switch |1998 |1643 |197 |1130 |0 |0 | +| adc_addr_gen |adc_addr_gen |213 |186 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |4 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |4 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 | +| insert |insert |974 |648 |170 |672 |0 |0 | +| ram_switch_state |ram_switch_state |811 |809 |0 |352 |0 |0 | +| read_ram_i |read_ram_rev |364 |251 |81 |211 |0 |0 | +| read_ram_addr |read_ram_addr_rev |297 |212 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |67 |39 |8 |49 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9940 + #2 2 3914 + #3 3 1327 + #4 4 538 + #5 5-10 1208 + #6 11-50 607 + #7 51-100 22 + #8 >500 1 + Average 2.90 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.076257s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (172.3%) + +RUN-1004 : used memory is 1101 MB, reserved memory is 1100 MB, peak memory is 1174 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.612284s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.8%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1104 MB, peak memory is 1174 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.511173s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.3%) + +RUN-1004 : used memory is 1109 MB, reserved memory is 1107 MB, peak memory is 1174 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6906 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17653, pip num: 172714 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 565 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 480236 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.208741s wall, 64.453125s user + 0.156250s system = 64.609375s CPU (632.9%) + +RUN-1004 : used memory is 1272 MB, reserved memory is 1268 MB, peak memory is 1387 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_153553.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_154441.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_154441.log new file mode 100644 index 0000000..c8bd557 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_154441.log @@ -0,0 +1,2003 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:44:41 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.455455s wall, 2.343750s user + 0.109375s system = 2.453125s CPU (99.9%) + +RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u1_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u1_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17764 instances +RUN-0007 : 7439 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20342 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13379 nets have 2 pins +RUN-1001 : 5518 nets have [3 - 5] pins +RUN-1001 : 1034 nets have [6 - 10] pins +RUN-1001 : 159 nets have [11 - 20] pins +RUN-1001 : 178 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2027 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17762 instances, 7439 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5956 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84908, tnet num: 20164, tinst num: 17762, tnode num: 115169, tedge num: 136218. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.191418s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (101.0%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20164 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.004715s wall, 1.937500s user + 0.078125s system = 2.015625s CPU (100.5%) + +PHY-3001 : Found 1227 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.12783e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17762. +PHY-3001 : Level 1 #clusters 1995. +PHY-3001 : End clustering; 0.151079s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (113.8%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.31589e+06, overlap = 459.094 +PHY-3002 : Step(2): len = 1.20858e+06, overlap = 518.844 +PHY-3002 : Step(3): len = 867234, overlap = 566.281 +PHY-3002 : Step(4): len = 794229, overlap = 618.188 +PHY-3002 : Step(5): len = 619939, overlap = 739.938 +PHY-3002 : Step(6): len = 537109, overlap = 830.969 +PHY-3002 : Step(7): len = 451424, overlap = 905.625 +PHY-3002 : Step(8): len = 409772, overlap = 931.719 +PHY-3002 : Step(9): len = 371626, overlap = 981.469 +PHY-3002 : Step(10): len = 334392, overlap = 1023.53 +PHY-3002 : Step(11): len = 301787, overlap = 1111.62 +PHY-3002 : Step(12): len = 276664, overlap = 1148.38 +PHY-3002 : Step(13): len = 252486, overlap = 1189.31 +PHY-3002 : Step(14): len = 227185, overlap = 1276.19 +PHY-3002 : Step(15): len = 211244, overlap = 1285.59 +PHY-3002 : Step(16): len = 191451, overlap = 1368.19 +PHY-3002 : Step(17): len = 182692, overlap = 1415.09 +PHY-3002 : Step(18): len = 163551, overlap = 1437.59 +PHY-3002 : Step(19): len = 153624, overlap = 1455.44 +PHY-3002 : Step(20): len = 141718, overlap = 1460.72 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.13995e-06 +PHY-3002 : Step(21): len = 141999, overlap = 1425.5 +PHY-3002 : Step(22): len = 171332, overlap = 1371.41 +PHY-3002 : Step(23): len = 177952, overlap = 1305.09 +PHY-3002 : Step(24): len = 183356, overlap = 1220.97 +PHY-3002 : Step(25): len = 183152, overlap = 1195.53 +PHY-3002 : Step(26): len = 185619, overlap = 1150.94 +PHY-3002 : Step(27): len = 186522, overlap = 1133.44 +PHY-3002 : Step(28): len = 187463, overlap = 1113.41 +PHY-3002 : Step(29): len = 187024, overlap = 1094.38 +PHY-3002 : Step(30): len = 184992, overlap = 1084.12 +PHY-3002 : Step(31): len = 183477, overlap = 1093.12 +PHY-3002 : Step(32): len = 181953, overlap = 1101.44 +PHY-3002 : Step(33): len = 180006, overlap = 1093.69 +PHY-3002 : Step(34): len = 178314, overlap = 1095.88 +PHY-3002 : Step(35): len = 176130, overlap = 1107.47 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.2799e-06 +PHY-3002 : Step(36): len = 180517, overlap = 1105.25 +PHY-3002 : Step(37): len = 192333, overlap = 1093.56 +PHY-3002 : Step(38): len = 194731, overlap = 1069.5 +PHY-3002 : Step(39): len = 198959, overlap = 1049.88 +PHY-3002 : Step(40): len = 200392, overlap = 1044.34 +PHY-3002 : Step(41): len = 202034, overlap = 1045 +PHY-3002 : Step(42): len = 202122, overlap = 1024.72 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.5598e-06 +PHY-3002 : Step(43): len = 208773, overlap = 990.25 +PHY-3002 : Step(44): len = 223740, overlap = 921 +PHY-3002 : Step(45): len = 232518, overlap = 856.344 +PHY-3002 : Step(46): len = 241579, overlap = 794.188 +PHY-3002 : Step(47): len = 245534, overlap = 754.562 +PHY-3002 : Step(48): len = 247096, overlap = 720.531 +PHY-3002 : Step(49): len = 247193, overlap = 691.469 +PHY-3002 : Step(50): len = 247789, overlap = 681.75 +PHY-3002 : Step(51): len = 247877, overlap = 672.75 +PHY-3002 : Step(52): len = 247686, overlap = 641.562 +PHY-3002 : Step(53): len = 247323, overlap = 641.625 +PHY-3002 : Step(54): len = 246482, overlap = 652.938 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.1196e-06 +PHY-3002 : Step(55): len = 260381, overlap = 619.094 +PHY-3002 : Step(56): len = 280900, overlap = 560.812 +PHY-3002 : Step(57): len = 289618, overlap = 516.281 +PHY-3002 : Step(58): len = 295394, overlap = 527 +PHY-3002 : Step(59): len = 293881, overlap = 521.688 +PHY-3002 : Step(60): len = 292463, overlap = 531.281 +PHY-3002 : Step(61): len = 289976, overlap = 525.656 +PHY-3002 : Step(62): len = 289017, overlap = 519.625 +PHY-3002 : Step(63): len = 290094, overlap = 503.156 +PHY-3002 : Step(64): len = 288402, overlap = 502.094 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.82392e-05 +PHY-3002 : Step(65): len = 310012, overlap = 494.5 +PHY-3002 : Step(66): len = 326591, overlap = 426.562 +PHY-3002 : Step(67): len = 332081, overlap = 407.531 +PHY-3002 : Step(68): len = 333352, overlap = 390.781 +PHY-3002 : Step(69): len = 333072, overlap = 369.656 +PHY-3002 : Step(70): len = 333678, overlap = 346.094 +PHY-3002 : Step(71): len = 333527, overlap = 332.781 +PHY-3002 : Step(72): len = 334972, overlap = 332.875 +PHY-3002 : Step(73): len = 333105, overlap = 332.781 +PHY-3002 : Step(74): len = 333410, overlap = 343.438 +PHY-3002 : Step(75): len = 334122, overlap = 354.625 +PHY-3002 : Step(76): len = 334697, overlap = 354.562 +PHY-3002 : Step(77): len = 334102, overlap = 362.188 +PHY-3002 : Step(78): len = 334457, overlap = 354.844 +PHY-3002 : Step(79): len = 334735, overlap = 362.812 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.64784e-05 +PHY-3002 : Step(80): len = 355209, overlap = 334.406 +PHY-3002 : Step(81): len = 364794, overlap = 324.406 +PHY-3002 : Step(82): len = 363238, overlap = 321.938 +PHY-3002 : Step(83): len = 365881, overlap = 315.438 +PHY-3002 : Step(84): len = 368738, overlap = 309.688 +PHY-3002 : Step(85): len = 372010, overlap = 299.406 +PHY-3002 : Step(86): len = 370207, overlap = 290.125 +PHY-3002 : Step(87): len = 371965, overlap = 285.812 +PHY-3002 : Step(88): len = 374438, overlap = 278.656 +PHY-3002 : Step(89): len = 376242, overlap = 284.531 +PHY-3002 : Step(90): len = 373689, overlap = 280.469 +PHY-3002 : Step(91): len = 373990, overlap = 275.094 +PHY-3002 : Step(92): len = 373883, overlap = 270 +PHY-3002 : Step(93): len = 374198, overlap = 276.344 +PHY-3002 : Step(94): len = 371262, overlap = 285.344 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.29568e-05 +PHY-3002 : Step(95): len = 388848, overlap = 263.75 +PHY-3002 : Step(96): len = 398904, overlap = 245.75 +PHY-3002 : Step(97): len = 398114, overlap = 247.031 +PHY-3002 : Step(98): len = 400034, overlap = 241.906 +PHY-3002 : Step(99): len = 402857, overlap = 237.906 +PHY-3002 : Step(100): len = 405410, overlap = 247.688 +PHY-3002 : Step(101): len = 403224, overlap = 244.938 +PHY-3002 : Step(102): len = 404045, overlap = 235.188 +PHY-3002 : Step(103): len = 406403, overlap = 238.531 +PHY-3002 : Step(104): len = 408720, overlap = 236.75 +PHY-3002 : Step(105): len = 406294, overlap = 237.688 +PHY-3002 : Step(106): len = 405977, overlap = 230.969 +PHY-3002 : Step(107): len = 407748, overlap = 233.75 +PHY-3002 : Step(108): len = 409398, overlap = 224.938 +PHY-3002 : Step(109): len = 408863, overlap = 217.562 +PHY-3002 : Step(110): len = 409556, overlap = 209.719 +PHY-3002 : Step(111): len = 410167, overlap = 211.562 +PHY-3002 : Step(112): len = 410520, overlap = 217.125 +PHY-3002 : Step(113): len = 408402, overlap = 227.344 +PHY-3002 : Step(114): len = 408882, overlap = 226.781 +PHY-3002 : Step(115): len = 409626, overlap = 222.75 +PHY-3002 : Step(116): len = 410449, overlap = 221.469 +PHY-3002 : Step(117): len = 409083, overlap = 226.594 +PHY-3002 : Step(118): len = 409942, overlap = 225.188 +PHY-3002 : Step(119): len = 410884, overlap = 228.5 +PHY-3002 : Step(120): len = 411894, overlap = 229.562 +PHY-3002 : Step(121): len = 409140, overlap = 224.656 +PHY-3002 : Step(122): len = 409126, overlap = 230.656 +PHY-3002 : Step(123): len = 411004, overlap = 210.5 +PHY-3002 : Step(124): len = 412123, overlap = 199.031 +PHY-3002 : Step(125): len = 409337, overlap = 204.312 +PHY-3002 : Step(126): len = 409236, overlap = 207.281 +PHY-3002 : Step(127): len = 409659, overlap = 218.469 +PHY-3002 : Step(128): len = 409828, overlap = 226.25 +PHY-3002 : Step(129): len = 408357, overlap = 221.156 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000145914 +PHY-3002 : Step(130): len = 423073, overlap = 196.094 +PHY-3002 : Step(131): len = 431674, overlap = 186.719 +PHY-3002 : Step(132): len = 429925, overlap = 188.906 +PHY-3002 : Step(133): len = 430692, overlap = 188.312 +PHY-3002 : Step(134): len = 435018, overlap = 180.625 +PHY-3002 : Step(135): len = 438120, overlap = 176.969 +PHY-3002 : Step(136): len = 436528, overlap = 182.125 +PHY-3002 : Step(137): len = 437215, overlap = 187.719 +PHY-3002 : Step(138): len = 438886, overlap = 185.938 +PHY-3002 : Step(139): len = 440263, overlap = 176.406 +PHY-3002 : Step(140): len = 438532, overlap = 183.594 +PHY-3002 : Step(141): len = 438130, overlap = 181.031 +PHY-3002 : Step(142): len = 439164, overlap = 169.188 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000290706 +PHY-3002 : Step(143): len = 451171, overlap = 172.125 +PHY-3002 : Step(144): len = 460037, overlap = 166.906 +PHY-3002 : Step(145): len = 460493, overlap = 160.156 +PHY-3002 : Step(146): len = 461208, overlap = 153.5 +PHY-3002 : Step(147): len = 463582, overlap = 151.906 +PHY-3002 : Step(148): len = 466320, overlap = 150.844 +PHY-3002 : Step(149): len = 466953, overlap = 142.812 +PHY-3002 : Step(150): len = 468090, overlap = 144.875 +PHY-3002 : Step(151): len = 470032, overlap = 144.562 +PHY-3002 : Step(152): len = 471568, overlap = 143.938 +PHY-3002 : Step(153): len = 469907, overlap = 147.031 +PHY-3002 : Step(154): len = 470338, overlap = 147.25 +PHY-3002 : Step(155): len = 471740, overlap = 149.219 +PHY-3002 : Step(156): len = 472633, overlap = 147.938 +PHY-3002 : Step(157): len = 471361, overlap = 149.438 +PHY-3002 : Step(158): len = 471627, overlap = 151.594 +PHY-3002 : Step(159): len = 472822, overlap = 151 +PHY-3002 : Step(160): len = 472993, overlap = 151.375 +PHY-3002 : Step(161): len = 471656, overlap = 155.406 +PHY-3002 : Step(162): len = 471313, overlap = 154.156 +PHY-3002 : Step(163): len = 472445, overlap = 156.094 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000577676 +PHY-3002 : Step(164): len = 479290, overlap = 148.438 +PHY-3002 : Step(165): len = 487269, overlap = 136.031 +PHY-3002 : Step(166): len = 489406, overlap = 142.75 +PHY-3002 : Step(167): len = 490613, overlap = 141.469 +PHY-3002 : Step(168): len = 491798, overlap = 128.969 +PHY-3002 : Step(169): len = 493078, overlap = 123.281 +PHY-3002 : Step(170): len = 493340, overlap = 130.844 +PHY-3002 : Step(171): len = 494077, overlap = 132.25 +PHY-3002 : Step(172): len = 495373, overlap = 129.406 +PHY-3002 : Step(173): len = 497086, overlap = 122.094 +PHY-3002 : Step(174): len = 498143, overlap = 124.719 +PHY-3002 : Step(175): len = 499075, overlap = 121.781 +PHY-3002 : Step(176): len = 499055, overlap = 116.812 +PHY-3002 : Step(177): len = 499272, overlap = 114.281 +PHY-3002 : Step(178): len = 499434, overlap = 115.781 +PHY-3002 : Step(179): len = 499677, overlap = 115.781 +PHY-3002 : Step(180): len = 499896, overlap = 113.531 +PHY-3002 : Step(181): len = 500406, overlap = 111.812 +PHY-3002 : Step(182): len = 500619, overlap = 113.719 +PHY-3002 : Step(183): len = 500843, overlap = 117.719 +PHY-3002 : Step(184): len = 501079, overlap = 115.594 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106889 +PHY-3002 : Step(185): len = 505470, overlap = 112.812 +PHY-3002 : Step(186): len = 511619, overlap = 108.562 +PHY-3002 : Step(187): len = 512559, overlap = 101.344 +PHY-3002 : Step(188): len = 513053, overlap = 101.156 +PHY-3002 : Step(189): len = 513872, overlap = 102.781 +PHY-3002 : Step(190): len = 514178, overlap = 102.406 +PHY-3002 : Step(191): len = 514309, overlap = 101.031 +PHY-3002 : Step(192): len = 514764, overlap = 100.281 +PHY-3002 : Step(193): len = 515339, overlap = 101.156 +PHY-3002 : Step(194): len = 515339, overlap = 101.156 +PHY-3002 : Step(195): len = 515402, overlap = 101.156 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00184799 +PHY-3002 : Step(196): len = 518773, overlap = 100.969 +PHY-3002 : Step(197): len = 524374, overlap = 102.75 +PHY-3002 : Step(198): len = 526575, overlap = 93.9062 +PHY-3002 : Step(199): len = 528626, overlap = 90.7812 +PHY-3002 : Step(200): len = 530487, overlap = 89.1562 +PHY-3002 : Step(201): len = 531646, overlap = 89.6562 +PHY-3002 : Step(202): len = 531364, overlap = 89.7812 +PHY-3002 : Step(203): len = 531261, overlap = 89.8438 +PHY-3002 : Step(204): len = 532005, overlap = 93.0625 +PHY-3002 : Step(205): len = 532394, overlap = 93 +PHY-3002 : Step(206): len = 532098, overlap = 93.375 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00299006 +PHY-3002 : Step(207): len = 533895, overlap = 93.5 +PHY-3002 : Step(208): len = 536639, overlap = 95.9375 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.012887s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (121.3%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20342. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 723104, over cnt = 1580(4%), over = 7294, worst = 53 +PHY-1001 : End global iterations; 0.698611s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (134.2%) + +PHY-1001 : Congestion index: top1 = 78.94, top5 = 61.72, top10 = 52.19, top15 = 46.51. +PHY-3001 : End congestion estimation; 0.943756s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (124.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20164 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.098910s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (101.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000127078 +PHY-3002 : Step(209): len = 656480, overlap = 41.625 +PHY-3002 : Step(210): len = 652406, overlap = 43.0625 +PHY-3002 : Step(211): len = 646096, overlap = 48.5312 +PHY-3002 : Step(212): len = 643378, overlap = 49.7188 +PHY-3002 : Step(213): len = 643543, overlap = 51.375 +PHY-3002 : Step(214): len = 644277, overlap = 50.7188 +PHY-3002 : Step(215): len = 642886, overlap = 43.75 +PHY-3002 : Step(216): len = 641109, overlap = 47.6562 +PHY-3002 : Step(217): len = 635908, overlap = 49.3125 +PHY-3002 : Step(218): len = 631133, overlap = 49.0625 +PHY-3002 : Step(219): len = 626172, overlap = 48.5938 +PHY-3002 : Step(220): len = 622132, overlap = 50.75 +PHY-3002 : Step(221): len = 618841, overlap = 50.9688 +PHY-3002 : Step(222): len = 616221, overlap = 49.0312 +PHY-3002 : Step(223): len = 613693, overlap = 46.75 +PHY-3002 : Step(224): len = 611303, overlap = 43.1562 +PHY-3002 : Step(225): len = 610246, overlap = 40.5938 +PHY-3002 : Step(226): len = 608212, overlap = 39.9375 +PHY-3002 : Step(227): len = 606096, overlap = 40.125 +PHY-3002 : Step(228): len = 604278, overlap = 38.5312 +PHY-3002 : Step(229): len = 603121, overlap = 37.1562 +PHY-3002 : Step(230): len = 601483, overlap = 38.8438 +PHY-3002 : Step(231): len = 599813, overlap = 37.25 +PHY-3002 : Step(232): len = 598510, overlap = 36.7188 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000254155 +PHY-3002 : Step(233): len = 600916, overlap = 35.1875 +PHY-3002 : Step(234): len = 603451, overlap = 33.7188 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 66/20342. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 690688, over cnt = 2562(7%), over = 10957, worst = 42 +PHY-1001 : End global iterations; 1.694593s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (130.9%) + +PHY-1001 : Congestion index: top1 = 83.10, top5 = 62.86, top10 = 54.85, top15 = 50.01. +PHY-3001 : End congestion estimation; 1.990787s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (126.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20164 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.877147s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.8%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.223e-05 +PHY-3002 : Step(235): len = 601128, overlap = 275.562 +PHY-3002 : Step(236): len = 605215, overlap = 231.844 +PHY-3002 : Step(237): len = 603522, overlap = 218.062 +PHY-3002 : Step(238): len = 599419, overlap = 202.25 +PHY-3002 : Step(239): len = 598483, overlap = 192.125 +PHY-3002 : Step(240): len = 597352, overlap = 180.25 +PHY-3002 : Step(241): len = 594163, overlap = 175.906 +PHY-3002 : Step(242): len = 592526, overlap = 165.719 +PHY-3002 : Step(243): len = 591225, overlap = 155.156 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00018446 +PHY-3002 : Step(244): len = 591774, overlap = 152.062 +PHY-3002 : Step(245): len = 595201, overlap = 149.312 +PHY-3002 : Step(246): len = 597680, overlap = 140.375 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00036892 +PHY-3002 : Step(247): len = 601689, overlap = 126.875 +PHY-3002 : Step(248): len = 608811, overlap = 116.75 +PHY-3002 : Step(249): len = 614831, overlap = 107 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84908, tnet num: 20164, tinst num: 17762, tnode num: 115169, tedge num: 136218. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.441868s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (98.6%) + +RUN-1004 : used memory is 582 MB, reserved memory is 563 MB, peak memory is 718 MB +OPT-1001 : Total overflow 435.66 peak overflow 3.16 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1352/20342. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 708672, over cnt = 2928(8%), over = 10700, worst = 25 +PHY-1001 : End global iterations; 1.149502s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (145.4%) + +PHY-1001 : Congestion index: top1 = 76.72, top5 = 58.43, top10 = 51.55, top15 = 47.70. +PHY-1001 : End incremental global routing; 1.482573s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (136.0%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20164 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.912236s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.3%) + +OPT-1001 : 50 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17627 has valid locations, 323 needs to be replaced +PHY-3001 : design contains 18035 instances, 7530 luts, 9284 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6069 pins +PHY-3001 : Found 1238 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 638928 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16407/20615. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 724088, over cnt = 2956(8%), over = 10788, worst = 24 +PHY-1001 : End global iterations; 0.225287s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (124.8%) + +PHY-1001 : Congestion index: top1 = 76.77, top5 = 58.82, top10 = 51.80, top15 = 47.98. +PHY-3001 : End congestion estimation; 0.474208s wall, 0.500000s user + 0.031250s system = 0.531250s CPU (112.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86000, tnet num: 20437, tinst num: 18035, tnode num: 116820, tedge num: 137856. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.471795s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.8%) + +RUN-1004 : used memory is 625 MB, reserved memory is 611 MB, peak memory is 721 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20437 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.789779s wall, 2.765625s user + 0.031250s system = 2.796875s CPU (100.3%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(250): len = 637529, overlap = 0.125 +PHY-3002 : Step(251): len = 637147, overlap = 0.0625 +PHY-3002 : Step(252): len = 636861, overlap = 0 +PHY-3002 : Step(253): len = 636702, overlap = 0.0625 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16496/20615. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 721208, over cnt = 2941(8%), over = 10767, worst = 24 +PHY-1001 : End global iterations; 0.199656s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (125.2%) + +PHY-1001 : Congestion index: top1 = 77.07, top5 = 59.17, top10 = 52.17, top15 = 48.28. +PHY-3001 : End congestion estimation; 0.448817s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (114.9%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20437 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.922974s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000435219 +PHY-3002 : Step(254): len = 636625, overlap = 109.031 +PHY-3002 : Step(255): len = 636675, overlap = 109.406 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000870438 +PHY-3002 : Step(256): len = 637030, overlap = 109.312 +PHY-3002 : Step(257): len = 637342, overlap = 108.812 +PHY-3001 : Final: Len = 637342, Over = 108.812 +PHY-3001 : End incremental placement; 5.298239s wall, 5.562500s user + 0.171875s system = 5.734375s CPU (108.2%) + +OPT-1001 : Total overflow 441.31 peak overflow 3.16 +OPT-1001 : End high-fanout net optimization; 8.231764s wall, 9.093750s user + 0.203125s system = 9.296875s CPU (112.9%) + +OPT-1001 : Current memory(MB): used = 722, reserve = 709, peak = 739. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16446/20615. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 723960, over cnt = 2871(8%), over = 9745, worst = 24 +PHY-1002 : len = 776352, over cnt = 2005(5%), over = 4883, worst = 19 +PHY-1002 : len = 809288, over cnt = 945(2%), over = 2177, worst = 18 +PHY-1002 : len = 838440, over cnt = 173(0%), over = 386, worst = 18 +PHY-1002 : len = 847176, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.649064s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (139.3%) + +PHY-1001 : Congestion index: top1 = 60.73, top5 = 51.36, top10 = 47.17, top15 = 44.71. +OPT-1001 : End congestion update; 1.903340s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (134.6%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20437 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 1.001677s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 119 cells processed and 17500 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 39 cells processed and 3950 slack improved +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 700 slack improved +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved +OPT-1001 : End bottleneck based optimization; 3.372197s wall, 4.015625s user + 0.015625s system = 4.031250s CPU (119.5%) + +OPT-1001 : Current memory(MB): used = 699, reserve = 687, peak = 739. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16515/20618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 848392, over cnt = 89(0%), over = 110, worst = 3 +PHY-1002 : len = 848088, over cnt = 45(0%), over = 51, worst = 3 +PHY-1002 : len = 848640, over cnt = 10(0%), over = 10, worst = 1 +PHY-1002 : len = 848720, over cnt = 6(0%), over = 6, worst = 1 +PHY-1002 : len = 848800, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.715828s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (107.0%) + +PHY-1001 : Congestion index: top1 = 60.30, top5 = 51.22, top10 = 47.08, top15 = 44.64. +OPT-1001 : End congestion update; 0.980215s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (103.6%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.795577s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.2%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 25 cells processed and 3950 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.889635s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (102.5%) + +OPT-1001 : Current memory(MB): used = 712, reserve = 698, peak = 739. +OPT-1001 : End physical optimization; 15.246092s wall, 16.828125s user + 0.265625s system = 17.093750s CPU (112.1%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7530 LUT to BLE ... +SYN-4008 : Packed 7530 LUT and 3135 SEQ to BLE. +SYN-4003 : Packing 6152 remaining SEQ's ... +SYN-4005 : Packed 3680 SEQ with LUT/SLICE +SYN-4006 : 1004 single LUT's are left +SYN-4006 : 2472 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10002/13857 primitive instances ... +PHY-3001 : End packing; 1.660250s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.8%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6908 instances +RUN-1001 : 3380 mslices, 3380 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17611 nets +RUN-6002 WARNING: There are 2 undriven nets. +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 10029 nets have 2 pins +RUN-1001 : 5758 nets have [3 - 5] pins +RUN-1001 : 1146 nets have [6 - 10] pins +RUN-1001 : 311 nets have [11 - 20] pins +RUN-1001 : 336 nets have [21 - 99] pins +RUN-1001 : 11 nets have 100+ pins +PHY-3001 : design contains 6906 instances, 6760 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3624 pins +PHY-3001 : Found 496 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 647870, Over = 271.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 7607/17611. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 799656, over cnt = 1916(5%), over = 3207, worst = 7 +PHY-1002 : len = 807104, over cnt = 1206(3%), over = 1773, worst = 6 +PHY-1002 : len = 822440, over cnt = 418(1%), over = 553, worst = 5 +PHY-1002 : len = 827784, over cnt = 185(0%), over = 249, worst = 5 +PHY-1002 : len = 834112, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.493776s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (145.4%) + +PHY-1001 : Congestion index: top1 = 60.41, top5 = 51.63, top10 = 47.20, top15 = 44.47. +PHY-3001 : End congestion estimation; 1.881120s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (137.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73832, tnet num: 17433, tinst num: 6906, tnode num: 96457, tedge num: 123835. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.647158s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%) + +RUN-1004 : used memory is 623 MB, reserved memory is 620 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17433 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.516379s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.85105e-05 +PHY-3002 : Step(258): len = 637527, overlap = 267.5 +PHY-3002 : Step(259): len = 632709, overlap = 263.25 +PHY-3002 : Step(260): len = 630123, overlap = 256.5 +PHY-3002 : Step(261): len = 628125, overlap = 257.5 +PHY-3002 : Step(262): len = 626195, overlap = 262.5 +PHY-3002 : Step(263): len = 623733, overlap = 272.25 +PHY-3002 : Step(264): len = 621845, overlap = 265 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.70211e-05 +PHY-3002 : Step(265): len = 624237, overlap = 263 +PHY-3002 : Step(266): len = 627669, overlap = 252.75 +PHY-3002 : Step(267): len = 628735, overlap = 250.5 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000194042 +PHY-3002 : Step(268): len = 638216, overlap = 239.75 +PHY-3002 : Step(269): len = 645661, overlap = 230.25 +PHY-3002 : Step(270): len = 644599, overlap = 228.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.357420s wall, 0.281250s user + 0.562500s system = 0.843750s CPU (236.1%) + +PHY-3001 : Trial Legalized: Len = 735582 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 825/17611. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 853048, over cnt = 2699(7%), over = 4574, worst = 8 +PHY-1002 : len = 870072, over cnt = 1689(4%), over = 2495, worst = 8 +PHY-1002 : len = 895928, over cnt = 326(0%), over = 462, worst = 8 +PHY-1002 : len = 900280, over cnt = 129(0%), over = 212, worst = 6 +PHY-1002 : len = 903688, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.403787s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (143.0%) + +PHY-1001 : Congestion index: top1 = 54.48, top5 = 49.55, top10 = 46.67, top15 = 44.71. +PHY-3001 : End congestion estimation; 2.880328s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (135.6%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17433 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.898852s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.8%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160452 +PHY-3002 : Step(271): len = 706358, overlap = 45.25 +PHY-3002 : Step(272): len = 688051, overlap = 76 +PHY-3002 : Step(273): len = 672539, overlap = 118 +PHY-3002 : Step(274): len = 664925, overlap = 138.25 +PHY-3002 : Step(275): len = 659490, overlap = 154.5 +PHY-3002 : Step(276): len = 656289, overlap = 172.5 +PHY-3002 : Step(277): len = 655048, overlap = 183.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320905 +PHY-3002 : Step(278): len = 659774, overlap = 176.5 +PHY-3002 : Step(279): len = 665933, overlap = 175.75 +PHY-3002 : Step(280): len = 669620, overlap = 178.25 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00064181 +PHY-3002 : Step(281): len = 673650, overlap = 172 +PHY-3002 : Step(282): len = 685096, overlap = 159.25 +PHY-3002 : Step(283): len = 689621, overlap = 157.25 +PHY-3002 : Step(284): len = 692126, overlap = 164 +PHY-3002 : Step(285): len = 693370, overlap = 162.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.036202s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (86.3%) + +PHY-3001 : Legalized: Len = 723089, Over = 0 +PHY-3001 : Spreading special nets. 438 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.101272s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (108.0%) + +PHY-3001 : 649 instances has been re-located, deltaX = 212, deltaY = 392, maxDist = 2. +PHY-3001 : Final: Len = 733427, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73832, tnet num: 17433, tinst num: 6909, tnode num: 96457, tedge num: 123835. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.864155s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.7%) + +RUN-1004 : used memory is 637 MB, reserved memory is 650 MB, peak memory is 739 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 2955/17611. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 862216, over cnt = 2581(7%), over = 4246, worst = 6 +PHY-1002 : len = 877688, over cnt = 1373(3%), over = 1967, worst = 6 +PHY-1002 : len = 894648, over cnt = 476(1%), over = 691, worst = 6 +PHY-1002 : len = 903832, over cnt = 71(0%), over = 87, worst = 4 +PHY-1002 : len = 905120, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.050711s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (154.7%) + +PHY-1001 : Congestion index: top1 = 52.16, top5 = 48.18, top10 = 45.65, top15 = 43.87. +PHY-1001 : End incremental global routing; 2.434516s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (146.3%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17433 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.887840s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.3%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6816 has valid locations, 25 needs to be replaced +PHY-3001 : design contains 6929 instances, 6780 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 736661 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16020/17631. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 908736, over cnt = 91(0%), over = 105, worst = 5 +PHY-1002 : len = 908696, over cnt = 41(0%), over = 42, worst = 2 +PHY-1002 : len = 909128, over cnt = 7(0%), over = 7, worst = 1 +PHY-1002 : len = 909344, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.597304s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (109.9%) + +PHY-1001 : Congestion index: top1 = 52.35, top5 = 48.39, top10 = 45.84, top15 = 44.03. +PHY-3001 : End congestion estimation; 0.913449s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (106.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74028, tnet num: 17453, tinst num: 6929, tnode num: 96699, tedge num: 124071. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.920738s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (100.1%) + +RUN-1004 : used memory is 666 MB, reserved memory is 663 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17453 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.832017s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (100.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(286): len = 735630, overlap = 0.25 +PHY-3002 : Step(287): len = 735321, overlap = 0.5 +PHY-3002 : Step(288): len = 735159, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16017/17631. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 907264, over cnt = 62(0%), over = 76, worst = 5 +PHY-1002 : len = 907328, over cnt = 49(0%), over = 49, worst = 1 +PHY-1002 : len = 907848, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 907928, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.617474s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (101.2%) + +PHY-1001 : Congestion index: top1 = 52.05, top5 = 48.34, top10 = 45.77, top15 = 43.95. +PHY-3001 : End congestion estimation; 0.938546s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.9%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17453 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.873314s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000515403 +PHY-3002 : Step(289): len = 735150, overlap = 1 +PHY-3002 : Step(290): len = 735171, overlap = 1.25 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005792s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 735198, Over = 0 +PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060426s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.4%) + +PHY-3001 : 5 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1. +PHY-3001 : Final: Len = 735162, Over = 0 +PHY-3001 : End incremental placement; 6.060271s wall, 6.281250s user + 0.062500s system = 6.343750s CPU (104.7%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 9.877560s wall, 11.187500s user + 0.093750s system = 11.281250s CPU (114.2%) + +OPT-1001 : Current memory(MB): used = 746, reserve = 739, peak = 751. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15989/17631. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 907568, over cnt = 66(0%), over = 81, worst = 3 +PHY-1002 : len = 907680, over cnt = 29(0%), over = 31, worst = 3 +PHY-1002 : len = 907968, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 908008, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.641640s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (99.8%) + +PHY-1001 : Congestion index: top1 = 52.11, top5 = 48.30, top10 = 45.73, top15 = 43.92. +OPT-1001 : End congestion update; 0.959099s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (101.0%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17453 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.780540s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.1%) + +OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6841 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6929 instances, 6780 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 740567, Over = 0 +PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060926s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%) + +PHY-3001 : 21 instances has been re-located, deltaX = 9, deltaY = 11, maxDist = 2. +PHY-3001 : Final: Len = 740995, Over = 0 +PHY-3001 : End incremental legalization; 0.400960s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (113.0%) + +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 47 cells processed and 13709 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6841 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6929 instances, 6780 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 743387, Over = 0 +PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062822s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%) + +PHY-3001 : 16 instances has been re-located, deltaX = 12, deltaY = 17, maxDist = 5. +PHY-3001 : Final: Len = 743503, Over = 0 +PHY-3001 : End incremental legalization; 0.460380s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (135.8%) + +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 23 cells processed and 8839 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6841 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6929 instances, 6780 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 743763, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061420s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.8%) + +PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 7, maxDist = 2. +PHY-3001 : Final: Len = 743790, Over = 0 +PHY-3001 : End incremental legalization; 0.901900s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (50.2%) + +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 10 cells processed and 841 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3697 pins +PHY-3001 : Found 501 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 744765, Over = 0 +PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061865s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%) + +PHY-3001 : 6 instances has been re-located, deltaX = 5, deltaY = 3, maxDist = 2. +PHY-3001 : Final: Len = 744841, Over = 0 +PHY-3001 : End incremental legalization; 0.394415s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.8%) + +OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 5 cells processed and 700 slack improved +OPT-1001 : End bottleneck based optimization; 4.533910s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (99.3%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 739, peak = 751. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15606/17634. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 917296, over cnt = 179(0%), over = 232, worst = 7 +PHY-1002 : len = 917672, over cnt = 77(0%), over = 84, worst = 3 +PHY-1002 : len = 918296, over cnt = 35(0%), over = 36, worst = 2 +PHY-1002 : len = 918680, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 918728, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.852734s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (104.4%) + +PHY-1001 : Congestion index: top1 = 52.59, top5 = 48.27, top10 = 45.63, top15 = 43.86. +OPT-1001 : End congestion update; 1.193052s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (103.5%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17456 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.761396s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3697 pins +PHY-3001 : Found 501 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 745613, Over = 0 +PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.066583s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.3%) + +PHY-3001 : 3 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2. +PHY-3001 : Final: Len = 745643, Over = 0 +PHY-3001 : End incremental legalization; 0.442749s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.8%) + +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 9 cells processed and 2050 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.538796s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (105.2%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 739, peak = 751. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17456 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.746136s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15998/17634. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 919400, over cnt = 39(0%), over = 46, worst = 2 +PHY-1002 : len = 919440, over cnt = 19(0%), over = 20, worst = 2 +PHY-1002 : len = 919512, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 919544, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.638143s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (105.3%) + +PHY-1001 : Congestion index: top1 = 52.67, top5 = 48.32, top10 = 45.66, top15 = 43.88. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17456 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.760113s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.7%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.206897 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 171ps with logic level 1 +OPT-1001 : End physical optimization; 21.553903s wall, 22.937500s user + 0.140625s system = 23.078125s CPU (107.1%) + +RUN-1003 : finish command "place" in 65.942957s wall, 87.703125s user + 5.390625s system = 93.093750s CPU (141.2%) + +RUN-1004 : used memory is 615 MB, reserved memory is 601 MB, peak memory is 751 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.724262s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (173.1%) + +RUN-1004 : used memory is 616 MB, reserved memory is 602 MB, peak memory is 751 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6937 instances +RUN-1001 : 3390 mslices, 3396 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17634 nets +RUN-6002 WARNING: There are 2 undriven nets. +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 10016 nets have 2 pins +RUN-1001 : 5769 nets have [3 - 5] pins +RUN-1001 : 1156 nets have [6 - 10] pins +RUN-1001 : 316 nets have [11 - 20] pins +RUN-1001 : 349 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74081, tnet num: 17456, tinst num: 6935, tnode num: 96772, tedge num: 124144. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.650763s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.3%) + +RUN-1004 : used memory is 631 MB, reserved memory is 628 MB, peak memory is 751 MB +PHY-1001 : 3390 mslices, 3396 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17456 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[24] is skipped due to 0 input or output +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[23] is skipped due to 0 input or output +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 856160, over cnt = 2738(7%), over = 4439, worst = 8 +PHY-1002 : len = 874176, over cnt = 1503(4%), over = 2169, worst = 8 +PHY-1002 : len = 891416, over cnt = 579(1%), over = 823, worst = 7 +PHY-1002 : len = 904248, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 904416, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.073618s wall, 4.125000s user + 0.000000s system = 4.125000s CPU (134.2%) + +PHY-1001 : Congestion index: top1 = 52.74, top5 = 48.02, top10 = 45.24, top15 = 43.37. +PHY-1001 : End global routing; 3.403745s wall, 4.437500s user + 0.015625s system = 4.453125s CPU (130.8%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 721, reserve = 721, peak = 751. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-5010 Similar messages will be suppressed. +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 997, reserve = 993, peak = 997. +PHY-1001 : End build detailed router design. 4.017225s wall, 4.000000s user + 0.015625s system = 4.015625s CPU (100.0%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 273520, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 5.263086s wall, 5.265625s user + 0.000000s system = 5.265625s CPU (100.0%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 273576, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.446773s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.9%) + +PHY-1001 : Current memory(MB): used = 1033, reserve = 1030, peak = 1033. +PHY-1001 : End phase 1; 5.722266s wall, 5.718750s user + 0.000000s system = 5.718750s CPU (99.9%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 45% nets. +PHY-1001 : Routed 52% nets. +PHY-1001 : Routed 61% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.35826e+06, over cnt = 1806(0%), over = 1818, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1050, reserve = 1045, peak = 1050. +PHY-1001 : End initial routed; 27.134962s wall, 61.062500s user + 0.234375s system = 61.296875s CPU (225.9%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16555(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.784 | -0.784 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.297430s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1058, reserve = 1053, peak = 1058. +PHY-1001 : End phase 2; 30.432457s wall, 64.359375s user + 0.234375s system = 64.593750s CPU (212.3%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.135754s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%) + +PHY-1022 : len = 2.35826e+06, over cnt = 1806(0%), over = 1818, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.402973s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.9%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.32469e+06, over cnt = 729(0%), over = 731, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.525096s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (184.4%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.31896e+06, over cnt = 134(0%), over = 134, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.997523s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (155.1%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.3192e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.427262s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (113.4%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.3195e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 4; 0.230464s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.5%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16555(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.661 | -0.661 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.264901s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.0%) + +PHY-1001 : Commit to database..... +PHY-1001 : 606 feed throughs used by 414 nets +PHY-1001 : End commit to database; 2.255205s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (99.8%) + +PHY-1001 : Current memory(MB): used = 1161, reserve = 1160, peak = 1161. +PHY-1001 : End phase 3; 9.503941s wall, 11.406250s user + 0.000000s system = 11.406250s CPU (120.0%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.136063s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.4%) + +PHY-1022 : len = 2.3195e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.383281s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.8%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16555(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.661 | -0.661 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.257298s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.8%) + +PHY-1001 : Commit to database..... +PHY-1001 : 606 feed throughs used by 414 nets +PHY-1001 : End commit to database; 2.332951s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (99.8%) + +PHY-1001 : Current memory(MB): used = 1170, reserve = 1170, peak = 1170. +PHY-1001 : End phase 4; 6.001311s wall, 6.000000s user + 0.000000s system = 6.000000s CPU (100.0%) + +PHY-1003 : Routed, final wirelength = 2.3195e+06 +PHY-1001 : Current memory(MB): used = 1172, reserve = 1172, peak = 1172. +PHY-1001 : End export database. 0.060327s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.6%) + +PHY-1001 : End detail routing; 56.130781s wall, 91.953125s user + 0.250000s system = 92.203125s CPU (164.3%) + +RUN-1003 : finish command "route" in 62.266162s wall, 99.109375s user + 0.265625s system = 99.375000s CPU (159.6%) + +RUN-1004 : used memory is 1099 MB, reserved memory is 1095 MB, peak memory is 1172 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10267 out of 19600 52.38% +#reg 9427 out of 19600 48.10% +#le 12678 + #lut only 3251 out of 12678 25.64% + #reg only 2411 out of 12678 19.02% + #lut® 7016 out of 12678 55.34% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1815 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1336 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1003 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[86]_syn_34.q0 140 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/en_adc_cfg_all_d1_reg_syn_5.f0 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_300.f1 3 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P147 LVCMOS33 N/A N/A NONE + paper_in INPUT P16 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE + debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P109 LVCMOS25 8 N/A NONE + paper_out OUTPUT P104 LVCMOS25 8 N/A NONE + scan_out OUTPUT P83 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P68 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12678 |9240 |1027 |9459 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |556 |444 |23 |443 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |105 |84 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |26 |26 |0 |19 |0 |0 | +| U_ecc_gen |ecc_gen |7 |7 |0 |6 |0 |0 | +| exdev_ctl_a |exdev_ctl |747 |387 |96 |549 |0 |0 | +| u_ADconfig |AD_config |179 |134 |25 |127 |0 |0 | +| u_gen_sp |gen_sp |265 |166 |71 |119 |0 |0 | +| exdev_ctl_b |exdev_ctl |738 |376 |96 |555 |0 |0 | +| u_ADconfig |AD_config |175 |126 |25 |131 |0 |0 | +| u_gen_sp |gen_sp |266 |158 |71 |127 |0 |0 | +| sampling_fe_a |sampling_fe |3120 |2535 |306 |2098 |25 |0 | +| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |184 |105 |17 |145 |0 |0 | +| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_sort |sort |2902 |2417 |289 |1919 |25 |0 | +| rddpram_ctl |rddpram_ctl |5 |4 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u_data_prebuffer |data_prebuffer |2451 |2081 |253 |1565 |22 |0 | +| channelPart |channel_part_8478 |146 |142 |3 |130 |0 |0 | +| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |0 | +| ram_switch |ram_switch |1933 |1624 |197 |1170 |0 |0 | +| adc_addr_gen |adc_addr_gen |222 |193 |27 |121 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |8 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 | +| insert |insert |948 |669 |170 |629 |0 |0 | +| ram_switch_state |ram_switch_state |763 |762 |0 |420 |0 |0 | +| read_ram_i |read_ram |284 |237 |44 |194 |0 |0 | +| read_ram_addr |read_ram_addr |221 |181 |40 |152 |0 |0 | +| read_ram_data |read_ram_data |59 |54 |4 |38 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |347 |246 |36 |281 |3 |0 | +| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3351 |2655 |349 |2074 |25 |1 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |184 |103 |17 |147 |0 |0 | +| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u_sort |sort_rev |3133 |2545 |332 |1893 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2695 |2206 |290 |1560 |22 |1 | +| channelPart |channel_part_8478 |245 |235 |3 |140 |0 |0 | +| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 | +| ram_switch |ram_switch |1994 |1633 |197 |1137 |0 |0 | +| adc_addr_gen |adc_addr_gen |217 |190 |27 |100 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |8 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |17 |14 |3 |8 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |10 |3 |3 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 | +| insert |insert |965 |631 |170 |661 |0 |0 | +| ram_switch_state |ram_switch_state |812 |812 |0 |376 |0 |0 | +| read_ram_i |read_ram_rev |368 |263 |81 |211 |0 |0 | +| read_ram_addr |read_ram_addr_rev |300 |215 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |68 |48 |8 |49 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9954 + #2 2 3852 + #3 3 1384 + #4 4 530 + #5 5-10 1216 + #6 11-50 580 + #7 51-100 22 + #8 >500 1 + Average 2.90 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.099103s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (172.7%) + +RUN-1004 : used memory is 1101 MB, reserved memory is 1097 MB, peak memory is 1172 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74081, tnet num: 17456, tinst num: 6935, tnode num: 96772, tedge num: 124144. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.633528s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.5%) + +RUN-1004 : used memory is 1105 MB, reserved memory is 1102 MB, peak memory is 1172 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17456 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.530044s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (100.1%) + +RUN-1004 : used memory is 1107 MB, reserved memory is 1104 MB, peak memory is 1172 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6935 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17634, pip num: 173432 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 606 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 481670 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.884284s wall, 64.484375s user + 0.171875s system = 64.656250s CPU (594.0%) + +RUN-1004 : used memory is 1273 MB, reserved memory is 1269 MB, peak memory is 1389 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_154441.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_155133.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_155133.log new file mode 100644 index 0000000..f2d0c71 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_155133.log @@ -0,0 +1,2004 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:51:33 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(721) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(754) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(756) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(762) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(936) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1025) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1326) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1337) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1355) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1537) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1933) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.453597s wall, 2.343750s user + 0.109375s system = 2.453125s CPU (100.0%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17745 instances +RUN-0007 : 7435 luts, 9087 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20323 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13378 nets have 2 pins +RUN-1001 : 5502 nets have [3 - 5] pins +RUN-1001 : 1031 nets have [6 - 10] pins +RUN-1001 : 159 nets have [11 - 20] pins +RUN-1001 : 179 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2012 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17743 instances, 7435 luts, 9087 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5941 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.141745s wall, 1.093750s user + 0.046875s system = 1.140625s CPU (99.9%) + +RUN-1004 : used memory is 539 MB, reserved memory is 515 MB, peak memory is 539 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.928570s wall, 1.859375s user + 0.062500s system = 1.921875s CPU (99.7%) + +PHY-3001 : Found 1219 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.03672e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17743. +PHY-3001 : Level 1 #clusters 2001. +PHY-3001 : End clustering; 0.128536s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.2%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28172e+06, overlap = 450.688 +PHY-3002 : Step(2): len = 1.17432e+06, overlap = 496.219 +PHY-3002 : Step(3): len = 856653, overlap = 576.094 +PHY-3002 : Step(4): len = 786084, overlap = 628.906 +PHY-3002 : Step(5): len = 595952, overlap = 759.281 +PHY-3002 : Step(6): len = 521360, overlap = 797.906 +PHY-3002 : Step(7): len = 440616, overlap = 913.812 +PHY-3002 : Step(8): len = 411923, overlap = 929.219 +PHY-3002 : Step(9): len = 368492, overlap = 1011.84 +PHY-3002 : Step(10): len = 344447, overlap = 1045.5 +PHY-3002 : Step(11): len = 308507, overlap = 1078.34 +PHY-3002 : Step(12): len = 283987, overlap = 1137.59 +PHY-3002 : Step(13): len = 260945, overlap = 1173.41 +PHY-3002 : Step(14): len = 239493, overlap = 1234.88 +PHY-3002 : Step(15): len = 224806, overlap = 1281.34 +PHY-3002 : Step(16): len = 206499, overlap = 1315.41 +PHY-3002 : Step(17): len = 190194, overlap = 1348.53 +PHY-3002 : Step(18): len = 172136, overlap = 1365.78 +PHY-3002 : Step(19): len = 161542, overlap = 1372.78 +PHY-3002 : Step(20): len = 146202, overlap = 1401.66 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10457e-06 +PHY-3002 : Step(21): len = 146798, overlap = 1396 +PHY-3002 : Step(22): len = 172633, overlap = 1332.34 +PHY-3002 : Step(23): len = 178535, overlap = 1234.84 +PHY-3002 : Step(24): len = 185020, overlap = 1204.31 +PHY-3002 : Step(25): len = 187522, overlap = 1183.28 +PHY-3002 : Step(26): len = 188298, overlap = 1152.5 +PHY-3002 : Step(27): len = 187442, overlap = 1116.62 +PHY-3002 : Step(28): len = 187095, overlap = 1079.91 +PHY-3002 : Step(29): len = 187618, overlap = 1077.53 +PHY-3002 : Step(30): len = 186342, overlap = 1047.97 +PHY-3002 : Step(31): len = 187852, overlap = 1046.09 +PHY-3002 : Step(32): len = 185978, overlap = 1058.34 +PHY-3002 : Step(33): len = 184677, overlap = 1048.94 +PHY-3002 : Step(34): len = 181811, overlap = 1031.5 +PHY-3002 : Step(35): len = 181702, overlap = 1027.47 +PHY-3002 : Step(36): len = 179387, overlap = 1046.06 +PHY-3002 : Step(37): len = 178992, overlap = 1058.69 +PHY-3002 : Step(38): len = 176523, overlap = 1062.59 +PHY-3002 : Step(39): len = 176436, overlap = 1064.91 +PHY-3002 : Step(40): len = 173457, overlap = 1072.81 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20914e-06 +PHY-3002 : Step(41): len = 177308, overlap = 1065.06 +PHY-3002 : Step(42): len = 190276, overlap = 1080.53 +PHY-3002 : Step(43): len = 194494, overlap = 1081.88 +PHY-3002 : Step(44): len = 197374, overlap = 1069.81 +PHY-3002 : Step(45): len = 198039, overlap = 1057.97 +PHY-3002 : Step(46): len = 198583, overlap = 1045.69 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.41828e-06 +PHY-3002 : Step(47): len = 205524, overlap = 1006.62 +PHY-3002 : Step(48): len = 221752, overlap = 868.594 +PHY-3002 : Step(49): len = 231082, overlap = 802.812 +PHY-3002 : Step(50): len = 239235, overlap = 809.188 +PHY-3002 : Step(51): len = 243212, overlap = 792.156 +PHY-3002 : Step(52): len = 244863, overlap = 759.938 +PHY-3002 : Step(53): len = 244837, overlap = 739.594 +PHY-3002 : Step(54): len = 243958, overlap = 733.281 +PHY-3002 : Step(55): len = 242207, overlap = 716.531 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.83657e-06 +PHY-3002 : Step(56): len = 257674, overlap = 678.75 +PHY-3002 : Step(57): len = 281477, overlap = 595.875 +PHY-3002 : Step(58): len = 290479, overlap = 533.531 +PHY-3002 : Step(59): len = 294876, overlap = 530.156 +PHY-3002 : Step(60): len = 292681, overlap = 540 +PHY-3002 : Step(61): len = 290012, overlap = 548.75 +PHY-3002 : Step(62): len = 286094, overlap = 558.438 +PHY-3002 : Step(63): len = 285239, overlap = 556.75 +PHY-3002 : Step(64): len = 286116, overlap = 564 +PHY-3002 : Step(65): len = 287019, overlap = 557.344 +PHY-3002 : Step(66): len = 286138, overlap = 561.25 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76731e-05 +PHY-3002 : Step(67): len = 304136, overlap = 548.594 +PHY-3002 : Step(68): len = 321073, overlap = 520.75 +PHY-3002 : Step(69): len = 326901, overlap = 462.375 +PHY-3002 : Step(70): len = 328175, overlap = 440.594 +PHY-3002 : Step(71): len = 326166, overlap = 419.219 +PHY-3002 : Step(72): len = 325697, overlap = 391.344 +PHY-3002 : Step(73): len = 325583, overlap = 378.188 +PHY-3002 : Step(74): len = 327742, overlap = 371.938 +PHY-3002 : Step(75): len = 326770, overlap = 377.25 +PHY-3002 : Step(76): len = 326758, overlap = 373.531 +PHY-3002 : Step(77): len = 326655, overlap = 382.125 +PHY-3002 : Step(78): len = 328557, overlap = 385.25 +PHY-3002 : Step(79): len = 327968, overlap = 384.719 +PHY-3002 : Step(80): len = 327971, overlap = 385.906 +PHY-3002 : Step(81): len = 328104, overlap = 396.406 +PHY-3002 : Step(82): len = 328472, overlap = 390.531 +PHY-3002 : Step(83): len = 328239, overlap = 387.719 +PHY-3002 : Step(84): len = 329143, overlap = 393.812 +PHY-3002 : Step(85): len = 327973, overlap = 397.875 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.53463e-05 +PHY-3002 : Step(86): len = 345898, overlap = 359.469 +PHY-3002 : Step(87): len = 359117, overlap = 339.75 +PHY-3002 : Step(88): len = 360816, overlap = 334.688 +PHY-3002 : Step(89): len = 361674, overlap = 334.812 +PHY-3002 : Step(90): len = 361511, overlap = 325.656 +PHY-3002 : Step(91): len = 362609, overlap = 312.125 +PHY-3002 : Step(92): len = 361131, overlap = 312.438 +PHY-3002 : Step(93): len = 361755, overlap = 315.188 +PHY-3002 : Step(94): len = 362466, overlap = 298.281 +PHY-3002 : Step(95): len = 363451, overlap = 296.312 +PHY-3002 : Step(96): len = 361923, overlap = 299.594 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.06925e-05 +PHY-3002 : Step(97): len = 380686, overlap = 280.875 +PHY-3002 : Step(98): len = 393877, overlap = 282.906 +PHY-3002 : Step(99): len = 391804, overlap = 268.094 +PHY-3002 : Step(100): len = 393310, overlap = 250.5 +PHY-3002 : Step(101): len = 394805, overlap = 250.688 +PHY-3002 : Step(102): len = 397473, overlap = 253 +PHY-3002 : Step(103): len = 394544, overlap = 256.438 +PHY-3002 : Step(104): len = 394989, overlap = 257.156 +PHY-3002 : Step(105): len = 396401, overlap = 240.719 +PHY-3002 : Step(106): len = 397811, overlap = 239 +PHY-3002 : Step(107): len = 396411, overlap = 242.188 +PHY-3002 : Step(108): len = 397568, overlap = 223.469 +PHY-3002 : Step(109): len = 399560, overlap = 225.5 +PHY-3002 : Step(110): len = 400464, overlap = 210.938 +PHY-3002 : Step(111): len = 398255, overlap = 214.312 +PHY-3002 : Step(112): len = 398369, overlap = 214.938 +PHY-3002 : Step(113): len = 399100, overlap = 209.25 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141385 +PHY-3002 : Step(114): len = 415646, overlap = 186.344 +PHY-3002 : Step(115): len = 424994, overlap = 208.875 +PHY-3002 : Step(116): len = 421927, overlap = 213.625 +PHY-3002 : Step(117): len = 421730, overlap = 206.906 +PHY-3002 : Step(118): len = 426278, overlap = 188.875 +PHY-3002 : Step(119): len = 429889, overlap = 188 +PHY-3002 : Step(120): len = 426628, overlap = 190.188 +PHY-3002 : Step(121): len = 427999, overlap = 193.25 +PHY-3002 : Step(122): len = 431889, overlap = 189.969 +PHY-3002 : Step(123): len = 435532, overlap = 192.469 +PHY-3002 : Step(124): len = 432226, overlap = 190 +PHY-3002 : Step(125): len = 432069, overlap = 180.531 +PHY-3002 : Step(126): len = 434337, overlap = 182.5 +PHY-3002 : Step(127): len = 436053, overlap = 179.25 +PHY-3002 : Step(128): len = 433744, overlap = 172.312 +PHY-3002 : Step(129): len = 433743, overlap = 176.469 +PHY-3002 : Step(130): len = 435984, overlap = 177.688 +PHY-3002 : Step(131): len = 437181, overlap = 180 +PHY-3002 : Step(132): len = 434829, overlap = 179.125 +PHY-3002 : Step(133): len = 434539, overlap = 181.906 +PHY-3002 : Step(134): len = 436034, overlap = 184.469 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00028277 +PHY-3002 : Step(135): len = 446842, overlap = 173.188 +PHY-3002 : Step(136): len = 456483, overlap = 164.562 +PHY-3002 : Step(137): len = 457435, overlap = 166.531 +PHY-3002 : Step(138): len = 458660, overlap = 169.531 +PHY-3002 : Step(139): len = 462075, overlap = 163.125 +PHY-3002 : Step(140): len = 464987, overlap = 160.781 +PHY-3002 : Step(141): len = 463523, overlap = 163.281 +PHY-3002 : Step(142): len = 463423, overlap = 163.469 +PHY-3002 : Step(143): len = 464548, overlap = 158.156 +PHY-3002 : Step(144): len = 466447, overlap = 164.5 +PHY-3002 : Step(145): len = 466639, overlap = 155.094 +PHY-3002 : Step(146): len = 468136, overlap = 162.219 +PHY-3002 : Step(147): len = 468952, overlap = 161.062 +PHY-3002 : Step(148): len = 469376, overlap = 160.781 +PHY-3002 : Step(149): len = 468182, overlap = 167.469 +PHY-3002 : Step(150): len = 468430, overlap = 166.562 +PHY-3002 : Step(151): len = 469025, overlap = 160.844 +PHY-3002 : Step(152): len = 469376, overlap = 158.219 +PHY-3002 : Step(153): len = 468892, overlap = 157.344 +PHY-3002 : Step(154): len = 469813, overlap = 158.219 +PHY-3002 : Step(155): len = 470872, overlap = 155.562 +PHY-3002 : Step(156): len = 471704, overlap = 155.844 +PHY-3002 : Step(157): len = 470506, overlap = 155.469 +PHY-3002 : Step(158): len = 470267, overlap = 156.344 +PHY-3002 : Step(159): len = 470463, overlap = 162.594 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000563391 +PHY-3002 : Step(160): len = 476929, overlap = 161.812 +PHY-3002 : Step(161): len = 484567, overlap = 151.156 +PHY-3002 : Step(162): len = 486813, overlap = 149.281 +PHY-3002 : Step(163): len = 488813, overlap = 149.875 +PHY-3002 : Step(164): len = 490570, overlap = 140.344 +PHY-3002 : Step(165): len = 491244, overlap = 141.281 +PHY-3002 : Step(166): len = 490396, overlap = 141.625 +PHY-3002 : Step(167): len = 490181, overlap = 141.156 +PHY-3002 : Step(168): len = 490945, overlap = 140.75 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0011016 +PHY-3002 : Step(169): len = 496449, overlap = 127.094 +PHY-3002 : Step(170): len = 504286, overlap = 130.031 +PHY-3002 : Step(171): len = 506351, overlap = 122.312 +PHY-3002 : Step(172): len = 507900, overlap = 123.844 +PHY-3002 : Step(173): len = 509788, overlap = 120.188 +PHY-3002 : Step(174): len = 511974, overlap = 114.219 +PHY-3002 : Step(175): len = 512667, overlap = 116.344 +PHY-3002 : Step(176): len = 513356, overlap = 115.906 +PHY-3002 : Step(177): len = 514345, overlap = 110.969 +PHY-3002 : Step(178): len = 514859, overlap = 111.062 +PHY-3002 : Step(179): len = 514889, overlap = 109.375 +PHY-3002 : Step(180): len = 514907, overlap = 107.562 +PHY-3002 : Step(181): len = 515226, overlap = 113.094 +PHY-3002 : Step(182): len = 515315, overlap = 115.344 +PHY-3002 : Step(183): len = 515218, overlap = 112.844 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0019155 +PHY-3002 : Step(184): len = 518415, overlap = 110.375 +PHY-3002 : Step(185): len = 524256, overlap = 105.188 +PHY-3002 : Step(186): len = 525904, overlap = 103.719 +PHY-3002 : Step(187): len = 527046, overlap = 101.125 +PHY-3002 : Step(188): len = 528391, overlap = 103.469 +PHY-3002 : Step(189): len = 529211, overlap = 107.188 +PHY-3002 : Step(190): len = 529278, overlap = 108.062 +PHY-3002 : Step(191): len = 529454, overlap = 108.406 +PHY-3002 : Step(192): len = 530029, overlap = 109.812 +PHY-3002 : Step(193): len = 530358, overlap = 111.219 +PHY-3002 : Step(194): len = 530896, overlap = 109.219 +PHY-3002 : Step(195): len = 531644, overlap = 108.031 +PHY-3002 : Step(196): len = 532126, overlap = 108.594 +PHY-3002 : Step(197): len = 532260, overlap = 108.688 +PHY-3002 : Step(198): len = 532185, overlap = 107.188 +PHY-3002 : Step(199): len = 532272, overlap = 106.312 +PHY-3002 : Step(200): len = 532808, overlap = 102.562 +PHY-3002 : Step(201): len = 533198, overlap = 103.875 +PHY-3002 : Step(202): len = 533068, overlap = 102.125 +PHY-3002 : Step(203): len = 533068, overlap = 102.125 +PHY-3002 : Step(204): len = 533123, overlap = 103.125 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.011261s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 714624, over cnt = 1568(4%), over = 7178, worst = 44 +PHY-1001 : End global iterations; 0.718858s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (136.9%) + +PHY-1001 : Congestion index: top1 = 75.67, top5 = 59.90, top10 = 51.49, top15 = 46.05. +PHY-3001 : End congestion estimation; 0.948863s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (128.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.862761s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126945 +PHY-3002 : Step(205): len = 651620, overlap = 56.3125 +PHY-3002 : Step(206): len = 653297, overlap = 65.5 +PHY-3002 : Step(207): len = 647753, overlap = 69.3438 +PHY-3002 : Step(208): len = 641445, overlap = 63.8438 +PHY-3002 : Step(209): len = 635799, overlap = 61.0312 +PHY-3002 : Step(210): len = 633738, overlap = 62.5938 +PHY-3002 : Step(211): len = 633098, overlap = 61.125 +PHY-3002 : Step(212): len = 632272, overlap = 56.75 +PHY-3002 : Step(213): len = 630468, overlap = 53.875 +PHY-3002 : Step(214): len = 627875, overlap = 48.125 +PHY-3002 : Step(215): len = 624830, overlap = 45.5312 +PHY-3002 : Step(216): len = 622143, overlap = 43.75 +PHY-3002 : Step(217): len = 620834, overlap = 37.25 +PHY-3002 : Step(218): len = 619641, overlap = 35.625 +PHY-3002 : Step(219): len = 618180, overlap = 34.1562 +PHY-3002 : Step(220): len = 618174, overlap = 37.2188 +PHY-3002 : Step(221): len = 617188, overlap = 36.9062 +PHY-3002 : Step(222): len = 615032, overlap = 38.0625 +PHY-3002 : Step(223): len = 612216, overlap = 38.9688 +PHY-3002 : Step(224): len = 610202, overlap = 35.9688 +PHY-3002 : Step(225): len = 608415, overlap = 36.0312 +PHY-3002 : Step(226): len = 606921, overlap = 38.9062 +PHY-3002 : Step(227): len = 605497, overlap = 37.1562 +PHY-3002 : Step(228): len = 603987, overlap = 36.625 +PHY-3002 : Step(229): len = 602886, overlap = 37.875 +PHY-3002 : Step(230): len = 601605, overlap = 36.7812 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025389 +PHY-3002 : Step(231): len = 605623, overlap = 35.1875 +PHY-3002 : Step(232): len = 608395, overlap = 33.9375 +PHY-3002 : Step(233): len = 609611, overlap = 32.0938 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000434206 +PHY-3002 : Step(234): len = 618373, overlap = 34.3438 +PHY-3002 : Step(235): len = 633524, overlap = 31.4062 +PHY-3002 : Step(236): len = 634716, overlap = 31.9062 +PHY-3002 : Step(237): len = 635266, overlap = 28.625 +PHY-3002 : Step(238): len = 635530, overlap = 26.0938 +PHY-3002 : Step(239): len = 634102, overlap = 28.7812 +PHY-3002 : Step(240): len = 634254, overlap = 30.9062 +PHY-3002 : Step(241): len = 634458, overlap = 33 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 48/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 719896, over cnt = 2733(7%), over = 11815, worst = 44 +PHY-1001 : End global iterations; 1.771193s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (126.2%) + +PHY-1001 : Congestion index: top1 = 83.60, top5 = 64.83, top10 = 56.55, top15 = 51.64. +PHY-3001 : End congestion estimation; 2.045193s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (123.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.884343s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (98.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000107045 +PHY-3002 : Step(242): len = 629397, overlap = 229.344 +PHY-3002 : Step(243): len = 630978, overlap = 186.312 +PHY-3002 : Step(244): len = 623229, overlap = 162.406 +PHY-3002 : Step(245): len = 618172, overlap = 145.188 +PHY-3002 : Step(246): len = 613147, overlap = 126.312 +PHY-3002 : Step(247): len = 610145, overlap = 125.594 +PHY-3002 : Step(248): len = 605265, overlap = 124.156 +PHY-3002 : Step(249): len = 603035, overlap = 127.125 +PHY-3002 : Step(250): len = 600841, overlap = 120.906 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000214089 +PHY-3002 : Step(251): len = 601155, overlap = 118.719 +PHY-3002 : Step(252): len = 603472, overlap = 114.906 +PHY-3002 : Step(253): len = 605803, overlap = 105.031 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000428178 +PHY-3002 : Step(254): len = 611464, overlap = 95.9688 +PHY-3002 : Step(255): len = 619589, overlap = 83.3125 +PHY-3002 : Step(256): len = 625102, overlap = 79.1562 +PHY-3002 : Step(257): len = 627521, overlap = 76.625 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84872, tnet num: 20145, tinst num: 17743, tnode num: 115088, tedge num: 136184. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.453367s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.0%) + +RUN-1004 : used memory is 582 MB, reserved memory is 564 MB, peak memory is 718 MB +OPT-1001 : Total overflow 384.84 peak overflow 3.47 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1093/20323. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 724368, over cnt = 3038(8%), over = 10466, worst = 26 +PHY-1001 : End global iterations; 1.231429s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (143.4%) + +PHY-1001 : Congestion index: top1 = 70.22, top5 = 56.96, top10 = 50.61, top15 = 46.87. +PHY-1001 : End incremental global routing; 1.578633s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (134.6%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20145 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.927718s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.4%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17607 has valid locations, 349 needs to be replaced +PHY-3001 : design contains 18041 instances, 7532 luts, 9288 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6063 pins +PHY-3001 : Found 1231 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 650874 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16601/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738040, over cnt = 3068(8%), over = 10637, worst = 26 +PHY-1001 : End global iterations; 0.237441s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (125.0%) + +PHY-1001 : Congestion index: top1 = 69.94, top5 = 57.07, top10 = 50.94, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.491496s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (114.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86082, tnet num: 20443, tinst num: 18041, tnode num: 116915, tedge num: 138008. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.445521s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.4%) + +RUN-1004 : used memory is 628 MB, reserved memory is 627 MB, peak memory is 723 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.398639s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (99.7%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(258): len = 650035, overlap = 0.125 +PHY-3002 : Step(259): len = 649700, overlap = 0.125 +PHY-3002 : Step(260): len = 649450, overlap = 0.125 +PHY-3002 : Step(261): len = 649177, overlap = 0.125 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16724/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 735584, over cnt = 3070(8%), over = 10643, worst = 26 +PHY-1001 : End global iterations; 0.191433s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.1%) + +PHY-1001 : Congestion index: top1 = 70.19, top5 = 57.15, top10 = 50.97, top15 = 47.24. +PHY-3001 : End congestion estimation; 0.444281s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (105.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.926605s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.5%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000334276 +PHY-3002 : Step(262): len = 649093, overlap = 79.4375 +PHY-3002 : Step(263): len = 649168, overlap = 78.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000668551 +PHY-3002 : Step(264): len = 649153, overlap = 79.0312 +PHY-3002 : Step(265): len = 649644, overlap = 78.625 +PHY-3001 : Final: Len = 649644, Over = 78.625 +PHY-3001 : End incremental placement; 4.916959s wall, 5.062500s user + 0.171875s system = 5.234375s CPU (106.5%) + +OPT-1001 : Total overflow 390.09 peak overflow 3.47 +OPT-1001 : End high-fanout net optimization; 7.962494s wall, 8.718750s user + 0.187500s system = 8.906250s CPU (111.9%) + +OPT-1001 : Current memory(MB): used = 726, reserve = 712, peak = 742. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16679/20621. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 738800, over cnt = 3016(8%), over = 9702, worst = 26 +PHY-1002 : len = 785712, over cnt = 1985(5%), over = 4886, worst = 21 +PHY-1002 : len = 825896, over cnt = 801(2%), over = 1646, worst = 16 +PHY-1002 : len = 844056, over cnt = 213(0%), over = 333, worst = 11 +PHY-1002 : len = 848840, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.712360s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (146.0%) + +PHY-1001 : Congestion index: top1 = 57.22, top5 = 49.72, top10 = 45.96, top15 = 43.61. +OPT-1001 : End congestion update; 1.975167s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (140.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20443 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.799865s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.6%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 115 cells processed and 15100 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 1084 slack improved +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved +OPT-1001 : End bottleneck based optimization; 3.088792s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (126.0%) + +OPT-1001 : Current memory(MB): used = 702, reserve = 692, peak = 742. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16775/20623. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849680, over cnt = 74(0%), over = 94, worst = 4 +PHY-1002 : len = 849528, over cnt = 33(0%), over = 36, worst = 3 +PHY-1002 : len = 849784, over cnt = 8(0%), over = 8, worst = 1 +PHY-1002 : len = 849832, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 849848, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.772275s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.2%) + +PHY-1001 : Congestion index: top1 = 56.90, top5 = 49.64, top10 = 45.91, top15 = 43.56. +OPT-1001 : End congestion update; 1.050552s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (101.1%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20445 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.796396s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.1%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 4450 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.965104s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (101.0%) + +OPT-1001 : Current memory(MB): used = 712, reserve = 698, peak = 742. +OPT-1001 : End physical optimization; 14.778135s wall, 16.421875s user + 0.218750s system = 16.640625s CPU (112.6%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7532 LUT to BLE ... +SYN-4008 : Packed 7532 LUT and 3133 SEQ to BLE. +SYN-4003 : Packing 6157 remaining SEQ's ... +SYN-4005 : Packed 3725 SEQ with LUT/SLICE +SYN-4006 : 977 single LUT's are left +SYN-4006 : 2432 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9964/13787 primitive instances ... +PHY-3001 : End packing; 1.610910s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6874 instances +RUN-1001 : 3363 mslices, 3363 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17618 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10005 nets have 2 pins +RUN-1001 : 5769 nets have [3 - 5] pins +RUN-1001 : 1139 nets have [6 - 10] pins +RUN-1001 : 345 nets have [11 - 20] pins +RUN-1001 : 327 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6872 instances, 6726 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3573 pins +PHY-3001 : Found 490 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 662223, Over = 253.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 7617/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 811720, over cnt = 1957(5%), over = 3182, worst = 8 +PHY-1002 : len = 819944, over cnt = 1208(3%), over = 1726, worst = 6 +PHY-1002 : len = 834160, over cnt = 468(1%), over = 625, worst = 5 +PHY-1002 : len = 841744, over cnt = 134(0%), over = 157, worst = 4 +PHY-1002 : len = 844704, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.634464s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (133.8%) + +PHY-1001 : Congestion index: top1 = 58.53, top5 = 50.73, top10 = 46.56, top15 = 43.91. +PHY-3001 : End congestion estimation; 2.032492s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (126.8%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6872, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.620075s wall, 1.578125s user + 0.046875s system = 1.625000s CPU (100.3%) + +RUN-1004 : used memory is 623 MB, reserved memory is 616 MB, peak memory is 742 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.483894s wall, 2.437500s user + 0.046875s system = 2.484375s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.65564e-05 +PHY-3002 : Step(266): len = 649520, overlap = 250 +PHY-3002 : Step(267): len = 642403, overlap = 253.75 +PHY-3002 : Step(268): len = 637448, overlap = 255 +PHY-3002 : Step(269): len = 634168, overlap = 254 +PHY-3002 : Step(270): len = 632517, overlap = 259.25 +PHY-3002 : Step(271): len = 631073, overlap = 264.75 +PHY-3002 : Step(272): len = 627992, overlap = 264.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.31129e-05 +PHY-3002 : Step(273): len = 630887, overlap = 259.75 +PHY-3002 : Step(274): len = 634775, overlap = 254 +PHY-3002 : Step(275): len = 634921, overlap = 251.25 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000186226 +PHY-3002 : Step(276): len = 644232, overlap = 241.25 +PHY-3002 : Step(277): len = 652624, overlap = 229.25 +PHY-3002 : Step(278): len = 652092, overlap = 229.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.364836s wall, 0.390625s user + 0.562500s system = 0.953125s CPU (261.2%) + +PHY-3001 : Trial Legalized: Len = 732801 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 884/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 849856, over cnt = 2629(7%), over = 4435, worst = 8 +PHY-1002 : len = 866496, over cnt = 1574(4%), over = 2279, worst = 6 +PHY-1002 : len = 885736, over cnt = 545(1%), over = 755, worst = 6 +PHY-1002 : len = 895568, over cnt = 99(0%), over = 127, worst = 5 +PHY-1002 : len = 897712, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.340981s wall, 3.406250s user + 0.046875s system = 3.453125s CPU (147.5%) + +PHY-1001 : Congestion index: top1 = 56.34, top5 = 49.93, top10 = 46.51, top15 = 44.33. +PHY-3001 : End congestion estimation; 2.810708s wall, 3.875000s user + 0.046875s system = 3.921875s CPU (139.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.852560s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165 +PHY-3002 : Step(279): len = 706565, overlap = 45.75 +PHY-3002 : Step(280): len = 692044, overlap = 70.5 +PHY-3002 : Step(281): len = 678987, overlap = 101.75 +PHY-3002 : Step(282): len = 671353, overlap = 129 +PHY-3002 : Step(283): len = 666387, overlap = 147 +PHY-3002 : Step(284): len = 664006, overlap = 154.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033 +PHY-3002 : Step(285): len = 669536, overlap = 153.25 +PHY-3002 : Step(286): len = 675137, overlap = 150.25 +PHY-3002 : Step(287): len = 677080, overlap = 152.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00064827 +PHY-3002 : Step(288): len = 680934, overlap = 147.75 +PHY-3002 : Step(289): len = 688915, overlap = 146.25 +PHY-3002 : Step(290): len = 698496, overlap = 140.25 +PHY-3002 : Step(291): len = 700456, overlap = 140.75 +PHY-3002 : Step(292): len = 701680, overlap = 142.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.033979s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (138.0%) + +PHY-3001 : Legalized: Len = 728102, Over = 0 +PHY-3001 : Spreading special nets. 443 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.100898s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (108.4%) + +PHY-3001 : 628 instances has been re-located, deltaX = 184, deltaY = 381, maxDist = 2. +PHY-3001 : Final: Len = 737976, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73791, tnet num: 17440, tinst num: 6875, tnode num: 96306, tedge num: 123817. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.873318s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.1%) + +RUN-1004 : used memory is 640 MB, reserved memory is 649 MB, peak memory is 742 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 3082/17618. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 863136, over cnt = 2610(7%), over = 4296, worst = 6 +PHY-1002 : len = 879048, over cnt = 1415(4%), over = 2042, worst = 6 +PHY-1002 : len = 895448, over cnt = 542(1%), over = 771, worst = 5 +PHY-1002 : len = 904664, over cnt = 130(0%), over = 187, worst = 5 +PHY-1002 : len = 907272, over cnt = 11(0%), over = 19, worst = 5 +PHY-1001 : End global iterations; 2.086045s wall, 3.015625s user + 0.062500s system = 3.078125s CPU (147.6%) + +PHY-1001 : Congestion index: top1 = 56.10, top5 = 49.56, top10 = 46.28, top15 = 44.25. +PHY-1001 : End incremental global routing; 2.463333s wall, 3.390625s user + 0.062500s system = 3.453125s CPU (140.2%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17440 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.876749s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.8%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6782 has valid locations, 30 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 741838 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16076/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 911648, over cnt = 110(0%), over = 130, worst = 5 +PHY-1002 : len = 911776, over cnt = 60(0%), over = 65, worst = 3 +PHY-1002 : len = 912328, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 912392, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 912456, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.796324s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (104.0%) + +PHY-1001 : Congestion index: top1 = 56.19, top5 = 49.69, top10 = 46.41, top15 = 44.36. +PHY-3001 : End congestion estimation; 1.117246s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74012, tnet num: 17472, tinst num: 6900, tnode num: 96587, tedge num: 124127. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.838552s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (100.3%) + +RUN-1004 : used memory is 664 MB, reserved memory is 657 MB, peak memory is 742 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.732292s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (100.1%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(293): len = 740891, overlap = 0.5 +PHY-3002 : Step(294): len = 740538, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16066/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910472, over cnt = 75(0%), over = 95, worst = 6 +PHY-1002 : len = 910680, over cnt = 32(0%), over = 34, worst = 2 +PHY-1002 : len = 911064, over cnt = 9(0%), over = 9, worst = 1 +PHY-1002 : len = 911200, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 911216, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.790916s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (106.7%) + +PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.69, top10 = 46.41, top15 = 44.34. +PHY-3001 : End congestion estimation; 1.099752s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (103.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.102123s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (78.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160642 +PHY-3002 : Step(295): len = 740237, overlap = 1.75 +PHY-3002 : Step(296): len = 740365, overlap = 2 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005897s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (264.9%) + +PHY-3001 : Legalized: Len = 740500, Over = 0 +PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060720s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.9%) + +PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 2. +PHY-3001 : Final: Len = 740436, Over = 0 +PHY-3001 : End incremental placement; 6.603331s wall, 6.609375s user + 0.093750s system = 6.703125s CPU (101.5%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 10.461729s wall, 11.484375s user + 0.156250s system = 11.640625s CPU (111.3%) + +OPT-1001 : Current memory(MB): used = 746, reserve = 742, peak = 750. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16051/17650. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 910608, over cnt = 64(0%), over = 75, worst = 3 +PHY-1002 : len = 910552, over cnt = 29(0%), over = 30, worst = 2 +PHY-1002 : len = 910712, over cnt = 5(0%), over = 5, worst = 1 +PHY-1002 : len = 910776, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 910792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.771600s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (107.3%) + +PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.74, top10 = 46.39, top15 = 44.32. +OPT-1001 : End congestion update; 1.083142s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (103.9%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17472 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.720397s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.8%) + +OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 743728, Over = 0 +PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062873s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.4%) + +PHY-3001 : 20 instances has been re-located, deltaX = 9, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 744032, Over = 0 +PHY-3001 : End incremental legalization; 0.395921s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.7%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 10363 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748708, Over = 0 +PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060519s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%) + +PHY-3001 : 18 instances has been re-located, deltaX = 7, deltaY = 16, maxDist = 2. +PHY-3001 : Final: Len = 749102, Over = 0 +PHY-3001 : End incremental legalization; 0.382695s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.0%) + +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 30 cells processed and 9680 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6812 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6900 instances, 6751 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3656 pins +PHY-3001 : Found 493 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 748964, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.064143s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.4%) + +PHY-3001 : 6 instances has been re-located, deltaX = 5, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 749362, Over = 0 +PHY-3001 : End incremental legalization; 0.416137s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.4%) + +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 649 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750417, Over = 0 +PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.065324s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%) + +PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 3. +PHY-3001 : Final: Len = 750441, Over = 0 +PHY-3001 : End incremental legalization; 0.420651s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (104.0%) + +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 1081 slack improved +OPT-1001 : End bottleneck based optimization; 3.975103s wall, 4.093750s user + 0.015625s system = 4.109375s CPU (103.4%) + +OPT-1001 : Current memory(MB): used = 746, reserve = 742, peak = 750. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 15658/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 921656, over cnt = 225(0%), over = 304, worst = 9 +PHY-1002 : len = 921944, over cnt = 124(0%), over = 136, worst = 4 +PHY-1002 : len = 922344, over cnt = 84(0%), over = 89, worst = 2 +PHY-1002 : len = 923408, over cnt = 19(0%), over = 19, worst = 1 +PHY-1002 : len = 923864, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.897835s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (102.7%) + +PHY-1001 : Congestion index: top1 = 56.08, top5 = 49.86, top10 = 46.58, top15 = 44.47. +OPT-1001 : End congestion update; 1.218596s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (102.6%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.721555s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6818 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6906 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3657 pins +PHY-3001 : Found 497 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 750211, Over = 0 +PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060810s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.8%) + +PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 9, maxDist = 2. +PHY-3001 : Final: Len = 750501, Over = 0 +PHY-3001 : End incremental legalization; 0.390384s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.1%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.465176s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (103.3%) + +OPT-1001 : Current memory(MB): used = 746, reserve = 742, peak = 750. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.721853s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Reuse net number 16067/17653. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 923880, over cnt = 30(0%), over = 31, worst = 2 +PHY-1002 : len = 923824, over cnt = 13(0%), over = 13, worst = 1 +PHY-1002 : len = 923856, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 923856, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 923904, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.786395s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.3%) + +PHY-1001 : Congestion index: top1 = 56.12, top5 = 49.87, top10 = 46.62, top15 = 44.51. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.723511s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.3%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.620690 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 221ps with logic level 1 +OPT-1001 : End physical optimization; 21.582468s wall, 22.796875s user + 0.171875s system = 22.968750s CPU (106.4%) + +RUN-1003 : finish command "place" in 65.568610s wall, 91.687500s user + 5.640625s system = 97.328125s CPU (148.4%) + +RUN-1004 : used memory is 654 MB, reserved memory is 658 MB, peak memory is 750 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.695913s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (174.1%) + +RUN-1004 : used memory is 654 MB, reserved memory is 659 MB, peak memory is 750 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6908 instances +RUN-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17653 nets +RUN-6002 WARNING: There are 1 undriven nets. +RUN-6004 WARNING: There are 21 nets with only 1 pin. +RUN-1001 : 10002 nets have 2 pins +RUN-1001 : 5782 nets have [3 - 5] pins +RUN-1001 : 1143 nets have [6 - 10] pins +RUN-1001 : 352 nets have [11 - 20] pins +RUN-1001 : 345 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.598275s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%) + +RUN-1004 : used memory is 636 MB, reserved memory is 629 MB, peak memory is 750 MB +PHY-1001 : 3388 mslices, 3369 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[20] is skipped due to 0 input or output +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 858424, over cnt = 2701(7%), over = 4497, worst = 8 +PHY-1002 : len = 877136, over cnt = 1568(4%), over = 2249, worst = 6 +PHY-1002 : len = 892488, over cnt = 746(2%), over = 1063, worst = 6 +PHY-1002 : len = 907912, over cnt = 24(0%), over = 37, worst = 6 +PHY-1002 : len = 908592, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.061463s wall, 4.078125s user + 0.031250s system = 4.109375s CPU (134.2%) + +PHY-1001 : Congestion index: top1 = 55.41, top5 = 49.60, top10 = 46.25, top15 = 44.10. +PHY-1001 : End global routing; 3.419014s wall, 4.421875s user + 0.031250s system = 4.453125s CPU (130.2%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 725, reserve = 721, peak = 750. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 998, reserve = 996, peak = 998. +PHY-1001 : End build detailed router design. 3.976029s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (99.8%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 265920, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 5.229235s wall, 5.187500s user + 0.046875s system = 5.234375s CPU (100.1%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 265976, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.432197s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%) + +PHY-1001 : Current memory(MB): used = 1034, reserve = 1033, peak = 1034. +PHY-1001 : End phase 1; 5.673768s wall, 5.625000s user + 0.046875s system = 5.671875s CPU (100.0%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 43% nets. +PHY-1001 : Routed 51% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.34276e+06, over cnt = 1866(0%), over = 1879, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1052, reserve = 1048, peak = 1052. +PHY-1001 : End initial routed; 29.301576s wall, 62.687500s user + 0.281250s system = 62.968750s CPU (214.9%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.241527s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.8%) + +PHY-1001 : Current memory(MB): used = 1057, reserve = 1054, peak = 1057. +PHY-1001 : End phase 2; 32.543169s wall, 65.921875s user + 0.281250s system = 66.203125s CPU (203.4%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.133745s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.5%) + +PHY-1022 : len = 2.34276e+06, over cnt = 1867(0%), over = 1880, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.392265s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.31113e+06, over cnt = 653(0%), over = 655, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.121127s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (202.1%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.31112e+06, over cnt = 129(0%), over = 129, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.543797s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (166.7%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.31181e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.306397s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (132.6%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.3119e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.222076s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (119.6%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 5; 0.188707s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.4%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.276743s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 2.261563s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (98.8%) + +PHY-1001 : Current memory(MB): used = 1162, reserve = 1163, peak = 1162. +PHY-1001 : End phase 3; 8.719749s wall, 10.328125s user + 0.015625s system = 10.343750s CPU (118.6%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.139261s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.0%) + +PHY-1022 : len = 2.31198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.388105s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.6%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16575(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.294443s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.1%) + +PHY-1001 : Commit to database..... +PHY-1001 : 565 feed throughs used by 440 nets +PHY-1001 : End commit to database; 3.912924s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (99.8%) + +PHY-1001 : Current memory(MB): used = 1171, reserve = 1173, peak = 1171. +PHY-1001 : End phase 4; 7.624002s wall, 7.609375s user + 0.000000s system = 7.609375s CPU (99.8%) + +PHY-1003 : Routed, final wirelength = 2.31198e+06 +PHY-1001 : Current memory(MB): used = 1173, reserve = 1174, peak = 1173. +PHY-1001 : End export database. 0.148408s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.3%) + +PHY-1001 : End detail routing; 59.083843s wall, 93.968750s user + 0.390625s system = 94.359375s CPU (159.7%) + +RUN-1003 : finish command "route" in 65.211126s wall, 101.078125s user + 0.453125s system = 101.531250s CPU (155.7%) + +RUN-1004 : used memory is 1100 MB, reserved memory is 1099 MB, peak memory is 1173 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10272 out of 19600 52.41% +#reg 9440 out of 19600 48.16% +#le 12642 + #lut only 3202 out of 12642 25.33% + #reg only 2370 out of 12642 18.75% + #lut® 7070 out of 12642 55.92% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1810 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1411 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 67 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_275.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_295.f0 3 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P16 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE + debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P110 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12642 |9245 |1027 |9472 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |534 |414 |23 |439 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |105 |89 |4 |93 |4 |0 | +| U_crc16_24b |crc16_24b |35 |35 |0 |21 |0 |0 | +| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 | +| exdev_ctl_a |exdev_ctl |783 |363 |96 |589 |0 |0 | +| u_ADconfig |AD_config |196 |132 |25 |142 |0 |0 | +| u_gen_sp |gen_sp |263 |146 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |755 |389 |96 |568 |0 |0 | +| u_ADconfig |AD_config |179 |143 |25 |128 |0 |0 | +| u_gen_sp |gen_sp |258 |158 |71 |122 |0 |0 | +| sampling_fe_a |sampling_fe |3082 |2473 |306 |2092 |25 |0 | +| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 | +| u_ad_sampling |ad_sampling |178 |118 |17 |140 |0 |0 | +| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_sort |sort |2866 |2347 |289 |1914 |25 |0 | +| rddpram_ctl |rddpram_ctl |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |1 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer |data_prebuffer |2426 |2024 |253 |1569 |22 |0 | +| channelPart |channel_part_8478 |130 |125 |3 |122 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |0 | +| ram_switch |ram_switch |1920 |1590 |197 |1175 |0 |0 | +| adc_addr_gen |adc_addr_gen |231 |204 |27 |126 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 | +| insert |insert |949 |648 |170 |655 |0 |0 | +| ram_switch_state |ram_switch_state |740 |738 |0 |394 |0 |0 | +| read_ram_i |read_ram |283 |235 |44 |196 |0 |0 | +| read_ram_addr |read_ram_addr |227 |187 |40 |156 |0 |0 | +| read_ram_data |read_ram_data |53 |46 |4 |37 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |334 |244 |36 |271 |3 |0 | +| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3369 |2673 |349 |2099 |25 |1 | +| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |182 |111 |17 |148 |0 |0 | +| u_sort |sort_rev |3150 |2545 |332 |1916 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 | +| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2693 |2207 |290 |1564 |22 |1 | +| channelPart |channel_part_8478 |233 |230 |3 |142 |0 |0 | +| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 | +| ram_switch |ram_switch |1998 |1643 |197 |1130 |0 |0 | +| adc_addr_gen |adc_addr_gen |213 |186 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |4 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |4 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 | +| insert |insert |974 |648 |170 |672 |0 |0 | +| ram_switch_state |ram_switch_state |811 |809 |0 |352 |0 |0 | +| read_ram_i |read_ram_rev |364 |251 |81 |211 |0 |0 | +| read_ram_addr |read_ram_addr_rev |297 |212 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |67 |39 |8 |49 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9940 + #2 2 3914 + #3 3 1327 + #4 4 538 + #5 5-10 1208 + #6 11-50 607 + #7 51-100 22 + #8 >500 1 + Average 2.90 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.700432s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (134.2%) + +RUN-1004 : used memory is 1102 MB, reserved memory is 1100 MB, peak memory is 1173 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74073, tnet num: 17475, tinst num: 6906, tnode num: 96668, tedge num: 124217. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.598248s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1104 MB, peak memory is 1173 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17475 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.464696s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.3%) + +RUN-1004 : used memory is 1109 MB, reserved memory is 1107 MB, peak memory is 1173 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6906 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17653, pip num: 172714 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 565 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 480236 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.634660s wall, 59.812500s user + 0.203125s system = 60.015625s CPU (622.9%) + +RUN-1004 : used memory is 1275 MB, reserved memory is 1270 MB, peak memory is 1390 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_155133.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_161301.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_161301.log new file mode 100644 index 0000000..6d6460d --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_161301.log @@ -0,0 +1,2048 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:13:01 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.428043s wall, 2.312500s user + 0.109375s system = 2.421875s CPU (99.7%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u1_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u1_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17682 instances +RUN-0007 : 7357 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20260 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13191 nets have 2 pins +RUN-1001 : 5790 nets have [3 - 5] pins +RUN-1001 : 865 nets have [6 - 10] pins +RUN-1001 : 158 nets have [11 - 20] pins +RUN-1001 : 182 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2027 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17680 instances, 7357 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.143237s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (99.8%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.937674s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (100.0%) + +PHY-3001 : Found 1234 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.1219e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17680. +PHY-3001 : Level 1 #clusters 1973. +PHY-3001 : End clustering; 0.142250s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (120.8%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28458e+06, overlap = 454.594 +PHY-3002 : Step(2): len = 1.19286e+06, overlap = 517.438 +PHY-3002 : Step(3): len = 834854, overlap = 592.562 +PHY-3002 : Step(4): len = 777443, overlap = 637.781 +PHY-3002 : Step(5): len = 600279, overlap = 721.844 +PHY-3002 : Step(6): len = 521980, overlap = 819.938 +PHY-3002 : Step(7): len = 451048, overlap = 893.281 +PHY-3002 : Step(8): len = 403911, overlap = 964.25 +PHY-3002 : Step(9): len = 368591, overlap = 1029.12 +PHY-3002 : Step(10): len = 338922, overlap = 1073.25 +PHY-3002 : Step(11): len = 304508, overlap = 1141.53 +PHY-3002 : Step(12): len = 279694, overlap = 1170.69 +PHY-3002 : Step(13): len = 252054, overlap = 1214.53 +PHY-3002 : Step(14): len = 238649, overlap = 1226.72 +PHY-3002 : Step(15): len = 215896, overlap = 1308.69 +PHY-3002 : Step(16): len = 208275, overlap = 1349.81 +PHY-3002 : Step(17): len = 186803, overlap = 1390.97 +PHY-3002 : Step(18): len = 181606, overlap = 1410.38 +PHY-3002 : Step(19): len = 161931, overlap = 1445.09 +PHY-3002 : Step(20): len = 158750, overlap = 1451.41 +PHY-3002 : Step(21): len = 144790, overlap = 1458.78 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10227e-06 +PHY-3002 : Step(22): len = 145764, overlap = 1436.72 +PHY-3002 : Step(23): len = 171419, overlap = 1355.31 +PHY-3002 : Step(24): len = 181024, overlap = 1285.84 +PHY-3002 : Step(25): len = 190053, overlap = 1252.5 +PHY-3002 : Step(26): len = 189802, overlap = 1232.38 +PHY-3002 : Step(27): len = 188169, overlap = 1167.09 +PHY-3002 : Step(28): len = 186098, overlap = 1152.94 +PHY-3002 : Step(29): len = 184554, overlap = 1153.88 +PHY-3002 : Step(30): len = 182246, overlap = 1160.28 +PHY-3002 : Step(31): len = 180553, overlap = 1150.56 +PHY-3002 : Step(32): len = 178023, overlap = 1131 +PHY-3002 : Step(33): len = 175804, overlap = 1116.19 +PHY-3002 : Step(34): len = 172887, overlap = 1111.69 +PHY-3002 : Step(35): len = 172318, overlap = 1092.16 +PHY-3002 : Step(36): len = 170745, overlap = 1082.41 +PHY-3002 : Step(37): len = 170225, overlap = 1078.19 +PHY-3002 : Step(38): len = 168406, overlap = 1092.12 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20454e-06 +PHY-3002 : Step(39): len = 173223, overlap = 1091 +PHY-3002 : Step(40): len = 183661, overlap = 1073.78 +PHY-3002 : Step(41): len = 187019, overlap = 1076.62 +PHY-3002 : Step(42): len = 191009, overlap = 1064.94 +PHY-3002 : Step(43): len = 192665, overlap = 1062.09 +PHY-3002 : Step(44): len = 195163, overlap = 1060.5 +PHY-3002 : Step(45): len = 192963, overlap = 1046.19 +PHY-3002 : Step(46): len = 193608, overlap = 1030.38 +PHY-3002 : Step(47): len = 192284, overlap = 1002.53 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.40908e-06 +PHY-3002 : Step(48): len = 200352, overlap = 983.75 +PHY-3002 : Step(49): len = 213737, overlap = 939.594 +PHY-3002 : Step(50): len = 219580, overlap = 886.688 +PHY-3002 : Step(51): len = 226210, overlap = 816.094 +PHY-3002 : Step(52): len = 229549, overlap = 804.75 +PHY-3002 : Step(53): len = 232138, overlap = 780.781 +PHY-3002 : Step(54): len = 233416, overlap = 765.125 +PHY-3002 : Step(55): len = 234157, overlap = 763 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.81817e-06 +PHY-3002 : Step(56): len = 245109, overlap = 742.219 +PHY-3002 : Step(57): len = 266212, overlap = 668.969 +PHY-3002 : Step(58): len = 277689, overlap = 618.844 +PHY-3002 : Step(59): len = 285405, overlap = 596.625 +PHY-3002 : Step(60): len = 288711, overlap = 579.406 +PHY-3002 : Step(61): len = 285269, overlap = 573.375 +PHY-3002 : Step(62): len = 282211, overlap = 567.625 +PHY-3002 : Step(63): len = 281487, overlap = 544.031 +PHY-3002 : Step(64): len = 281654, overlap = 536.062 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76363e-05 +PHY-3002 : Step(65): len = 298684, overlap = 505.062 +PHY-3002 : Step(66): len = 312625, overlap = 481.625 +PHY-3002 : Step(67): len = 320174, overlap = 451.344 +PHY-3002 : Step(68): len = 324546, overlap = 454.938 +PHY-3002 : Step(69): len = 322533, overlap = 425.188 +PHY-3002 : Step(70): len = 326215, overlap = 428.062 +PHY-3002 : Step(71): len = 325562, overlap = 429.625 +PHY-3002 : Step(72): len = 328832, overlap = 411.375 +PHY-3002 : Step(73): len = 327893, overlap = 403.625 +PHY-3002 : Step(74): len = 328559, overlap = 392.656 +PHY-3002 : Step(75): len = 328014, overlap = 378.594 +PHY-3002 : Step(76): len = 327790, overlap = 361.219 +PHY-3002 : Step(77): len = 327386, overlap = 365.656 +PHY-3002 : Step(78): len = 327424, overlap = 361.812 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.52727e-05 +PHY-3002 : Step(79): len = 347844, overlap = 345 +PHY-3002 : Step(80): len = 360317, overlap = 330.156 +PHY-3002 : Step(81): len = 359507, overlap = 338.219 +PHY-3002 : Step(82): len = 360230, overlap = 363.219 +PHY-3002 : Step(83): len = 360958, overlap = 361.75 +PHY-3002 : Step(84): len = 363179, overlap = 337.781 +PHY-3002 : Step(85): len = 362174, overlap = 335.562 +PHY-3002 : Step(86): len = 365967, overlap = 331.625 +PHY-3002 : Step(87): len = 366931, overlap = 327.406 +PHY-3002 : Step(88): len = 369206, overlap = 313.719 +PHY-3002 : Step(89): len = 365751, overlap = 298.844 +PHY-3002 : Step(90): len = 366337, overlap = 287.688 +PHY-3002 : Step(91): len = 367062, overlap = 293.812 +PHY-3002 : Step(92): len = 368680, overlap = 292.719 +PHY-3002 : Step(93): len = 366044, overlap = 303.5 +PHY-3002 : Step(94): len = 365356, overlap = 315.25 +PHY-3002 : Step(95): len = 365794, overlap = 306.25 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.05453e-05 +PHY-3002 : Step(96): len = 383373, overlap = 294.125 +PHY-3002 : Step(97): len = 396682, overlap = 289.375 +PHY-3002 : Step(98): len = 396725, overlap = 271.656 +PHY-3002 : Step(99): len = 398660, overlap = 253.812 +PHY-3002 : Step(100): len = 402517, overlap = 254.156 +PHY-3002 : Step(101): len = 405673, overlap = 241.094 +PHY-3002 : Step(102): len = 403429, overlap = 252.25 +PHY-3002 : Step(103): len = 405140, overlap = 248.125 +PHY-3002 : Step(104): len = 407766, overlap = 237.375 +PHY-3002 : Step(105): len = 409418, overlap = 249.156 +PHY-3002 : Step(106): len = 405880, overlap = 239.969 +PHY-3002 : Step(107): len = 405662, overlap = 235.875 +PHY-3002 : Step(108): len = 406048, overlap = 232.312 +PHY-3002 : Step(109): len = 406902, overlap = 237.75 +PHY-3002 : Step(110): len = 404493, overlap = 248.5 +PHY-3002 : Step(111): len = 404712, overlap = 239.375 +PHY-3002 : Step(112): len = 406242, overlap = 226.094 +PHY-3002 : Step(113): len = 407166, overlap = 224.438 +PHY-3002 : Step(114): len = 404269, overlap = 228.969 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000136152 +PHY-3002 : Step(115): len = 418935, overlap = 227.062 +PHY-3002 : Step(116): len = 427384, overlap = 206.469 +PHY-3002 : Step(117): len = 425584, overlap = 205.844 +PHY-3002 : Step(118): len = 425470, overlap = 212.75 +PHY-3002 : Step(119): len = 428820, overlap = 206.594 +PHY-3002 : Step(120): len = 432309, overlap = 196.875 +PHY-3002 : Step(121): len = 430894, overlap = 197.094 +PHY-3002 : Step(122): len = 432789, overlap = 200.562 +PHY-3002 : Step(123): len = 436136, overlap = 200.344 +PHY-3002 : Step(124): len = 439101, overlap = 196.25 +PHY-3002 : Step(125): len = 436715, overlap = 199.156 +PHY-3002 : Step(126): len = 436613, overlap = 197.156 +PHY-3002 : Step(127): len = 439831, overlap = 196.281 +PHY-3002 : Step(128): len = 443685, overlap = 196.625 +PHY-3002 : Step(129): len = 441926, overlap = 189.938 +PHY-3002 : Step(130): len = 441301, overlap = 179.031 +PHY-3002 : Step(131): len = 442397, overlap = 184.125 +PHY-3002 : Step(132): len = 443133, overlap = 199.562 +PHY-3002 : Step(133): len = 441362, overlap = 195.719 +PHY-3002 : Step(134): len = 441255, overlap = 209.875 +PHY-3002 : Step(135): len = 442109, overlap = 207.469 +PHY-3002 : Step(136): len = 442607, overlap = 207.156 +PHY-3002 : Step(137): len = 441272, overlap = 203.031 +PHY-3002 : Step(138): len = 441832, overlap = 203.344 +PHY-3002 : Step(139): len = 443179, overlap = 212.375 +PHY-3002 : Step(140): len = 444519, overlap = 214.75 +PHY-3002 : Step(141): len = 442739, overlap = 209.094 +PHY-3002 : Step(142): len = 442473, overlap = 207.844 +PHY-3002 : Step(143): len = 443263, overlap = 205.531 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000272303 +PHY-3002 : Step(144): len = 455518, overlap = 195.062 +PHY-3002 : Step(145): len = 464702, overlap = 185.5 +PHY-3002 : Step(146): len = 464857, overlap = 180.531 +PHY-3002 : Step(147): len = 465637, overlap = 183.438 +PHY-3002 : Step(148): len = 468027, overlap = 192.156 +PHY-3002 : Step(149): len = 469099, overlap = 190.906 +PHY-3002 : Step(150): len = 467659, overlap = 192.344 +PHY-3002 : Step(151): len = 467713, overlap = 188.438 +PHY-3002 : Step(152): len = 470120, overlap = 192.5 +PHY-3002 : Step(153): len = 472631, overlap = 190.406 +PHY-3002 : Step(154): len = 472240, overlap = 188.5 +PHY-3002 : Step(155): len = 472491, overlap = 190.688 +PHY-3002 : Step(156): len = 473540, overlap = 190.875 +PHY-3002 : Step(157): len = 473764, overlap = 188.156 +PHY-3002 : Step(158): len = 472836, overlap = 191.719 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000517479 +PHY-3002 : Step(159): len = 481783, overlap = 185.75 +PHY-3002 : Step(160): len = 489324, overlap = 173.531 +PHY-3002 : Step(161): len = 490952, overlap = 175.844 +PHY-3002 : Step(162): len = 491576, overlap = 179.406 +PHY-3002 : Step(163): len = 493038, overlap = 172.75 +PHY-3002 : Step(164): len = 494288, overlap = 172.031 +PHY-3002 : Step(165): len = 494102, overlap = 170.969 +PHY-3002 : Step(166): len = 494482, overlap = 171.281 +PHY-3002 : Step(167): len = 495592, overlap = 167.562 +PHY-3002 : Step(168): len = 496404, overlap = 160.312 +PHY-3002 : Step(169): len = 496139, overlap = 161.219 +PHY-3002 : Step(170): len = 496343, overlap = 161.719 +PHY-3002 : Step(171): len = 497891, overlap = 156.531 +PHY-3002 : Step(172): len = 499031, overlap = 157.719 +PHY-3002 : Step(173): len = 498589, overlap = 156.281 +PHY-3002 : Step(174): len = 498494, overlap = 157.719 +PHY-3002 : Step(175): len = 498990, overlap = 159.594 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100707 +PHY-3002 : Step(176): len = 503830, overlap = 152.062 +PHY-3002 : Step(177): len = 509893, overlap = 150.5 +PHY-3002 : Step(178): len = 511435, overlap = 152.344 +PHY-3002 : Step(179): len = 512388, overlap = 133.812 +PHY-3002 : Step(180): len = 513505, overlap = 133.719 +PHY-3002 : Step(181): len = 514467, overlap = 129.719 +PHY-3002 : Step(182): len = 515230, overlap = 135.812 +PHY-3002 : Step(183): len = 516003, overlap = 136.906 +PHY-3002 : Step(184): len = 516865, overlap = 134.562 +PHY-3002 : Step(185): len = 517779, overlap = 130.688 +PHY-3002 : Step(186): len = 518736, overlap = 132.719 +PHY-3002 : Step(187): len = 519811, overlap = 126.688 +PHY-3002 : Step(188): len = 520285, overlap = 126.156 +PHY-3002 : Step(189): len = 520609, overlap = 125.312 +PHY-3002 : Step(190): len = 521783, overlap = 127.844 +PHY-3002 : Step(191): len = 524804, overlap = 133.906 +PHY-3002 : Step(192): len = 525311, overlap = 128.094 +PHY-3002 : Step(193): len = 525522, overlap = 127.75 +PHY-3002 : Step(194): len = 525992, overlap = 130.906 +PHY-3002 : Step(195): len = 526317, overlap = 127.812 +PHY-3002 : Step(196): len = 526461, overlap = 129.562 +PHY-3002 : Step(197): len = 526651, overlap = 128.719 +PHY-3002 : Step(198): len = 526598, overlap = 125.625 +PHY-3002 : Step(199): len = 526598, overlap = 125.625 +PHY-3002 : Step(200): len = 526552, overlap = 127.5 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00175132 +PHY-3002 : Step(201): len = 530576, overlap = 126.094 +PHY-3002 : Step(202): len = 538601, overlap = 110.594 +PHY-3002 : Step(203): len = 541750, overlap = 108.5 +PHY-3002 : Step(204): len = 544652, overlap = 105.531 +PHY-3002 : Step(205): len = 547197, overlap = 106.688 +PHY-3002 : Step(206): len = 548616, overlap = 102.438 +PHY-3002 : Step(207): len = 548103, overlap = 107.719 +PHY-3002 : Step(208): len = 547931, overlap = 106.031 +PHY-3002 : Step(209): len = 548688, overlap = 104.594 +PHY-3002 : Step(210): len = 548850, overlap = 104.406 +PHY-3002 : Step(211): len = 548658, overlap = 104.156 +PHY-3002 : Step(212): len = 548451, overlap = 102.812 +PHY-3002 : Step(213): len = 548705, overlap = 102.719 +PHY-3002 : Step(214): len = 549232, overlap = 110.531 +PHY-3002 : Step(215): len = 548966, overlap = 110.062 +PHY-3002 : Step(216): len = 548965, overlap = 106.812 +PHY-3002 : Step(217): len = 549793, overlap = 107.031 +PHY-3002 : Step(218): len = 550809, overlap = 106.312 +PHY-3002 : Step(219): len = 550869, overlap = 103.344 +PHY-3002 : Step(220): len = 550943, overlap = 103.188 +PHY-3002 : Step(221): len = 551329, overlap = 103.625 +PHY-3002 : Step(222): len = 551423, overlap = 103.688 +PHY-3002 : Step(223): len = 551233, overlap = 103.312 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00283364 +PHY-3002 : Step(224): len = 553382, overlap = 104.562 +PHY-3002 : Step(225): len = 556308, overlap = 104.5 +PHY-3002 : Step(226): len = 557092, overlap = 103.656 +PHY-3002 : Step(227): len = 557701, overlap = 103.594 +PHY-3002 : Step(228): len = 559575, overlap = 101.031 +PHY-3002 : Step(229): len = 561650, overlap = 102.812 +PHY-3002 : Step(230): len = 561954, overlap = 101.875 +PHY-3002 : Step(231): len = 562121, overlap = 101.688 +PHY-3002 : Step(232): len = 562575, overlap = 103.812 +PHY-3002 : Step(233): len = 563080, overlap = 103.562 +PHY-3002 : Step(234): len = 563399, overlap = 102.906 +PHY-3002 : Step(235): len = 563656, overlap = 109.125 +PHY-3002 : Step(236): len = 564193, overlap = 114.281 +PHY-3002 : Step(237): len = 564456, overlap = 114.406 +PHY-3002 : Step(238): len = 564464, overlap = 115.469 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.014179s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (110.2%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 742288, over cnt = 1602(4%), over = 6977, worst = 39 +PHY-1001 : End global iterations; 0.652759s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (141.2%) + +PHY-1001 : Congestion index: top1 = 77.52, top5 = 59.55, top10 = 51.12, top15 = 45.77. +PHY-3001 : End congestion estimation; 0.876199s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (130.2%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.852705s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001333 +PHY-3002 : Step(239): len = 674159, overlap = 72.75 +PHY-3002 : Step(240): len = 670375, overlap = 62.5 +PHY-3002 : Step(241): len = 667742, overlap = 60.2812 +PHY-3002 : Step(242): len = 661142, overlap = 54.7812 +PHY-3002 : Step(243): len = 657871, overlap = 47.75 +PHY-3002 : Step(244): len = 652912, overlap = 41.875 +PHY-3002 : Step(245): len = 651397, overlap = 37.7812 +PHY-3002 : Step(246): len = 649252, overlap = 33.5625 +PHY-3002 : Step(247): len = 647941, overlap = 30.125 +PHY-3002 : Step(248): len = 644819, overlap = 29.8438 +PHY-3002 : Step(249): len = 642332, overlap = 26.75 +PHY-3002 : Step(250): len = 639578, overlap = 25.0938 +PHY-3002 : Step(251): len = 638076, overlap = 22.1875 +PHY-3002 : Step(252): len = 636057, overlap = 21.8438 +PHY-3002 : Step(253): len = 635525, overlap = 20.5938 +PHY-3002 : Step(254): len = 635265, overlap = 18.875 +PHY-3002 : Step(255): len = 633552, overlap = 19.6875 +PHY-3002 : Step(256): len = 632166, overlap = 20.5312 +PHY-3002 : Step(257): len = 631004, overlap = 17.7812 +PHY-3002 : Step(258): len = 629923, overlap = 15.4375 +PHY-3002 : Step(259): len = 628251, overlap = 16.25 +PHY-3002 : Step(260): len = 626553, overlap = 16.8438 +PHY-3002 : Step(261): len = 625655, overlap = 16.9688 +PHY-3002 : Step(262): len = 623391, overlap = 18.5312 +PHY-3002 : Step(263): len = 621512, overlap = 21.7188 +PHY-3002 : Step(264): len = 619921, overlap = 21.875 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.0002666 +PHY-3002 : Step(265): len = 621478, overlap = 21.1875 +PHY-3002 : Step(266): len = 624688, overlap = 21.5938 +PHY-3002 : Step(267): len = 628537, overlap = 22.4062 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000490515 +PHY-3002 : Step(268): len = 633348, overlap = 23.375 +PHY-3002 : Step(269): len = 646881, overlap = 24.5625 +PHY-3002 : Step(270): len = 667813, overlap = 23.7812 +PHY-3002 : Step(271): len = 668638, overlap = 23 +PHY-3002 : Step(272): len = 666623, overlap = 24.0938 +PHY-3002 : Step(273): len = 663010, overlap = 25.1562 +PHY-3002 : Step(274): len = 662126, overlap = 29.625 +PHY-3002 : Step(275): len = 662547, overlap = 32.375 +PHY-3002 : Step(276): len = 665980, overlap = 34.375 +PHY-3002 : Step(277): len = 669864, overlap = 33.75 +PHY-3002 : Step(278): len = 670104, overlap = 36.0625 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00098103 +PHY-3002 : Step(279): len = 673627, overlap = 33.8438 +PHY-3002 : Step(280): len = 686849, overlap = 31.5312 +PHY-3002 : Step(281): len = 702527, overlap = 31.2812 +PHY-3002 : Step(282): len = 703083, overlap = 32.5312 +PHY-3002 : Step(283): len = 702070, overlap = 32.875 +PHY-3002 : Step(284): len = 700564, overlap = 33.6875 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 56/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 793528, over cnt = 2729(7%), over = 12915, worst = 50 +PHY-1001 : End global iterations; 1.592772s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (140.3%) + +PHY-1001 : Congestion index: top1 = 89.22, top5 = 69.76, top10 = 60.63, top15 = 55.27. +PHY-3001 : End congestion estimation; 1.863207s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (135.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.883097s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.1%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000141092 +PHY-3002 : Step(285): len = 686719, overlap = 209.219 +PHY-3002 : Step(286): len = 679160, overlap = 185.719 +PHY-3002 : Step(287): len = 668627, overlap = 171.438 +PHY-3002 : Step(288): len = 659741, overlap = 163.281 +PHY-3002 : Step(289): len = 652528, overlap = 142.688 +PHY-3002 : Step(290): len = 646089, overlap = 128.125 +PHY-3002 : Step(291): len = 641384, overlap = 120.906 +PHY-3002 : Step(292): len = 637552, overlap = 120.125 +PHY-3002 : Step(293): len = 633155, overlap = 127.406 +PHY-3002 : Step(294): len = 629814, overlap = 125.781 +PHY-3002 : Step(295): len = 626141, overlap = 122.438 +PHY-3002 : Step(296): len = 622123, overlap = 118.188 +PHY-3002 : Step(297): len = 619117, overlap = 120.344 +PHY-3002 : Step(298): len = 616716, overlap = 116 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000282184 +PHY-3002 : Step(299): len = 617271, overlap = 112.062 +PHY-3002 : Step(300): len = 619942, overlap = 106.469 +PHY-3002 : Step(301): len = 620859, overlap = 105.969 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000564367 +PHY-3002 : Step(302): len = 624079, overlap = 108.156 +PHY-3002 : Step(303): len = 632262, overlap = 102.344 +PHY-3002 : Step(304): len = 637610, overlap = 93.75 +PHY-3002 : Step(305): len = 636593, overlap = 89.125 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00112873 +PHY-3002 : Step(306): len = 638768, overlap = 85.25 +PHY-3002 : Step(307): len = 642229, overlap = 85.4688 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.434897s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.2%) + +RUN-1004 : used memory is 582 MB, reserved memory is 564 MB, peak memory is 717 MB +OPT-1001 : Total overflow 432.28 peak overflow 4.09 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 671/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 745968, over cnt = 3022(8%), over = 11122, worst = 31 +PHY-1001 : End global iterations; 1.423949s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (141.6%) + +PHY-1001 : Congestion index: top1 = 72.18, top5 = 58.02, top10 = 52.03, top15 = 48.35. +PHY-1001 : End incremental global routing; 1.777809s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (133.6%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.938413s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.9%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17544 has valid locations, 338 needs to be replaced +PHY-3001 : design contains 17967 instances, 7460 luts, 9286 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6084 pins +PHY-3001 : Found 1245 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 667470 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16790/20547. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 762352, over cnt = 3092(8%), over = 11092, worst = 31 +PHY-1001 : End global iterations; 0.246472s wall, 0.312500s user + 0.046875s system = 0.359375s CPU (145.8%) + +PHY-1001 : Congestion index: top1 = 72.16, top5 = 58.35, top10 = 52.33, top15 = 48.69. +PHY-3001 : End congestion estimation; 0.500635s wall, 0.562500s user + 0.046875s system = 0.609375s CPU (121.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85721, tnet num: 20369, tinst num: 17967, tnode num: 116561, tedge num: 137434. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.445206s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.5%) + +RUN-1004 : used memory is 624 MB, reserved memory is 614 MB, peak memory is 721 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20369 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 3.351320s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (83.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(308): len = 666430, overlap = 0.25 +PHY-3002 : Step(309): len = 665906, overlap = 0.25 +PHY-3002 : Step(310): len = 665599, overlap = 0.25 +PHY-3002 : Step(311): len = 665256, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16902/20547. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 759496, over cnt = 3109(8%), over = 11184, worst = 31 +PHY-1001 : End global iterations; 0.214553s wall, 0.265625s user + 0.046875s system = 0.312500s CPU (145.7%) + +PHY-1001 : Congestion index: top1 = 72.54, top5 = 58.76, top10 = 52.69, top15 = 48.97. +PHY-3001 : End congestion estimation; 0.471923s wall, 0.515625s user + 0.062500s system = 0.578125s CPU (122.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20369 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.288397s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.7%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000468831 +PHY-3002 : Step(312): len = 665186, overlap = 87.6875 +PHY-3002 : Step(313): len = 665211, overlap = 87.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000937662 +PHY-3002 : Step(314): len = 665606, overlap = 87.9375 +PHY-3002 : Step(315): len = 666171, overlap = 88.0625 +PHY-3001 : Final: Len = 666171, Over = 88.0625 +PHY-3001 : End incremental placement; 6.283656s wall, 6.093750s user + 0.281250s system = 6.375000s CPU (101.5%) + +OPT-1001 : Total overflow 437.94 peak overflow 4.09 +OPT-1001 : End high-fanout net optimization; 9.551103s wall, 10.031250s user + 0.281250s system = 10.312500s CPU (108.0%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 709, peak = 739. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16826/20547. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 762416, over cnt = 3032(8%), over = 10049, worst = 31 +PHY-1002 : len = 820840, over cnt = 1886(5%), over = 4407, worst = 18 +PHY-1002 : len = 852848, over cnt = 842(2%), over = 1916, worst = 18 +PHY-1002 : len = 877584, over cnt = 188(0%), over = 346, worst = 10 +PHY-1002 : len = 884336, over cnt = 9(0%), over = 10, worst = 2 +PHY-1001 : End global iterations; 1.718213s wall, 2.500000s user + 0.062500s system = 2.562500s CPU (149.1%) + +PHY-1001 : Congestion index: top1 = 59.12, top5 = 51.48, top10 = 47.69, top15 = 45.21. +OPT-1001 : End congestion update; 1.976093s wall, 2.750000s user + 0.062500s system = 2.812500s CPU (142.3%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20369 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.820342s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.0%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 109 cells processed and 14400 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 33 cells processed and 3978 slack improved +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 15 cells processed and 200 slack improved +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved +OPT-1001 : End bottleneck based optimization; 3.197235s wall, 3.984375s user + 0.062500s system = 4.046875s CPU (126.6%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 739. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16881/20552. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 884632, over cnt = 94(0%), over = 128, worst = 5 +PHY-1002 : len = 884576, over cnt = 48(0%), over = 55, worst = 4 +PHY-1002 : len = 884920, over cnt = 10(0%), over = 10, worst = 1 +PHY-1002 : len = 885016, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 885072, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.713355s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.8%) + +PHY-1001 : Congestion index: top1 = 59.05, top5 = 51.24, top10 = 47.56, top15 = 45.12. +OPT-1001 : End congestion update; 0.980073s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (98.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20374 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.789025s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.0%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 23 cells processed and 4050 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.893684s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.8%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 739. +OPT-1001 : End physical optimization; 16.386057s wall, 17.718750s user + 0.375000s system = 18.093750s CPU (110.4%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7460 LUT to BLE ... +SYN-4008 : Packed 7460 LUT and 3135 SEQ to BLE. +SYN-4003 : Packing 6156 remaining SEQ's ... +SYN-4005 : Packed 3892 SEQ with LUT/SLICE +SYN-4006 : 736 single LUT's are left +SYN-4006 : 2264 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9724/13579 primitive instances ... +PHY-3001 : End packing; 1.614608s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6825 instances +RUN-1001 : 3338 mslices, 3339 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17550 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9809 nets have 2 pins +RUN-1001 : 6079 nets have [3 - 5] pins +RUN-1001 : 975 nets have [6 - 10] pins +RUN-1001 : 319 nets have [11 - 20] pins +RUN-1001 : 337 nets have [21 - 99] pins +RUN-1001 : 11 nets have 100+ pins +PHY-3001 : design contains 6823 instances, 6677 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3638 pins +PHY-3001 : Found 502 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 677871, Over = 269.75 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 7579/17550. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 837000, over cnt = 1985(5%), over = 3246, worst = 7 +PHY-1002 : len = 843760, over cnt = 1268(3%), over = 1862, worst = 7 +PHY-1002 : len = 856040, over cnt = 591(1%), over = 819, worst = 7 +PHY-1002 : len = 867712, over cnt = 111(0%), over = 154, worst = 5 +PHY-1002 : len = 870328, over cnt = 5(0%), over = 6, worst = 2 +PHY-1001 : End global iterations; 1.643042s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (144.5%) + +PHY-1001 : Congestion index: top1 = 57.93, top5 = 51.48, top10 = 47.25, top15 = 44.65. +PHY-3001 : End congestion estimation; 2.044628s wall, 2.703125s user + 0.062500s system = 2.765625s CPU (135.3%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73801, tnet num: 17372, tinst num: 6823, tnode num: 96493, tedge num: 123919. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.680944s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.5%) + +RUN-1004 : used memory is 621 MB, reserved memory is 614 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17372 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.555028s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (99.7%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.77939e-05 +PHY-3002 : Step(316): len = 666119, overlap = 268.25 +PHY-3002 : Step(317): len = 659862, overlap = 262 +PHY-3002 : Step(318): len = 655243, overlap = 262.75 +PHY-3002 : Step(319): len = 652335, overlap = 266 +PHY-3002 : Step(320): len = 649505, overlap = 273.5 +PHY-3002 : Step(321): len = 645693, overlap = 273.25 +PHY-3002 : Step(322): len = 643087, overlap = 272 +PHY-3002 : Step(323): len = 640994, overlap = 276.75 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.55878e-05 +PHY-3002 : Step(324): len = 645221, overlap = 275 +PHY-3002 : Step(325): len = 648913, overlap = 266 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000191176 +PHY-3002 : Step(326): len = 653438, overlap = 257.75 +PHY-3002 : Step(327): len = 666738, overlap = 242.5 +PHY-3002 : Step(328): len = 669436, overlap = 238.5 +PHY-3002 : Step(329): len = 670631, overlap = 233.25 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.398556s wall, 0.312500s user + 0.468750s system = 0.781250s CPU (196.0%) + +PHY-3001 : Trial Legalized: Len = 750217 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 777/17550. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 872144, over cnt = 2727(7%), over = 4605, worst = 7 +PHY-1002 : len = 888072, over cnt = 1810(5%), over = 2688, worst = 6 +PHY-1002 : len = 911296, over cnt = 647(1%), over = 906, worst = 6 +PHY-1002 : len = 922416, over cnt = 183(0%), over = 260, worst = 5 +PHY-1002 : len = 927432, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.544521s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (141.8%) + +PHY-1001 : Congestion index: top1 = 56.47, top5 = 50.58, top10 = 47.53, top15 = 45.54. +PHY-3001 : End congestion estimation; 3.023643s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (135.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17372 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.994135s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000156944 +PHY-3002 : Step(330): len = 723316, overlap = 36.25 +PHY-3002 : Step(331): len = 707463, overlap = 67.25 +PHY-3002 : Step(332): len = 694275, overlap = 96.75 +PHY-3002 : Step(333): len = 685415, overlap = 126.5 +PHY-3002 : Step(334): len = 680208, overlap = 142.25 +PHY-3002 : Step(335): len = 677666, overlap = 151 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000313888 +PHY-3002 : Step(336): len = 682823, overlap = 146.75 +PHY-3002 : Step(337): len = 688992, overlap = 145.5 +PHY-3002 : Step(338): len = 692515, overlap = 146.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000627776 +PHY-3002 : Step(339): len = 695694, overlap = 146 +PHY-3002 : Step(340): len = 706310, overlap = 138.75 +PHY-3002 : Step(341): len = 714736, overlap = 138.75 +PHY-3002 : Step(342): len = 712979, overlap = 137 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.036169s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (129.6%) + +PHY-3001 : Legalized: Len = 742603, Over = 0 +PHY-3001 : Spreading special nets. 487 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.105174s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (89.1%) + +PHY-3001 : 710 instances has been re-located, deltaX = 239, deltaY = 397, maxDist = 3. +PHY-3001 : Final: Len = 754583, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73801, tnet num: 17372, tinst num: 6826, tnode num: 96493, tedge num: 123919. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.837709s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.3%) + +RUN-1004 : used memory is 654 MB, reserved memory is 653 MB, peak memory is 739 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 3318/17550. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 887296, over cnt = 2542(7%), over = 4114, worst = 7 +PHY-1002 : len = 902032, over cnt = 1438(4%), over = 2025, worst = 7 +PHY-1002 : len = 917016, over cnt = 650(1%), over = 888, worst = 7 +PHY-1002 : len = 925904, over cnt = 185(0%), over = 252, worst = 4 +PHY-1002 : len = 930136, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.148734s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (157.8%) + +PHY-1001 : Congestion index: top1 = 54.59, top5 = 48.87, top10 = 46.13, top15 = 44.36. +PHY-1001 : End incremental global routing; 2.563988s wall, 3.781250s user + 0.015625s system = 3.796875s CPU (148.1%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17372 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. +TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.886034s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.5%) + +OPT-1001 : 4 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6734 has valid locations, 20 needs to be replaced +PHY-3001 : design contains 6842 instances, 6693 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3708 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 756999 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16068/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 932752, over cnt = 64(0%), over = 73, worst = 4 +PHY-1002 : len = 932976, over cnt = 31(0%), over = 31, worst = 1 +PHY-1002 : len = 933184, over cnt = 11(0%), over = 11, worst = 1 +PHY-1002 : len = 933312, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 933360, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.788389s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (105.0%) + +PHY-1001 : Congestion index: top1 = 54.68, top5 = 48.97, top10 = 46.27, top15 = 44.48. +PHY-3001 : End congestion estimation; 1.117666s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (103.5%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73967, tnet num: 17397, tinst num: 6842, tnode num: 96707, tedge num: 124138. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.833546s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (99.7%) + +RUN-1004 : used memory is 695 MB, reserved memory is 692 MB, peak memory is 739 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-6513 Similar messages will be suppressed. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.717802s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(343): len = 756474, overlap = 0 +PHY-3002 : Step(344): len = 756302, overlap = 0 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16058/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 932432, over cnt = 61(0%), over = 69, worst = 2 +PHY-1002 : len = 932576, over cnt = 20(0%), over = 22, worst = 2 +PHY-1002 : len = 932832, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 932864, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.590593s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (108.5%) + +PHY-1001 : Congestion index: top1 = 54.66, top5 = 48.97, top10 = 46.27, top15 = 44.46. +PHY-3001 : End congestion estimation; 0.904445s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (105.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.860345s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000425114 +PHY-3002 : Step(345): len = 756206, overlap = 0.75 +PHY-3002 : Step(346): len = 756209, overlap = 0.25 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005685s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 756266, Over = 0 +PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059261s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.1%) + +PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2. +PHY-3001 : Final: Len = 756294, Over = 0 +PHY-3001 : End incremental placement; 6.114725s wall, 6.140625s user + 0.125000s system = 6.265625s CPU (102.5%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 10.054941s wall, 11.375000s user + 0.171875s system = 11.546875s CPU (114.8%) + +OPT-1001 : Current memory(MB): used = 747, reserve = 737, peak = 750. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16039/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 932536, over cnt = 54(0%), over = 66, worst = 4 +PHY-1002 : len = 932744, over cnt = 32(0%), over = 33, worst = 2 +PHY-1002 : len = 933024, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 933064, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.592563s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.5%) + +PHY-1001 : Congestion index: top1 = 54.66, top5 = 48.95, top10 = 46.21, top15 = 44.41. +OPT-1001 : End congestion update; 0.909070s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (103.1%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.722421s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%) + +OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6754 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6842 instances, 6693 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3708 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 760402, Over = 0 +PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.068435s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (114.2%) + +PHY-3001 : 30 instances has been re-located, deltaX = 29, deltaY = 21, maxDist = 5. +PHY-3001 : Final: Len = 760830, Over = 0 +PHY-3001 : End incremental legalization; 0.394063s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.1%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 51 cells processed and 16112 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6754 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6842 instances, 6693 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3708 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 762374, Over = 0 +PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.066560s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.9%) + +PHY-3001 : 29 instances has been re-located, deltaX = 14, deltaY = 25, maxDist = 2. +PHY-3001 : Final: Len = 762954, Over = 0 +PHY-3001 : End incremental legalization; 0.422049s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.0%) + +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 27 cells processed and 6619 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6754 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6842 instances, 6693 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3708 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 763320, Over = 0 +PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061902s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%) + +PHY-3001 : 9 instances has been re-located, deltaX = 7, deltaY = 5, maxDist = 2. +PHY-3001 : Final: Len = 763646, Over = 0 +PHY-3001 : End incremental legalization; 0.389558s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.3%) + +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 14 cells processed and 1302 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6763 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6851 instances, 6702 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins +PHY-3001 : Found 512 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 764804, Over = 0 +PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060695s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.0%) + +PHY-3001 : 17 instances has been re-located, deltaX = 16, deltaY = 8, maxDist = 4. +PHY-3001 : Final: Len = 765296, Over = 0 +PHY-3001 : End incremental legalization; 0.384337s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (113.8%) + +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 8 cells processed and 1584 slack improved +OPT-1001 : End bottleneck based optimization; 3.829803s wall, 3.890625s user + 0.015625s system = 3.906250s CPU (102.0%) + +OPT-1001 : Current memory(MB): used = 748, reserve = 739, peak = 751. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 15600/17579. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 941864, over cnt = 193(0%), over = 244, worst = 6 +PHY-1002 : len = 942032, over cnt = 108(0%), over = 119, worst = 5 +PHY-1002 : len = 942552, over cnt = 64(0%), over = 66, worst = 2 +PHY-1002 : len = 943720, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 943720, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.860948s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.6%) + +PHY-1001 : Congestion index: top1 = 55.13, top5 = 49.16, top10 = 46.35, top15 = 44.55. +OPT-1001 : End congestion update; 1.178935s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.7%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17401 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.729723s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.6%) + +OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6763 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6851 instances, 6702 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins +PHY-3001 : Found 512 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 765616, Over = 0 +PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062208s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%) + +PHY-3001 : 11 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 3. +PHY-3001 : Final: Len = 766012, Over = 0 +PHY-3001 : End incremental legalization; 0.378346s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.1%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 15 cells processed and 2100 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.418556s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (101.4%) + +OPT-1001 : Current memory(MB): used = 749, reserve = 739, peak = 751. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17401 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.723464s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (97.2%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16018/17579. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 944296, over cnt = 49(0%), over = 55, worst = 2 +PHY-1002 : len = 944256, over cnt = 25(0%), over = 29, worst = 2 +PHY-1002 : len = 944488, over cnt = 7(0%), over = 7, worst = 1 +PHY-1002 : len = 944568, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 944584, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.789287s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.0%) + +PHY-1001 : Congestion index: top1 = 55.15, top5 = 49.20, top10 = 46.40, top15 = 44.62. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17401 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.724433s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.2%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.793103 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 221ps with logic level 1 +OPT-1001 : End physical optimization; 20.947409s wall, 22.312500s user + 0.218750s system = 22.531250s CPU (107.6%) + +RUN-1003 : finish command "place" in 69.691795s wall, 102.281250s user + 6.281250s system = 108.562500s CPU (155.8%) + +RUN-1004 : used memory is 695 MB, reserved memory is 689 MB, peak memory is 751 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.691093s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (174.6%) + +RUN-1004 : used memory is 695 MB, reserved memory is 690 MB, peak memory is 751 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6853 instances +RUN-1001 : 3356 mslices, 3346 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17579 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9799 nets have 2 pins +RUN-1001 : 6098 nets have [3 - 5] pins +RUN-1001 : 982 nets have [6 - 10] pins +RUN-1001 : 325 nets have [11 - 20] pins +RUN-1001 : 347 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74040, tnet num: 17401, tinst num: 6851, tnode num: 96811, tedge num: 124238. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.631292s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.6%) + +RUN-1004 : used memory is 673 MB, reserved memory is 669 MB, peak memory is 751 MB +PHY-1001 : 3356 mslices, 3346 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17401 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 876832, over cnt = 2758(7%), over = 4538, worst = 8 +PHY-1002 : len = 892976, over cnt = 1757(4%), over = 2607, worst = 8 +PHY-1002 : len = 919360, over cnt = 453(1%), over = 639, worst = 6 +PHY-1002 : len = 929240, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 929464, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.227789s wall, 4.250000s user + 0.000000s system = 4.250000s CPU (131.7%) + +PHY-1001 : Congestion index: top1 = 54.74, top5 = 49.10, top10 = 46.12, top15 = 44.27. +PHY-1001 : End global routing; 3.559292s wall, 4.578125s user + 0.015625s system = 4.593750s CPU (129.1%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 724, reserve = 720, peak = 751. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 996, reserve = 991, peak = 997. +PHY-1001 : End build detailed router design. 3.971205s wall, 3.953125s user + 0.031250s system = 3.984375s CPU (100.3%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 276896, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 5.458346s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (99.6%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 276952, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.467215s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.3%) + +PHY-1001 : Current memory(MB): used = 1033, reserve = 1028, peak = 1033. +PHY-1001 : End phase 1; 5.937938s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (99.7%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 44% nets. +PHY-1001 : Routed 52% nets. +PHY-1001 : Routed 61% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.41394e+06, over cnt = 1723(0%), over = 1727, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1049, reserve = 1045, peak = 1049. +PHY-1001 : End initial routed; 31.831994s wall, 68.234375s user + 0.328125s system = 68.562500s CPU (215.4%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16502(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.286290s wall, 3.250000s user + 0.015625s system = 3.265625s CPU (99.4%) + +PHY-1001 : Current memory(MB): used = 1061, reserve = 1056, peak = 1061. +PHY-1001 : End phase 2; 35.118355s wall, 71.484375s user + 0.343750s system = 71.828125s CPU (204.5%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.138635s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%) + +PHY-1022 : len = 2.41394e+06, over cnt = 1724(0%), over = 1728, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.433579s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.9%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.3852e+06, over cnt = 683(0%), over = 684, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.028758s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (208.1%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.3823e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.597396s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (146.5%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.3831e+06, over cnt = 48(0%), over = 48, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.328423s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (123.7%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.3833e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.268995s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.7%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.38348e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 5; 0.196048s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.6%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16502(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.361385s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (99.9%) + +PHY-1001 : Commit to database..... +PHY-1001 : 542 feed throughs used by 413 nets +PHY-1001 : End commit to database; 2.250525s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1164, reserve = 1162, peak = 1164. +PHY-1001 : End phase 3; 8.869276s wall, 10.281250s user + 0.031250s system = 10.312500s CPU (116.3%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.134831s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (92.7%) + +PHY-1022 : len = 2.38348e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.384117s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (93.6%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16502(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.658 | -0.658 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.524329s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.8%) + +PHY-1001 : Commit to database..... +PHY-1001 : 542 feed throughs used by 413 nets +PHY-1001 : End commit to database; 2.391862s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (99.3%) + +PHY-1001 : Current memory(MB): used = 1172, reserve = 1171, peak = 1172. +PHY-1001 : End phase 4; 6.327149s wall, 6.265625s user + 0.015625s system = 6.281250s CPU (99.3%) + +PHY-1003 : Routed, final wirelength = 2.38348e+06 +PHY-1001 : Current memory(MB): used = 1175, reserve = 1174, peak = 1175. +PHY-1001 : End export database. 0.066260s wall, 0.046875s user + 0.015625s system = 0.062500s CPU (94.3%) + +PHY-1001 : End detail routing; 60.700027s wall, 98.375000s user + 0.437500s system = 98.812500s CPU (162.8%) + +RUN-1003 : finish command "route" in 66.975346s wall, 105.656250s user + 0.453125s system = 106.109375s CPU (158.4%) + +RUN-1004 : used memory is 1100 MB, reserved memory is 1100 MB, peak memory is 1175 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10244 out of 19600 52.27% +#reg 9440 out of 19600 48.16% +#le 12441 + #lut only 3001 out of 12441 24.12% + #reg only 2197 out of 12441 17.66% + #lut® 7243 out of 12441 58.22% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1816 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1429 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1350 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1003 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138 +#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69 +#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 29 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_264.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/u_ADconfig/en_adc_cfg_d1_reg_syn_5.f1 2 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P17 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG + debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12441 |9217 |1027 |9474 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |541 |460 |23 |445 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |78 |4 |91 |4 |0 | +| U_crc16_24b |crc16_24b |42 |42 |0 |26 |0 |0 | +| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 | +| exdev_ctl_a |exdev_ctl |776 |361 |96 |568 |0 |0 | +| u_ADconfig |AD_config |195 |124 |25 |145 |0 |0 | +| u_gen_sp |gen_sp |277 |169 |71 |119 |0 |0 | +| exdev_ctl_b |exdev_ctl |770 |400 |96 |575 |0 |0 | +| u_ADconfig |AD_config |179 |119 |25 |128 |0 |0 | +| u_gen_sp |gen_sp |266 |153 |71 |122 |0 |0 | +| sampling_fe_a |sampling_fe |2959 |2353 |306 |2081 |25 |0 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |187 |128 |17 |146 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort |2738 |2208 |289 |1901 |25 |0 | +| rddpram_ctl |rddpram_ctl |2 |1 |0 |2 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_rdsoft_n |cdc_sync |6 |4 |0 |6 |0 |0 | +| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |2330 |1945 |253 |1557 |22 |0 | +| channelPart |channel_part_8478 |160 |155 |3 |133 |0 |0 | +| fifo_adc |fifo_adc |59 |50 |9 |43 |0 |0 | +| ram_switch |ram_switch |1805 |1487 |197 |1159 |0 |0 | +| adc_addr_gen |adc_addr_gen |233 |206 |27 |126 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| insert |insert |960 |670 |170 |655 |0 |0 | +| ram_switch_state |ram_switch_state |612 |611 |0 |378 |0 |0 | +| read_ram_i |read_ram |279 |228 |44 |197 |0 |0 | +| read_ram_addr |read_ram_addr |224 |184 |40 |156 |0 |0 | +| read_ram_data |read_ram_data |50 |40 |4 |36 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |306 |179 |36 |274 |3 |0 | +| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3308 |2703 |349 |2106 |25 |1 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_ad_sampling |ad_sampling |184 |118 |17 |145 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort_rev |3092 |2569 |332 |1929 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2635 |2199 |290 |1571 |22 |1 | +| channelPart |channel_part_8478 |262 |252 |3 |145 |0 |0 | +| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 | +| ram_switch |ram_switch |1918 |1613 |197 |1148 |0 |0 | +| adc_addr_gen |adc_addr_gen |228 |200 |27 |111 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |7 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |17 |14 |3 |6 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 | +| insert |insert |962 |685 |170 |660 |0 |0 | +| ram_switch_state |ram_switch_state |728 |728 |0 |377 |0 |0 | +| read_ram_i |read_ram_rev |363 |254 |81 |205 |0 |0 | +| read_ram_addr |read_ram_addr_rev |294 |210 |73 |155 |0 |0 | +| read_ram_data |read_ram_data_rev |69 |44 |8 |50 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9737 + #2 2 4021 + #3 3 1438 + #4 4 636 + #5 5-10 1041 + #6 11-50 585 + #7 51-100 25 + #8 >500 1 + Average 2.91 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.078487s wall, 3.531250s user + 0.046875s system = 3.578125s CPU (172.2%) + +RUN-1004 : used memory is 1102 MB, reserved memory is 1101 MB, peak memory is 1175 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74040, tnet num: 17401, tinst num: 6851, tnode num: 96811, tedge num: 124238. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.659009s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.8%) + +RUN-1004 : used memory is 1105 MB, reserved memory is 1104 MB, peak memory is 1175 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17401 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.541495s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (98.3%) + +RUN-1004 : used memory is 1108 MB, reserved memory is 1107 MB, peak memory is 1175 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6851 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17579, pip num: 174604 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 542 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3253 valid insts, and 483002 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.703016s wall, 59.703125s user + 0.156250s system = 59.859375s CPU (616.9%) + +RUN-1004 : used memory is 1270 MB, reserved memory is 1266 MB, peak memory is 1385 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_161301.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_163057.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_163057.log new file mode 100644 index 0000000..f913956 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_163057.log @@ -0,0 +1,2161 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:30:57 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.124478s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (100.0%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17682 instances +RUN-0007 : 7357 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20260 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13191 nets have 2 pins +RUN-1001 : 5790 nets have [3 - 5] pins +RUN-1001 : 865 nets have [6 - 10] pins +RUN-1001 : 158 nets have [11 - 20] pins +RUN-1001 : 182 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2027 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17680 instances, 7357 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.174824s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.7%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.956917s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (99.8%) + +PHY-3001 : Found 1234 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.1219e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17680. +PHY-3001 : Level 1 #clusters 1973. +PHY-3001 : End clustering; 0.127923s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (109.9%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28458e+06, overlap = 454.594 +PHY-3002 : Step(2): len = 1.19286e+06, overlap = 517.438 +PHY-3002 : Step(3): len = 834854, overlap = 592.562 +PHY-3002 : Step(4): len = 777443, overlap = 637.781 +PHY-3002 : Step(5): len = 600279, overlap = 721.844 +PHY-3002 : Step(6): len = 521980, overlap = 819.938 +PHY-3002 : Step(7): len = 451048, overlap = 893.281 +PHY-3002 : Step(8): len = 403911, overlap = 964.25 +PHY-3002 : Step(9): len = 368591, overlap = 1029.12 +PHY-3002 : Step(10): len = 338922, overlap = 1073.25 +PHY-3002 : Step(11): len = 304508, overlap = 1141.53 +PHY-3002 : Step(12): len = 279694, overlap = 1170.69 +PHY-3002 : Step(13): len = 252054, overlap = 1214.53 +PHY-3002 : Step(14): len = 238649, overlap = 1226.72 +PHY-3002 : Step(15): len = 215896, overlap = 1308.69 +PHY-3002 : Step(16): len = 208275, overlap = 1349.81 +PHY-3002 : Step(17): len = 186803, overlap = 1390.97 +PHY-3002 : Step(18): len = 181606, overlap = 1410.38 +PHY-3002 : Step(19): len = 161931, overlap = 1445.09 +PHY-3002 : Step(20): len = 158750, overlap = 1451.41 +PHY-3002 : Step(21): len = 144790, overlap = 1458.78 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10227e-06 +PHY-3002 : Step(22): len = 145764, overlap = 1436.72 +PHY-3002 : Step(23): len = 171419, overlap = 1355.31 +PHY-3002 : Step(24): len = 181024, overlap = 1285.84 +PHY-3002 : Step(25): len = 190053, overlap = 1252.5 +PHY-3002 : Step(26): len = 189802, overlap = 1232.38 +PHY-3002 : Step(27): len = 188169, overlap = 1167.09 +PHY-3002 : Step(28): len = 186098, overlap = 1152.94 +PHY-3002 : Step(29): len = 184554, overlap = 1153.88 +PHY-3002 : Step(30): len = 182246, overlap = 1160.28 +PHY-3002 : Step(31): len = 180553, overlap = 1150.56 +PHY-3002 : Step(32): len = 178023, overlap = 1131 +PHY-3002 : Step(33): len = 175804, overlap = 1116.19 +PHY-3002 : Step(34): len = 172887, overlap = 1111.69 +PHY-3002 : Step(35): len = 172318, overlap = 1092.16 +PHY-3002 : Step(36): len = 170745, overlap = 1082.41 +PHY-3002 : Step(37): len = 170225, overlap = 1078.19 +PHY-3002 : Step(38): len = 168406, overlap = 1092.12 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20454e-06 +PHY-3002 : Step(39): len = 173223, overlap = 1091 +PHY-3002 : Step(40): len = 183661, overlap = 1073.78 +PHY-3002 : Step(41): len = 187019, overlap = 1076.62 +PHY-3002 : Step(42): len = 191009, overlap = 1064.94 +PHY-3002 : Step(43): len = 192665, overlap = 1062.09 +PHY-3002 : Step(44): len = 195163, overlap = 1060.5 +PHY-3002 : Step(45): len = 192963, overlap = 1046.19 +PHY-3002 : Step(46): len = 193608, overlap = 1030.38 +PHY-3002 : Step(47): len = 192284, overlap = 1002.53 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.40908e-06 +PHY-3002 : Step(48): len = 200352, overlap = 983.75 +PHY-3002 : Step(49): len = 213737, overlap = 939.594 +PHY-3002 : Step(50): len = 219580, overlap = 886.688 +PHY-3002 : Step(51): len = 226210, overlap = 816.094 +PHY-3002 : Step(52): len = 229549, overlap = 804.75 +PHY-3002 : Step(53): len = 232138, overlap = 780.781 +PHY-3002 : Step(54): len = 233416, overlap = 765.125 +PHY-3002 : Step(55): len = 234157, overlap = 763 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.81817e-06 +PHY-3002 : Step(56): len = 245109, overlap = 742.219 +PHY-3002 : Step(57): len = 266212, overlap = 668.969 +PHY-3002 : Step(58): len = 277689, overlap = 618.844 +PHY-3002 : Step(59): len = 285405, overlap = 596.625 +PHY-3002 : Step(60): len = 288711, overlap = 579.406 +PHY-3002 : Step(61): len = 285269, overlap = 573.375 +PHY-3002 : Step(62): len = 282211, overlap = 567.625 +PHY-3002 : Step(63): len = 281487, overlap = 544.031 +PHY-3002 : Step(64): len = 281654, overlap = 536.062 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76363e-05 +PHY-3002 : Step(65): len = 298684, overlap = 505.062 +PHY-3002 : Step(66): len = 312625, overlap = 481.625 +PHY-3002 : Step(67): len = 320174, overlap = 451.344 +PHY-3002 : Step(68): len = 324546, overlap = 454.938 +PHY-3002 : Step(69): len = 322533, overlap = 425.188 +PHY-3002 : Step(70): len = 326215, overlap = 428.062 +PHY-3002 : Step(71): len = 325562, overlap = 429.625 +PHY-3002 : Step(72): len = 328832, overlap = 411.375 +PHY-3002 : Step(73): len = 327893, overlap = 403.625 +PHY-3002 : Step(74): len = 328559, overlap = 392.656 +PHY-3002 : Step(75): len = 328014, overlap = 378.594 +PHY-3002 : Step(76): len = 327790, overlap = 361.219 +PHY-3002 : Step(77): len = 327386, overlap = 365.656 +PHY-3002 : Step(78): len = 327424, overlap = 361.812 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.52727e-05 +PHY-3002 : Step(79): len = 347844, overlap = 345 +PHY-3002 : Step(80): len = 360317, overlap = 330.156 +PHY-3002 : Step(81): len = 359507, overlap = 338.219 +PHY-3002 : Step(82): len = 360230, overlap = 363.219 +PHY-3002 : Step(83): len = 360958, overlap = 361.75 +PHY-3002 : Step(84): len = 363179, overlap = 337.781 +PHY-3002 : Step(85): len = 362174, overlap = 335.562 +PHY-3002 : Step(86): len = 365967, overlap = 331.625 +PHY-3002 : Step(87): len = 366931, overlap = 327.406 +PHY-3002 : Step(88): len = 369206, overlap = 313.719 +PHY-3002 : Step(89): len = 365751, overlap = 298.844 +PHY-3002 : Step(90): len = 366337, overlap = 287.688 +PHY-3002 : Step(91): len = 367062, overlap = 293.812 +PHY-3002 : Step(92): len = 368680, overlap = 292.719 +PHY-3002 : Step(93): len = 366044, overlap = 303.5 +PHY-3002 : Step(94): len = 365356, overlap = 315.25 +PHY-3002 : Step(95): len = 365794, overlap = 306.25 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.05453e-05 +PHY-3002 : Step(96): len = 383373, overlap = 294.125 +PHY-3002 : Step(97): len = 396682, overlap = 289.375 +PHY-3002 : Step(98): len = 396725, overlap = 271.656 +PHY-3002 : Step(99): len = 398660, overlap = 253.812 +PHY-3002 : Step(100): len = 402517, overlap = 254.156 +PHY-3002 : Step(101): len = 405673, overlap = 241.094 +PHY-3002 : Step(102): len = 403429, overlap = 252.25 +PHY-3002 : Step(103): len = 405140, overlap = 248.125 +PHY-3002 : Step(104): len = 407766, overlap = 237.375 +PHY-3002 : Step(105): len = 409418, overlap = 249.156 +PHY-3002 : Step(106): len = 405880, overlap = 239.969 +PHY-3002 : Step(107): len = 405662, overlap = 235.875 +PHY-3002 : Step(108): len = 406048, overlap = 232.312 +PHY-3002 : Step(109): len = 406902, overlap = 237.75 +PHY-3002 : Step(110): len = 404493, overlap = 248.5 +PHY-3002 : Step(111): len = 404712, overlap = 239.375 +PHY-3002 : Step(112): len = 406242, overlap = 226.094 +PHY-3002 : Step(113): len = 407166, overlap = 224.438 +PHY-3002 : Step(114): len = 404269, overlap = 228.969 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000136152 +PHY-3002 : Step(115): len = 418935, overlap = 227.062 +PHY-3002 : Step(116): len = 427384, overlap = 206.469 +PHY-3002 : Step(117): len = 425584, overlap = 205.844 +PHY-3002 : Step(118): len = 425470, overlap = 212.75 +PHY-3002 : Step(119): len = 428820, overlap = 206.594 +PHY-3002 : Step(120): len = 432309, overlap = 196.875 +PHY-3002 : Step(121): len = 430894, overlap = 197.094 +PHY-3002 : Step(122): len = 432789, overlap = 200.562 +PHY-3002 : Step(123): len = 436136, overlap = 200.344 +PHY-3002 : Step(124): len = 439101, overlap = 196.25 +PHY-3002 : Step(125): len = 436715, overlap = 199.156 +PHY-3002 : Step(126): len = 436613, overlap = 197.156 +PHY-3002 : Step(127): len = 439831, overlap = 196.281 +PHY-3002 : Step(128): len = 443685, overlap = 196.625 +PHY-3002 : Step(129): len = 441926, overlap = 189.938 +PHY-3002 : Step(130): len = 441301, overlap = 179.031 +PHY-3002 : Step(131): len = 442397, overlap = 184.125 +PHY-3002 : Step(132): len = 443133, overlap = 199.562 +PHY-3002 : Step(133): len = 441362, overlap = 195.719 +PHY-3002 : Step(134): len = 441255, overlap = 209.875 +PHY-3002 : Step(135): len = 442109, overlap = 207.469 +PHY-3002 : Step(136): len = 442607, overlap = 207.156 +PHY-3002 : Step(137): len = 441272, overlap = 203.031 +PHY-3002 : Step(138): len = 441832, overlap = 203.344 +PHY-3002 : Step(139): len = 443179, overlap = 212.375 +PHY-3002 : Step(140): len = 444519, overlap = 214.75 +PHY-3002 : Step(141): len = 442739, overlap = 209.094 +PHY-3002 : Step(142): len = 442473, overlap = 207.844 +PHY-3002 : Step(143): len = 443263, overlap = 205.531 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000272303 +PHY-3002 : Step(144): len = 455518, overlap = 195.062 +PHY-3002 : Step(145): len = 464702, overlap = 185.5 +PHY-3002 : Step(146): len = 464857, overlap = 180.531 +PHY-3002 : Step(147): len = 465637, overlap = 183.438 +PHY-3002 : Step(148): len = 468027, overlap = 192.156 +PHY-3002 : Step(149): len = 469099, overlap = 190.906 +PHY-3002 : Step(150): len = 467659, overlap = 192.344 +PHY-3002 : Step(151): len = 467713, overlap = 188.438 +PHY-3002 : Step(152): len = 470120, overlap = 192.5 +PHY-3002 : Step(153): len = 472631, overlap = 190.406 +PHY-3002 : Step(154): len = 472240, overlap = 188.5 +PHY-3002 : Step(155): len = 472491, overlap = 190.688 +PHY-3002 : Step(156): len = 473540, overlap = 190.875 +PHY-3002 : Step(157): len = 473764, overlap = 188.156 +PHY-3002 : Step(158): len = 472836, overlap = 191.719 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000517479 +PHY-3002 : Step(159): len = 481783, overlap = 185.75 +PHY-3002 : Step(160): len = 489324, overlap = 173.531 +PHY-3002 : Step(161): len = 490952, overlap = 175.844 +PHY-3002 : Step(162): len = 491576, overlap = 179.406 +PHY-3002 : Step(163): len = 493038, overlap = 172.75 +PHY-3002 : Step(164): len = 494288, overlap = 172.031 +PHY-3002 : Step(165): len = 494102, overlap = 170.969 +PHY-3002 : Step(166): len = 494482, overlap = 171.281 +PHY-3002 : Step(167): len = 495592, overlap = 167.562 +PHY-3002 : Step(168): len = 496404, overlap = 160.312 +PHY-3002 : Step(169): len = 496139, overlap = 161.219 +PHY-3002 : Step(170): len = 496343, overlap = 161.719 +PHY-3002 : Step(171): len = 497891, overlap = 156.531 +PHY-3002 : Step(172): len = 499031, overlap = 157.719 +PHY-3002 : Step(173): len = 498589, overlap = 156.281 +PHY-3002 : Step(174): len = 498494, overlap = 157.719 +PHY-3002 : Step(175): len = 498990, overlap = 159.594 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100707 +PHY-3002 : Step(176): len = 503830, overlap = 152.062 +PHY-3002 : Step(177): len = 509893, overlap = 150.5 +PHY-3002 : Step(178): len = 511435, overlap = 152.344 +PHY-3002 : Step(179): len = 512388, overlap = 133.812 +PHY-3002 : Step(180): len = 513505, overlap = 133.719 +PHY-3002 : Step(181): len = 514467, overlap = 129.719 +PHY-3002 : Step(182): len = 515230, overlap = 135.812 +PHY-3002 : Step(183): len = 516003, overlap = 136.906 +PHY-3002 : Step(184): len = 516865, overlap = 134.562 +PHY-3002 : Step(185): len = 517779, overlap = 130.688 +PHY-3002 : Step(186): len = 518736, overlap = 132.719 +PHY-3002 : Step(187): len = 519811, overlap = 126.688 +PHY-3002 : Step(188): len = 520285, overlap = 126.156 +PHY-3002 : Step(189): len = 520609, overlap = 125.312 +PHY-3002 : Step(190): len = 521783, overlap = 127.844 +PHY-3002 : Step(191): len = 524804, overlap = 133.906 +PHY-3002 : Step(192): len = 525311, overlap = 128.094 +PHY-3002 : Step(193): len = 525522, overlap = 127.75 +PHY-3002 : Step(194): len = 525992, overlap = 130.906 +PHY-3002 : Step(195): len = 526317, overlap = 127.812 +PHY-3002 : Step(196): len = 526461, overlap = 129.562 +PHY-3002 : Step(197): len = 526651, overlap = 128.719 +PHY-3002 : Step(198): len = 526598, overlap = 125.625 +PHY-3002 : Step(199): len = 526598, overlap = 125.625 +PHY-3002 : Step(200): len = 526552, overlap = 127.5 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00175132 +PHY-3002 : Step(201): len = 530576, overlap = 126.094 +PHY-3002 : Step(202): len = 538601, overlap = 110.594 +PHY-3002 : Step(203): len = 541750, overlap = 108.5 +PHY-3002 : Step(204): len = 544652, overlap = 105.531 +PHY-3002 : Step(205): len = 547197, overlap = 106.688 +PHY-3002 : Step(206): len = 548616, overlap = 102.438 +PHY-3002 : Step(207): len = 548103, overlap = 107.719 +PHY-3002 : Step(208): len = 547931, overlap = 106.031 +PHY-3002 : Step(209): len = 548688, overlap = 104.594 +PHY-3002 : Step(210): len = 548850, overlap = 104.406 +PHY-3002 : Step(211): len = 548658, overlap = 104.156 +PHY-3002 : Step(212): len = 548451, overlap = 102.812 +PHY-3002 : Step(213): len = 548705, overlap = 102.719 +PHY-3002 : Step(214): len = 549232, overlap = 110.531 +PHY-3002 : Step(215): len = 548966, overlap = 110.062 +PHY-3002 : Step(216): len = 548965, overlap = 106.812 +PHY-3002 : Step(217): len = 549793, overlap = 107.031 +PHY-3002 : Step(218): len = 550809, overlap = 106.312 +PHY-3002 : Step(219): len = 550869, overlap = 103.344 +PHY-3002 : Step(220): len = 550943, overlap = 103.188 +PHY-3002 : Step(221): len = 551329, overlap = 103.625 +PHY-3002 : Step(222): len = 551423, overlap = 103.688 +PHY-3002 : Step(223): len = 551233, overlap = 103.312 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00283364 +PHY-3002 : Step(224): len = 553382, overlap = 104.562 +PHY-3002 : Step(225): len = 556308, overlap = 104.5 +PHY-3002 : Step(226): len = 557092, overlap = 103.656 +PHY-3002 : Step(227): len = 557701, overlap = 103.594 +PHY-3002 : Step(228): len = 559575, overlap = 101.031 +PHY-3002 : Step(229): len = 561650, overlap = 102.812 +PHY-3002 : Step(230): len = 561954, overlap = 101.875 +PHY-3002 : Step(231): len = 562121, overlap = 101.688 +PHY-3002 : Step(232): len = 562575, overlap = 103.812 +PHY-3002 : Step(233): len = 563080, overlap = 103.562 +PHY-3002 : Step(234): len = 563399, overlap = 102.906 +PHY-3002 : Step(235): len = 563656, overlap = 109.125 +PHY-3002 : Step(236): len = 564193, overlap = 114.281 +PHY-3002 : Step(237): len = 564456, overlap = 114.406 +PHY-3002 : Step(238): len = 564464, overlap = 115.469 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.014442s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 742288, over cnt = 1602(4%), over = 6977, worst = 39 +PHY-1001 : End global iterations; 0.651037s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (148.8%) + +PHY-1001 : Congestion index: top1 = 77.52, top5 = 59.55, top10 = 51.12, top15 = 45.77. +PHY-3001 : End congestion estimation; 0.893491s wall, 1.140625s user + 0.062500s system = 1.203125s CPU (134.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.887422s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000134098 +PHY-3002 : Step(239): len = 674162, overlap = 73.5 +PHY-3002 : Step(240): len = 670596, overlap = 61.3125 +PHY-3002 : Step(241): len = 668312, overlap = 59.5625 +PHY-3002 : Step(242): len = 662072, overlap = 55.0625 +PHY-3002 : Step(243): len = 659219, overlap = 46.6562 +PHY-3002 : Step(244): len = 654533, overlap = 41.7188 +PHY-3002 : Step(245): len = 653845, overlap = 38.3438 +PHY-3002 : Step(246): len = 652502, overlap = 32.7812 +PHY-3002 : Step(247): len = 651565, overlap = 29 +PHY-3002 : Step(248): len = 649002, overlap = 29.2812 +PHY-3002 : Step(249): len = 647118, overlap = 26.875 +PHY-3002 : Step(250): len = 645340, overlap = 23.5 +PHY-3002 : Step(251): len = 644071, overlap = 22.3125 +PHY-3002 : Step(252): len = 642522, overlap = 22.6562 +PHY-3002 : Step(253): len = 643069, overlap = 19.5 +PHY-3002 : Step(254): len = 642226, overlap = 19.8438 +PHY-3002 : Step(255): len = 641386, overlap = 18.8438 +PHY-3002 : Step(256): len = 640522, overlap = 20.3125 +PHY-3002 : Step(257): len = 641564, overlap = 18.2188 +PHY-3002 : Step(258): len = 641706, overlap = 18.5938 +PHY-3002 : Step(259): len = 640729, overlap = 18.1875 +PHY-3002 : Step(260): len = 639333, overlap = 17.6562 +PHY-3002 : Step(261): len = 637600, overlap = 21.125 +PHY-3002 : Step(262): len = 635940, overlap = 22.1875 +PHY-3002 : Step(263): len = 634881, overlap = 26.125 +PHY-3002 : Step(264): len = 633529, overlap = 27.4375 +PHY-3002 : Step(265): len = 632208, overlap = 30.0312 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000268196 +PHY-3002 : Step(266): len = 633978, overlap = 28.4688 +PHY-3002 : Step(267): len = 636544, overlap = 29.0625 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 44/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 722688, over cnt = 2639(7%), over = 11351, worst = 45 +PHY-1001 : End global iterations; 1.646729s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (135.7%) + +PHY-1001 : Congestion index: top1 = 79.96, top5 = 64.73, top10 = 56.49, top15 = 51.40. +PHY-3001 : End congestion estimation; 1.918718s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (131.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.931553s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.45711e-05 +PHY-3002 : Step(268): len = 634348, overlap = 279.812 +PHY-3002 : Step(269): len = 639507, overlap = 216.344 +PHY-3002 : Step(270): len = 638353, overlap = 198.625 +PHY-3002 : Step(271): len = 634382, overlap = 177.656 +PHY-3002 : Step(272): len = 632561, overlap = 168.781 +PHY-3002 : Step(273): len = 632299, overlap = 158.906 +PHY-3002 : Step(274): len = 629659, overlap = 151.312 +PHY-3002 : Step(275): len = 626125, overlap = 147.844 +PHY-3002 : Step(276): len = 625185, overlap = 141.875 +PHY-3002 : Step(277): len = 623351, overlap = 138.406 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000189142 +PHY-3002 : Step(278): len = 623152, overlap = 137.344 +PHY-3002 : Step(279): len = 625031, overlap = 133.312 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000341742 +PHY-3002 : Step(280): len = 627249, overlap = 124.875 +PHY-3002 : Step(281): len = 634382, overlap = 114.781 +PHY-3002 : Step(282): len = 641077, overlap = 110.656 +PHY-3002 : Step(283): len = 647090, overlap = 103.875 +PHY-3002 : Step(284): len = 649306, overlap = 99.7812 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.431298s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (100.4%) + +RUN-1004 : used memory is 581 MB, reserved memory is 562 MB, peak memory is 716 MB +OPT-1001 : Total overflow 437.66 peak overflow 4.34 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1293/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 750200, over cnt = 3025(8%), over = 11597, worst = 30 +PHY-1001 : End global iterations; 1.190744s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (147.0%) + +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.18, top10 = 52.60, top15 = 48.96. +PHY-1001 : End incremental global routing; 1.526599s wall, 2.078125s user + 0.015625s system = 2.093750s CPU (137.2%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.903766s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.3%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17544 has valid locations, 333 needs to be replaced +PHY-3001 : design contains 17962 instances, 7448 luts, 9293 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6083 pins +PHY-3001 : Found 1246 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 673789 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16643/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 764288, over cnt = 3037(8%), over = 11623, worst = 30 +PHY-1001 : End global iterations; 0.235124s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (126.3%) + +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.30, top10 = 52.75, top15 = 49.18. +PHY-3001 : End congestion estimation; 0.486708s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (112.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85707, tnet num: 20364, tinst num: 17962, tnode num: 116573, tedge num: 137416. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.451236s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.1%) + +RUN-1004 : used memory is 634 MB, reserved memory is 631 MB, peak memory is 719 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.394666s wall, 2.296875s user + 0.093750s system = 2.390625s CPU (99.8%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(285): len = 672646, overlap = 1.375 +PHY-3002 : Step(286): len = 672026, overlap = 1.375 +PHY-3002 : Step(287): len = 671652, overlap = 1.5 +PHY-3002 : Step(288): len = 671270, overlap = 1.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16759/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 761576, over cnt = 3040(8%), over = 11693, worst = 30 +PHY-1001 : End global iterations; 0.195863s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.7%) + +PHY-1001 : Congestion index: top1 = 69.40, top5 = 58.58, top10 = 52.80, top15 = 49.30. +PHY-3001 : End congestion estimation; 0.450382s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.6%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.926446s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000435663 +PHY-3002 : Step(289): len = 671244, overlap = 101.719 +PHY-3002 : Step(290): len = 671463, overlap = 101.938 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000871325 +PHY-3002 : Step(291): len = 671601, overlap = 101.75 +PHY-3002 : Step(292): len = 671936, overlap = 102.031 +PHY-3001 : Final: Len = 671936, Over = 102.031 +PHY-3001 : End incremental placement; 4.916795s wall, 5.140625s user + 0.234375s system = 5.375000s CPU (109.3%) + +OPT-1001 : Total overflow 441.78 peak overflow 4.34 +OPT-1001 : End high-fanout net optimization; 7.885941s wall, 8.765625s user + 0.250000s system = 9.015625s CPU (114.3%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 709, peak = 740. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16686/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 765152, over cnt = 3002(8%), over = 10538, worst = 30 +PHY-1002 : len = 812976, over cnt = 2132(6%), over = 5931, worst = 20 +PHY-1002 : len = 868056, over cnt = 761(2%), over = 1696, worst = 16 +PHY-1002 : len = 884888, over cnt = 289(0%), over = 690, worst = 16 +PHY-1002 : len = 896184, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.027905s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (131.8%) + +PHY-1001 : Congestion index: top1 = 58.60, top5 = 51.57, top10 = 47.85, top15 = 45.55. +OPT-1001 : End congestion update; 2.292059s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (128.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.855022s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.5%) + +OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2 +OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 113 cells processed and 15600 slack improved +OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 31 cells processed and 3800 slack improved +OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 10 cells processed and 2650 slack improved +OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 15 cells processed and 200 slack improved +OPT-0007 : Iter 5: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 2 cells processed and 600 slack improved +OPT-1001 : End bottleneck based optimization; 3.720309s wall, 4.375000s user + 0.000000s system = 4.375000s CPU (117.6%) + +OPT-1001 : Current memory(MB): used = 700, reserve = 689, peak = 740. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16728/20547. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 896064, over cnt = 90(0%), over = 120, worst = 4 +PHY-1002 : len = 895760, over cnt = 57(0%), over = 67, worst = 3 +PHY-1002 : len = 895960, over cnt = 6(0%), over = 6, worst = 1 +PHY-1002 : len = 896024, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 896200, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.722240s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (112.5%) + +PHY-1001 : Congestion index: top1 = 58.62, top5 = 51.34, top10 = 47.67, top15 = 45.36. +OPT-1001 : End congestion update; 0.997396s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (108.1%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20369 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.794135s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.3%) + +OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2 +OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 18 cells processed and 4150 slack improved +OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.918521s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (104.2%) + +OPT-1001 : Current memory(MB): used = 711, reserve = 698, peak = 740. +OPT-1001 : End physical optimization; 15.256657s wall, 16.781250s user + 0.328125s system = 17.109375s CPU (112.1%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7448 LUT to BLE ... +SYN-4008 : Packed 7448 LUT and 3135 SEQ to BLE. +SYN-4003 : Packing 6163 remaining SEQ's ... +SYN-4005 : Packed 3683 SEQ with LUT/SLICE +SYN-4006 : 926 single LUT's are left +SYN-4006 : 2480 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9928/13783 primitive instances ... +PHY-3001 : End packing; 1.633907s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.4%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6887 instances +RUN-1001 : 3369 mslices, 3370 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17545 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9847 nets have 2 pins +RUN-1001 : 6021 nets have [3 - 5] pins +RUN-1001 : 978 nets have [6 - 10] pins +RUN-1001 : 325 nets have [11 - 20] pins +RUN-1001 : 342 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6885 instances, 6739 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3607 pins +PHY-3001 : Found 496 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 682734, Over = 288.75 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 7643/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 840584, over cnt = 1929(5%), over = 3204, worst = 7 +PHY-1002 : len = 848976, over cnt = 1202(3%), over = 1744, worst = 7 +PHY-1002 : len = 861872, over cnt = 503(1%), over = 681, worst = 7 +PHY-1002 : len = 867064, over cnt = 252(0%), over = 331, worst = 4 +PHY-1002 : len = 872872, over cnt = 4(0%), over = 4, worst = 1 +PHY-1001 : End global iterations; 1.639579s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (138.2%) + +PHY-1001 : Congestion index: top1 = 58.04, top5 = 50.67, top10 = 47.01, top15 = 44.60. +PHY-3001 : End congestion estimation; 2.037225s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (130.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73646, tnet num: 17367, tinst num: 6885, tnode num: 96231, tedge num: 123681. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.638472s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (100.1%) + +RUN-1004 : used memory is 621 MB, reserved memory is 614 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.567961s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (100.4%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.3821e-05 +PHY-3002 : Step(293): len = 671896, overlap = 282.5 +PHY-3002 : Step(294): len = 665349, overlap = 281 +PHY-3002 : Step(295): len = 660635, overlap = 273.25 +PHY-3002 : Step(296): len = 657063, overlap = 271.25 +PHY-3002 : Step(297): len = 654825, overlap = 274.5 +PHY-3002 : Step(298): len = 652635, overlap = 278 +PHY-3002 : Step(299): len = 650135, overlap = 282.75 +PHY-3002 : Step(300): len = 648515, overlap = 283.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.7642e-05 +PHY-3002 : Step(301): len = 651194, overlap = 274.25 +PHY-3002 : Step(302): len = 656248, overlap = 265.25 +PHY-3002 : Step(303): len = 658574, overlap = 262 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000175284 +PHY-3002 : Step(304): len = 666182, overlap = 251.75 +PHY-3002 : Step(305): len = 678087, overlap = 229 +PHY-3002 : Step(306): len = 680573, overlap = 221.5 +PHY-3002 : Step(307): len = 680972, overlap = 221.5 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.373038s wall, 0.421875s user + 0.515625s system = 0.937500s CPU (251.3%) + +PHY-3001 : Trial Legalized: Len = 760466 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 717/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 880240, over cnt = 2795(7%), over = 4672, worst = 7 +PHY-1002 : len = 897344, over cnt = 1708(4%), over = 2511, worst = 7 +PHY-1002 : len = 912568, over cnt = 842(2%), over = 1242, worst = 6 +PHY-1002 : len = 928584, over cnt = 281(0%), over = 419, worst = 6 +PHY-1002 : len = 935096, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.413250s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (141.8%) + +PHY-1001 : Congestion index: top1 = 56.12, top5 = 50.08, top10 = 47.38, top15 = 45.48. +PHY-3001 : End congestion estimation; 2.885740s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (134.3%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.867289s wall, 0.828125s user + 0.046875s system = 0.875000s CPU (100.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143513 +PHY-3002 : Step(308): len = 735027, overlap = 41.5 +PHY-3002 : Step(309): len = 718340, overlap = 63 +PHY-3002 : Step(310): len = 705093, overlap = 96.5 +PHY-3002 : Step(311): len = 696733, overlap = 116.25 +PHY-3002 : Step(312): len = 692473, overlap = 128 +PHY-3002 : Step(313): len = 689142, overlap = 139.25 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000287027 +PHY-3002 : Step(314): len = 693600, overlap = 139.5 +PHY-3002 : Step(315): len = 699671, overlap = 137.5 +PHY-3002 : Step(316): len = 704357, overlap = 143 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000574053 +PHY-3002 : Step(317): len = 708838, overlap = 142.5 +PHY-3002 : Step(318): len = 721779, overlap = 142 +PHY-3002 : Step(319): len = 724628, overlap = 146 +PHY-3002 : Step(320): len = 726277, overlap = 143.5 +PHY-3002 : Step(321): len = 728856, overlap = 142 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.033700s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.7%) + +PHY-3001 : Legalized: Len = 758015, Over = 0 +PHY-3001 : Spreading special nets. 501 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.109747s wall, 0.093750s user + 0.015625s system = 0.109375s CPU (99.7%) + +PHY-3001 : 740 instances has been re-located, deltaX = 212, deltaY = 439, maxDist = 3. +PHY-3001 : Final: Len = 767639, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73646, tnet num: 17367, tinst num: 6888, tnode num: 96231, tedge num: 123681. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.901276s wall, 1.859375s user + 0.031250s system = 1.890625s CPU (99.4%) + +RUN-1004 : used memory is 620 MB, reserved memory is 608 MB, peak memory is 740 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 3277/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 901968, over cnt = 2630(7%), over = 4221, worst = 6 +PHY-1002 : len = 916720, over cnt = 1471(4%), over = 2028, worst = 5 +PHY-1002 : len = 936176, over cnt = 396(1%), over = 532, worst = 5 +PHY-1002 : len = 942728, over cnt = 62(0%), over = 73, worst = 3 +PHY-1002 : len = 944240, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.122403s wall, 3.171875s user + 0.046875s system = 3.218750s CPU (151.7%) + +PHY-1001 : Congestion index: top1 = 55.60, top5 = 49.46, top10 = 46.52, top15 = 44.63. +PHY-1001 : End incremental global routing; 2.508802s wall, 3.562500s user + 0.046875s system = 3.609375s CPU (143.9%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.921544s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (100.0%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6795 has valid locations, 30 needs to be replaced +PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 770784 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16063/17580. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 948088, over cnt = 96(0%), over = 111, worst = 6 +PHY-1002 : len = 948200, over cnt = 64(0%), over = 69, worst = 2 +PHY-1002 : len = 948688, over cnt = 16(0%), over = 18, worst = 2 +PHY-1002 : len = 948912, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.604434s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (113.7%) + +PHY-1001 : Congestion index: top1 = 55.56, top5 = 49.52, top10 = 46.59, top15 = 44.70. +PHY-3001 : End congestion estimation; 0.919946s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (108.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73901, tnet num: 17402, tinst num: 6913, tnode num: 96557, tedge num: 124033. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.898673s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.6%) + +RUN-1004 : used memory is 656 MB, reserved memory is 647 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17402 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.803318s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (99.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(322): len = 770784, overlap = 0 +PHY-3002 : Step(323): len = 770784, overlap = 0 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16088/17580. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 948912, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.133790s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.4%) + +PHY-1001 : Congestion index: top1 = 55.56, top5 = 49.52, top10 = 46.59, top15 = 44.70. +PHY-3001 : End congestion estimation; 0.447954s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.7%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17402 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.869429s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.6%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000652812 +PHY-3002 : Step(324): len = 770283, overlap = 2 +PHY-3002 : Step(325): len = 770010, overlap = 2.25 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005737s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 770101, Over = 0 +PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061413s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.8%) + +PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2. +PHY-3001 : Final: Len = 770143, Over = 0 +PHY-3001 : End incremental placement; 5.512296s wall, 5.656250s user + 0.093750s system = 5.750000s CPU (104.3%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 9.428918s wall, 10.687500s user + 0.187500s system = 10.875000s CPU (115.3%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16043/17580. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 947424, over cnt = 108(0%), over = 118, worst = 3 +PHY-1002 : len = 947504, over cnt = 61(0%), over = 64, worst = 3 +PHY-1002 : len = 947968, over cnt = 23(0%), over = 23, worst = 1 +PHY-1002 : len = 948248, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.618440s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (106.1%) + +PHY-1001 : Congestion index: top1 = 55.58, top5 = 49.56, top10 = 46.55, top15 = 44.66. +OPT-1001 : End congestion update; 0.937871s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (105.0%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17402 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.728078s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.9%) + +OPT-0007 : Start: WNS -1086 TNS -1850 NUM_FEPS 3 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 775149, Over = 0 +PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.064219s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.3%) + +PHY-3001 : 35 instances has been re-located, deltaX = 22, deltaY = 23, maxDist = 4. +PHY-3001 : Final: Len = 775681, Over = 0 +PHY-3001 : End incremental legalization; 0.399341s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (109.6%) + +OPT-0007 : Iter 1: improved WNS -936 TNS -1421 NUM_FEPS 2 with 49 cells processed and 16995 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 778685, Over = 0 +PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061599s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.5%) + +PHY-3001 : 23 instances has been re-located, deltaX = 14, deltaY = 18, maxDist = 3. +PHY-3001 : Final: Len = 779319, Over = 0 +PHY-3001 : End incremental legalization; 0.384913s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (117.7%) + +OPT-0007 : Iter 2: improved WNS -886 TNS -1371 NUM_FEPS 2 with 29 cells processed and 5725 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 780021, Over = 0 +PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.067400s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.9%) + +PHY-3001 : 24 instances has been re-located, deltaX = 17, deltaY = 11, maxDist = 2. +PHY-3001 : Final: Len = 780535, Over = 0 +PHY-3001 : End incremental legalization; 0.392302s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%) + +OPT-0007 : Iter 3: improved WNS -836 TNS -1321 NUM_FEPS 2 with 25 cells processed and 1685 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 499 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 780499, Over = 0 +PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.068381s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.4%) + +PHY-3001 : 16 instances has been re-located, deltaX = 9, deltaY = 6, maxDist = 2. +PHY-3001 : Final: Len = 780787, Over = 0 +PHY-3001 : End incremental legalization; 0.473935s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (105.5%) + +OPT-0007 : Iter 4: improved WNS -836 TNS -1421 NUM_FEPS 2 with 18 cells processed and 1367 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 781207, Over = 0 +PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060897s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%) + +PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 4, maxDist = 2. +PHY-3001 : Final: Len = 781297, Over = 0 +PHY-3001 : End incremental legalization; 0.401806s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (120.5%) + +OPT-0007 : Iter 5: improved WNS -836 TNS -1421 NUM_FEPS 2 with 4 cells processed and 600 slack improved +OPT-1001 : End bottleneck based optimization; 4.413324s wall, 4.781250s user + 0.046875s system = 4.828125s CPU (109.4%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 15602/17584. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 958816, over cnt = 181(0%), over = 232, worst = 6 +PHY-1002 : len = 958984, over cnt = 102(0%), over = 115, worst = 4 +PHY-1002 : len = 959784, over cnt = 38(0%), over = 38, worst = 1 +PHY-1002 : len = 960440, over cnt = 3(0%), over = 3, worst = 1 +PHY-1002 : len = 960480, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.870559s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (107.7%) + +PHY-1001 : Congestion index: top1 = 55.73, top5 = 49.71, top10 = 46.68, top15 = 44.78. +OPT-1001 : End congestion update; 1.206309s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (106.2%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.733546s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%) + +OPT-0007 : Start: WNS -886 TNS -1471 NUM_FEPS 2 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 781349, Over = 0 +PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.061230s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%) + +PHY-3001 : 14 instances has been re-located, deltaX = 6, deltaY = 11, maxDist = 2. +PHY-3001 : Final: Len = 781527, Over = 0 +PHY-3001 : End incremental legalization; 0.396857s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.4%) + +OPT-0007 : Iter 1: improved WNS -836 TNS -1371 NUM_FEPS 2 with 21 cells processed and 2000 slack improved +OPT-0007 : Iter 2: improved WNS -836 TNS -1371 NUM_FEPS 2 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.517960s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (103.0%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.742114s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.0%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16011/17584. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 960424, over cnt = 50(0%), over = 61, worst = 4 +PHY-1002 : len = 960312, over cnt = 42(0%), over = 43, worst = 2 +PHY-1002 : len = 960744, over cnt = 8(0%), over = 8, worst = 1 +PHY-1002 : len = 960784, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 960880, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.822028s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (100.7%) + +PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.89, top10 = 46.77, top15 = 44.83. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.755042s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.4%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS -886 TNS -1471 NUM_FEPS 2 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.482759 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack -886ps with logic level 2 +RUN-1001 : extra opt step will be enabled to improve QoR +RUN-1001 : 0 HFN exist on timing critical paths out of 17584 nets +RUN-1001 : 0 long nets exist on timing critical paths out of 17584 nets +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 781527, Over = 0 +PHY-3001 : End spreading; 0.059816s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.5%) + +PHY-3001 : Final: Len = 781527, Over = 0 +PHY-3001 : End incremental legalization; 0.392323s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.845988s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (96.0%) + +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16091/17584. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 960880, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.131873s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.6%) + +PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.89, top10 = 46.77, top15 = 44.83. +OPT-1001 : End congestion update; 0.473927s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.9%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.743881s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.7%) + +OPT-0007 : Start: WNS -886 TNS -1471 NUM_FEPS 2 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 781497, Over = 0 +PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060029s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.1%) + +PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1. +PHY-3001 : Final: Len = 781527, Over = 0 +PHY-3001 : End incremental legalization; 0.395165s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.6%) + +OPT-0007 : Iter 1: improved WNS -836 TNS -1371 NUM_FEPS 2 with 2 cells processed and 100 slack improved +OPT-0007 : Iter 2: improved WNS -836 TNS -1371 NUM_FEPS 2 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.735135s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (106.3%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16091/17584. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 960880, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.148237s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.4%) + +PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.89, top10 = 46.77, top15 = 44.83. +OPT-1001 : End congestion update; 0.562725s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (94.4%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.931020s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (97.3%) + +OPT-0007 : Start: WNS -886 TNS -1471 NUM_FEPS 2 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 781583, Over = 0 +PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.076149s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.6%) + +PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1. +PHY-3001 : Final: Len = 781581, Over = 0 +PHY-3001 : End incremental legalization; 0.484067s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (103.3%) + +OPT-0007 : Iter 1: improved WNS -886 TNS -1371 NUM_FEPS 2 with 1 cells processed and 0 slack improved +OPT-0007 : Iter 2: improved WNS -886 TNS -1371 NUM_FEPS 2 with 0 cells processed and 0 slack improved +OPT-0007 : Iter 3: improved WNS -886 TNS -1371 NUM_FEPS 2 with 0 cells processed and 0 slack improved +OPT-1001 : End bottleneck based optimization; 2.313869s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (98.6%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.960547s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (97.6%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : Start congestion recovery ... +RUN-1002 : start command "set_param place ofv 80" +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.878862s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.6%) + +RUN-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16084/17584. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 960960, over cnt = 1(0%), over = 1, worst = 1 +PHY-1002 : len = 960968, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.319756s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (97.7%) + +PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.89, top10 = 46.76, top15 = 44.83. +RUN-1001 : End congestion update; 0.747698s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.2%) + +RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952 +OPT-1001 : End congestion recovery; 1.632537s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.5%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 738, peak = 748. +OPT-1001 : End physical optimization; 29.440762s wall, 31.015625s user + 0.296875s system = 31.312500s CPU (106.4%) + +RUN-1003 : finish command "place" in 73.029922s wall, 101.609375s user + 6.484375s system = 108.093750s CPU (148.0%) + +RUN-1004 : used memory is 623 MB, reserved memory is 607 MB, peak memory is 748 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.822302s wall, 3.140625s user + 0.015625s system = 3.156250s CPU (173.2%) + +RUN-1004 : used memory is 624 MB, reserved memory is 609 MB, peak memory is 748 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6920 instances +RUN-1001 : 3379 mslices, 3390 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17584 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9860 nets have 2 pins +RUN-1001 : 6024 nets have [3 - 5] pins +RUN-1001 : 978 nets have [6 - 10] pins +RUN-1001 : 334 nets have [11 - 20] pins +RUN-1001 : 360 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73936, tnet num: 17406, tinst num: 6918, tnode num: 96607, tedge num: 124081. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.798965s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.0%) + +RUN-1004 : used memory is 635 MB, reserved memory is 633 MB, peak memory is 748 MB +PHY-1001 : 3379 mslices, 3390 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 894304, over cnt = 2813(7%), over = 4576, worst = 8 +PHY-1002 : len = 914200, over cnt = 1633(4%), over = 2266, worst = 6 +PHY-1002 : len = 929808, over cnt = 750(2%), over = 1024, worst = 6 +PHY-1002 : len = 939024, over cnt = 342(0%), over = 451, worst = 5 +PHY-1002 : len = 949112, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.693173s wall, 5.156250s user + 0.015625s system = 5.171875s CPU (140.0%) + +PHY-1001 : Congestion index: top1 = 56.64, top5 = 49.64, top10 = 46.48, top15 = 44.61. +PHY-1001 : End global routing; 4.077676s wall, 5.546875s user + 0.015625s system = 5.562500s CPU (136.4%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 725, reserve = 721, peak = 748. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 995, reserve = 992, peak = 995. +PHY-1001 : End build detailed router design. 4.445157s wall, 4.343750s user + 0.109375s system = 4.453125s CPU (100.2%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 274112, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 6.734319s wall, 6.656250s user + 0.031250s system = 6.687500s CPU (99.3%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 274168, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.544160s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (100.5%) + +PHY-1001 : Current memory(MB): used = 1031, reserve = 1029, peak = 1031. +PHY-1001 : End phase 1; 7.293583s wall, 7.218750s user + 0.031250s system = 7.250000s CPU (99.4%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 44% nets. +PHY-1001 : Routed 51% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 73% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.37463e+06, over cnt = 1773(0%), over = 1781, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1047, reserve = 1042, peak = 1047. +PHY-1001 : End initial routed; 37.446258s wall, 82.578125s user + 0.375000s system = 82.953125s CPU (221.5%) + +PHY-1001 : Update timing..... +PHY-1001 : 6/16507(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -1.813 | -3.684 | 4 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.696178s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (99.8%) + +PHY-1001 : Current memory(MB): used = 1059, reserve = 1055, peak = 1059. +PHY-1001 : End phase 2; 41.142501s wall, 86.265625s user + 0.375000s system = 86.640625s CPU (210.6%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 5 pins with SWNS -1.946ns STNS -3.696ns FEP 3. +PHY-1001 : End OPT Iter 1; 0.157668s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.1%) + +PHY-1022 : len = 2.37468e+06, over cnt = 1779(0%), over = 1787, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.478727s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.2%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.34764e+06, over cnt = 771(0%), over = 772, worst = 2, crit = 0 +PHY-1001 : End DR Iter 1; 1.413572s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (169.1%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.34274e+06, over cnt = 199(0%), over = 199, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.902586s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (140.2%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.34376e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.744973s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (121.6%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.34393e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.287898s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (92.3%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.34401e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 5; 0.294504s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (95.5%) + +PHY-1001 : ===== DR Iter 6 ===== +PHY-1022 : len = 2.34401e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 6; 0.373532s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.4%) + +PHY-1001 : ===== DR Iter 7 ===== +PHY-1022 : len = 2.34401e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 7; 0.663512s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (98.9%) + +PHY-1001 : ===== DR Iter 8 ===== +PHY-1022 : len = 2.34402e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 8; 0.199863s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.6%) + +PHY-1001 : ==== DR Iter 9 ==== +PHY-1022 : len = 2.34391e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 9; 0.187416s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.0%) + +PHY-1001 : Update timing..... +PHY-1001 : 4/16507(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -1.946 | -3.696 | 3 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.669473s wall, 3.625000s user + 0.015625s system = 3.640625s CPU (99.2%) + +PHY-1001 : Commit to database..... +PHY-1001 : 548 feed throughs used by 407 nets +PHY-1001 : End commit to database; 2.437837s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1164, reserve = 1164, peak = 1164. +PHY-1001 : End phase 3; 12.124315s wall, 13.546875s user + 0.015625s system = 13.562500s CPU (111.9%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 3 pins with SWNS -1.670ns STNS -3.420ns FEP 3. +PHY-1001 : End OPT Iter 1; 0.155670s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.4%) + +PHY-1022 : len = 2.34388e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.456333s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.3%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.670ns, -3.420ns, 3} +PHY-1001 : Update timing..... +PHY-1001 : 4/16507(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -1.670 | -3.420 | 3 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.733495s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (98.3%) + +PHY-1001 : Commit to database..... +PHY-1001 : 549 feed throughs used by 408 nets +PHY-1001 : End commit to database; 2.547059s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (100.0%) + +PHY-1001 : Current memory(MB): used = 1173, reserve = 1173, peak = 1173. +PHY-1001 : End phase 4; 6.770554s wall, 6.703125s user + 0.000000s system = 6.703125s CPU (99.0%) + +PHY-1003 : Routed, final wirelength = 2.34388e+06 +PHY-1001 : Current memory(MB): used = 1174, reserve = 1175, peak = 1175. +PHY-1001 : End export database. 0.072877s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (107.2%) + +PHY-1001 : End detail routing; 72.295459s wall, 118.578125s user + 0.546875s system = 119.125000s CPU (164.8%) + +RUN-1003 : finish command "route" in 79.402122s wall, 127.140625s user + 0.562500s system = 127.703125s CPU (160.8%) + +RUN-1004 : used memory is 1100 MB, reserved memory is 1098 MB, peak memory is 1175 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10235 out of 19600 52.22% +#reg 9453 out of 19600 48.23% +#le 12651 + #lut only 3198 out of 12651 25.28% + #reg only 2416 out of 12651 19.10% + #lut® 7037 out of 12651 55.62% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1799 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1413 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 990 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P17 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG + debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12651 |9208 |1027 |9487 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |553 |469 |23 |441 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |46 |46 |0 |22 |0 |0 | +| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 | +| exdev_ctl_a |exdev_ctl |758 |324 |96 |572 |0 |0 | +| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 | +| u_gen_sp |gen_sp |262 |150 |71 |122 |0 |0 | +| exdev_ctl_b |exdev_ctl |764 |382 |96 |571 |0 |0 | +| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 | +| u_gen_sp |gen_sp |260 |156 |71 |119 |0 |0 | +| sampling_fe_a |sampling_fe |2995 |2402 |306 |2062 |25 |0 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort |2782 |2281 |289 |1887 |25 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_data_prebuffer |data_prebuffer |2372 |2004 |253 |1550 |22 |0 | +| channelPart |channel_part_8478 |180 |176 |3 |146 |0 |0 | +| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 | +| ram_switch |ram_switch |1840 |1540 |197 |1143 |0 |0 | +| adc_addr_gen |adc_addr_gen |233 |205 |27 |124 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| insert |insert |953 |681 |170 |642 |0 |0 | +| ram_switch_state |ram_switch_state |654 |654 |0 |377 |0 |0 | +| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 | +| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 | +| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |297 |177 |36 |264 |3 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3430 |2773 |349 |2118 |25 |1 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_ad_sampling |ad_sampling |187 |119 |17 |150 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort_rev |3214 |2638 |332 |1939 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2750 |2275 |290 |1588 |22 |1 | +| channelPart |channel_part_8478 |264 |251 |3 |148 |0 |0 | +| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 | +| ram_switch |ram_switch |2004 |1663 |197 |1139 |0 |0 | +| adc_addr_gen |adc_addr_gen |220 |193 |27 |104 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| insert |insert |983 |670 |170 |672 |0 |0 | +| ram_switch_state |ram_switch_state |801 |800 |0 |363 |0 |0 | +| read_ram_i |read_ram_rev |378 |269 |81 |217 |0 |0 | +| read_ram_addr |read_ram_addr_rev |307 |222 |73 |163 |0 |0 | +| read_ram_data |read_ram_data_rev |71 |47 |8 |54 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9798 + #2 2 3967 + #3 3 1431 + #4 4 623 + #5 5-10 1038 + #6 11-50 607 + #7 51-100 24 + #8 >500 1 + Average 2.91 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.240732s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (173.6%) + +RUN-1004 : used memory is 1101 MB, reserved memory is 1100 MB, peak memory is 1175 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73936, tnet num: 17406, tinst num: 6918, tnode num: 96607, tedge num: 124081. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.803686s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (98.8%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1104 MB, peak memory is 1175 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17406 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.693124s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (98.7%) + +RUN-1004 : used memory is 1108 MB, reserved memory is 1106 MB, peak memory is 1175 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6918 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17584, pip num: 173973 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 549 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 482068 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.998166s wall, 61.906250s user + 0.187500s system = 62.093750s CPU (621.1%) + +RUN-1004 : used memory is 1270 MB, reserved memory is 1265 MB, peak memory is 1386 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_163057.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_164001.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_164001.log new file mode 100644 index 0000000..1597a24 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_164001.log @@ -0,0 +1,2009 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:40:01 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.195129s wall, 2.125000s user + 0.078125s system = 2.203125s CPU (100.4%) + +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 350 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "place" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param place opt_timing high" +RUN-1001 : Print Place Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : detailed_place | on | on | +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : legalization | ori | ori | +RUN-1001 : new_spreading | on | on | +RUN-1001 : opt_timing | high | medium | * +RUN-1001 : post_clock_route_opt | off | off | +RUN-1001 : pr_strategy | 1 | 1 | +RUN-1001 : relaxation | 1.00 | 1.00 | +RUN-1001 : retiming | off | off | +RUN-1001 : -------------------------------------------------------------- +PHY-3001 : Placer runs in 8 thread(s). +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1 +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28] +SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] +SYN-5055 Similar messages will be suppressed. +RUN-1002 : start command "phys_opt -simplify_lut" +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins). +SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). +SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst. +SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst. +SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst. +SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst. +SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst. +SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst. +SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst. +SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst. +SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst. +SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst. +SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins. +SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins. +SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net +SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net +SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net +SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net +SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net +SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net +SYN-4026 : Tagged 15 rtl::Net as clock net +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. +SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 17682 instances +RUN-0007 : 7357 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20260 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 13191 nets have 2 pins +RUN-1001 : 5790 nets have [3 - 5] pins +RUN-1001 : 865 nets have [6 - 10] pins +RUN-1001 : 158 nets have [11 - 20] pins +RUN-1001 : 182 nets have [21 - 99] pins +RUN-1001 : 54 nets have 100+ pins +PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. +RUN-1001 : Report Control nets information: +RUN-1001 : DFF Distribution +RUN-1001 : ---------------------------------- +RUN-1001 : CE | SSR | ASR | DFF Count +RUN-1001 : ---------------------------------- +RUN-1001 : No | No | No | 793 +RUN-1001 : No | No | Yes | 2027 +RUN-1001 : No | Yes | No | 3473 +RUN-1001 : Yes | No | No | 64 +RUN-1001 : Yes | No | Yes | 72 +RUN-1001 : Yes | Yes | No | 2673 +RUN-1001 : ---------------------------------- +RUN-0007 : Control Group Statistic +RUN-0007 : --------------------------- +RUN-0007 : #CLK | #CE | #SSR/ASR +RUN-0007 : --------------------------- +RUN-0007 : 12 | 76 | 57 +RUN-0007 : --------------------------- +RUN-0007 : Control Set = 142 +PHY-3001 : Initial placement ... +PHY-3001 : design contains 17680 instances, 7357 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins +PHY-0007 : Cell area utilization is 48% +PHY-3001 : Start timing update ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.169949s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (100.2%) + +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.973139s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (100.6%) + +PHY-3001 : Found 1234 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 4.1219e+06 +PHY-3001 : Clustering ... +PHY-3001 : Level 0 #clusters 17680. +PHY-3001 : Level 1 #clusters 1973. +PHY-3001 : End clustering; 0.128462s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.3%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 48% +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(1): len = 1.28458e+06, overlap = 454.594 +PHY-3002 : Step(2): len = 1.19286e+06, overlap = 517.438 +PHY-3002 : Step(3): len = 834854, overlap = 592.562 +PHY-3002 : Step(4): len = 777443, overlap = 637.781 +PHY-3002 : Step(5): len = 600279, overlap = 721.844 +PHY-3002 : Step(6): len = 521980, overlap = 819.938 +PHY-3002 : Step(7): len = 451048, overlap = 893.281 +PHY-3002 : Step(8): len = 403911, overlap = 964.25 +PHY-3002 : Step(9): len = 368591, overlap = 1029.12 +PHY-3002 : Step(10): len = 338922, overlap = 1073.25 +PHY-3002 : Step(11): len = 304508, overlap = 1141.53 +PHY-3002 : Step(12): len = 279694, overlap = 1170.69 +PHY-3002 : Step(13): len = 252054, overlap = 1214.53 +PHY-3002 : Step(14): len = 238649, overlap = 1226.72 +PHY-3002 : Step(15): len = 215896, overlap = 1308.69 +PHY-3002 : Step(16): len = 208275, overlap = 1349.81 +PHY-3002 : Step(17): len = 186803, overlap = 1390.97 +PHY-3002 : Step(18): len = 181606, overlap = 1410.38 +PHY-3002 : Step(19): len = 161931, overlap = 1445.09 +PHY-3002 : Step(20): len = 158750, overlap = 1451.41 +PHY-3002 : Step(21): len = 144790, overlap = 1458.78 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10227e-06 +PHY-3002 : Step(22): len = 145764, overlap = 1436.72 +PHY-3002 : Step(23): len = 171419, overlap = 1355.31 +PHY-3002 : Step(24): len = 181024, overlap = 1285.84 +PHY-3002 : Step(25): len = 190053, overlap = 1252.5 +PHY-3002 : Step(26): len = 189802, overlap = 1232.38 +PHY-3002 : Step(27): len = 188169, overlap = 1167.09 +PHY-3002 : Step(28): len = 186098, overlap = 1152.94 +PHY-3002 : Step(29): len = 184554, overlap = 1153.88 +PHY-3002 : Step(30): len = 182246, overlap = 1160.28 +PHY-3002 : Step(31): len = 180553, overlap = 1150.56 +PHY-3002 : Step(32): len = 178023, overlap = 1131 +PHY-3002 : Step(33): len = 175804, overlap = 1116.19 +PHY-3002 : Step(34): len = 172887, overlap = 1111.69 +PHY-3002 : Step(35): len = 172318, overlap = 1092.16 +PHY-3002 : Step(36): len = 170745, overlap = 1082.41 +PHY-3002 : Step(37): len = 170225, overlap = 1078.19 +PHY-3002 : Step(38): len = 168406, overlap = 1092.12 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20454e-06 +PHY-3002 : Step(39): len = 173223, overlap = 1091 +PHY-3002 : Step(40): len = 183661, overlap = 1073.78 +PHY-3002 : Step(41): len = 187019, overlap = 1076.62 +PHY-3002 : Step(42): len = 191009, overlap = 1064.94 +PHY-3002 : Step(43): len = 192665, overlap = 1062.09 +PHY-3002 : Step(44): len = 195163, overlap = 1060.5 +PHY-3002 : Step(45): len = 192963, overlap = 1046.19 +PHY-3002 : Step(46): len = 193608, overlap = 1030.38 +PHY-3002 : Step(47): len = 192284, overlap = 1002.53 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.40908e-06 +PHY-3002 : Step(48): len = 200352, overlap = 983.75 +PHY-3002 : Step(49): len = 213737, overlap = 939.594 +PHY-3002 : Step(50): len = 219580, overlap = 886.688 +PHY-3002 : Step(51): len = 226210, overlap = 816.094 +PHY-3002 : Step(52): len = 229549, overlap = 804.75 +PHY-3002 : Step(53): len = 232138, overlap = 780.781 +PHY-3002 : Step(54): len = 233416, overlap = 765.125 +PHY-3002 : Step(55): len = 234157, overlap = 763 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.81817e-06 +PHY-3002 : Step(56): len = 245109, overlap = 742.219 +PHY-3002 : Step(57): len = 266212, overlap = 668.969 +PHY-3002 : Step(58): len = 277689, overlap = 618.844 +PHY-3002 : Step(59): len = 285405, overlap = 596.625 +PHY-3002 : Step(60): len = 288711, overlap = 579.406 +PHY-3002 : Step(61): len = 285269, overlap = 573.375 +PHY-3002 : Step(62): len = 282211, overlap = 567.625 +PHY-3002 : Step(63): len = 281487, overlap = 544.031 +PHY-3002 : Step(64): len = 281654, overlap = 536.062 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76363e-05 +PHY-3002 : Step(65): len = 298684, overlap = 505.062 +PHY-3002 : Step(66): len = 312625, overlap = 481.625 +PHY-3002 : Step(67): len = 320174, overlap = 451.344 +PHY-3002 : Step(68): len = 324546, overlap = 454.938 +PHY-3002 : Step(69): len = 322533, overlap = 425.188 +PHY-3002 : Step(70): len = 326215, overlap = 428.062 +PHY-3002 : Step(71): len = 325562, overlap = 429.625 +PHY-3002 : Step(72): len = 328832, overlap = 411.375 +PHY-3002 : Step(73): len = 327893, overlap = 403.625 +PHY-3002 : Step(74): len = 328559, overlap = 392.656 +PHY-3002 : Step(75): len = 328014, overlap = 378.594 +PHY-3002 : Step(76): len = 327790, overlap = 361.219 +PHY-3002 : Step(77): len = 327386, overlap = 365.656 +PHY-3002 : Step(78): len = 327424, overlap = 361.812 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.52727e-05 +PHY-3002 : Step(79): len = 347844, overlap = 345 +PHY-3002 : Step(80): len = 360317, overlap = 330.156 +PHY-3002 : Step(81): len = 359507, overlap = 338.219 +PHY-3002 : Step(82): len = 360230, overlap = 363.219 +PHY-3002 : Step(83): len = 360958, overlap = 361.75 +PHY-3002 : Step(84): len = 363179, overlap = 337.781 +PHY-3002 : Step(85): len = 362174, overlap = 335.562 +PHY-3002 : Step(86): len = 365967, overlap = 331.625 +PHY-3002 : Step(87): len = 366931, overlap = 327.406 +PHY-3002 : Step(88): len = 369206, overlap = 313.719 +PHY-3002 : Step(89): len = 365751, overlap = 298.844 +PHY-3002 : Step(90): len = 366337, overlap = 287.688 +PHY-3002 : Step(91): len = 367062, overlap = 293.812 +PHY-3002 : Step(92): len = 368680, overlap = 292.719 +PHY-3002 : Step(93): len = 366044, overlap = 303.5 +PHY-3002 : Step(94): len = 365356, overlap = 315.25 +PHY-3002 : Step(95): len = 365794, overlap = 306.25 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.05453e-05 +PHY-3002 : Step(96): len = 383373, overlap = 294.125 +PHY-3002 : Step(97): len = 396682, overlap = 289.375 +PHY-3002 : Step(98): len = 396725, overlap = 271.656 +PHY-3002 : Step(99): len = 398660, overlap = 253.812 +PHY-3002 : Step(100): len = 402517, overlap = 254.156 +PHY-3002 : Step(101): len = 405673, overlap = 241.094 +PHY-3002 : Step(102): len = 403429, overlap = 252.25 +PHY-3002 : Step(103): len = 405140, overlap = 248.125 +PHY-3002 : Step(104): len = 407766, overlap = 237.375 +PHY-3002 : Step(105): len = 409418, overlap = 249.156 +PHY-3002 : Step(106): len = 405880, overlap = 239.969 +PHY-3002 : Step(107): len = 405662, overlap = 235.875 +PHY-3002 : Step(108): len = 406048, overlap = 232.312 +PHY-3002 : Step(109): len = 406902, overlap = 237.75 +PHY-3002 : Step(110): len = 404493, overlap = 248.5 +PHY-3002 : Step(111): len = 404712, overlap = 239.375 +PHY-3002 : Step(112): len = 406242, overlap = 226.094 +PHY-3002 : Step(113): len = 407166, overlap = 224.438 +PHY-3002 : Step(114): len = 404269, overlap = 228.969 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000136152 +PHY-3002 : Step(115): len = 418935, overlap = 227.062 +PHY-3002 : Step(116): len = 427384, overlap = 206.469 +PHY-3002 : Step(117): len = 425584, overlap = 205.844 +PHY-3002 : Step(118): len = 425470, overlap = 212.75 +PHY-3002 : Step(119): len = 428820, overlap = 206.594 +PHY-3002 : Step(120): len = 432309, overlap = 196.875 +PHY-3002 : Step(121): len = 430894, overlap = 197.094 +PHY-3002 : Step(122): len = 432789, overlap = 200.562 +PHY-3002 : Step(123): len = 436136, overlap = 200.344 +PHY-3002 : Step(124): len = 439101, overlap = 196.25 +PHY-3002 : Step(125): len = 436715, overlap = 199.156 +PHY-3002 : Step(126): len = 436613, overlap = 197.156 +PHY-3002 : Step(127): len = 439831, overlap = 196.281 +PHY-3002 : Step(128): len = 443685, overlap = 196.625 +PHY-3002 : Step(129): len = 441926, overlap = 189.938 +PHY-3002 : Step(130): len = 441301, overlap = 179.031 +PHY-3002 : Step(131): len = 442397, overlap = 184.125 +PHY-3002 : Step(132): len = 443133, overlap = 199.562 +PHY-3002 : Step(133): len = 441362, overlap = 195.719 +PHY-3002 : Step(134): len = 441255, overlap = 209.875 +PHY-3002 : Step(135): len = 442109, overlap = 207.469 +PHY-3002 : Step(136): len = 442607, overlap = 207.156 +PHY-3002 : Step(137): len = 441272, overlap = 203.031 +PHY-3002 : Step(138): len = 441832, overlap = 203.344 +PHY-3002 : Step(139): len = 443179, overlap = 212.375 +PHY-3002 : Step(140): len = 444519, overlap = 214.75 +PHY-3002 : Step(141): len = 442739, overlap = 209.094 +PHY-3002 : Step(142): len = 442473, overlap = 207.844 +PHY-3002 : Step(143): len = 443263, overlap = 205.531 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000272303 +PHY-3002 : Step(144): len = 455518, overlap = 195.062 +PHY-3002 : Step(145): len = 464702, overlap = 185.5 +PHY-3002 : Step(146): len = 464857, overlap = 180.531 +PHY-3002 : Step(147): len = 465637, overlap = 183.438 +PHY-3002 : Step(148): len = 468027, overlap = 192.156 +PHY-3002 : Step(149): len = 469099, overlap = 190.906 +PHY-3002 : Step(150): len = 467659, overlap = 192.344 +PHY-3002 : Step(151): len = 467713, overlap = 188.438 +PHY-3002 : Step(152): len = 470120, overlap = 192.5 +PHY-3002 : Step(153): len = 472631, overlap = 190.406 +PHY-3002 : Step(154): len = 472240, overlap = 188.5 +PHY-3002 : Step(155): len = 472491, overlap = 190.688 +PHY-3002 : Step(156): len = 473540, overlap = 190.875 +PHY-3002 : Step(157): len = 473764, overlap = 188.156 +PHY-3002 : Step(158): len = 472836, overlap = 191.719 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000517479 +PHY-3002 : Step(159): len = 481783, overlap = 185.75 +PHY-3002 : Step(160): len = 489324, overlap = 173.531 +PHY-3002 : Step(161): len = 490952, overlap = 175.844 +PHY-3002 : Step(162): len = 491576, overlap = 179.406 +PHY-3002 : Step(163): len = 493038, overlap = 172.75 +PHY-3002 : Step(164): len = 494288, overlap = 172.031 +PHY-3002 : Step(165): len = 494102, overlap = 170.969 +PHY-3002 : Step(166): len = 494482, overlap = 171.281 +PHY-3002 : Step(167): len = 495592, overlap = 167.562 +PHY-3002 : Step(168): len = 496404, overlap = 160.312 +PHY-3002 : Step(169): len = 496139, overlap = 161.219 +PHY-3002 : Step(170): len = 496343, overlap = 161.719 +PHY-3002 : Step(171): len = 497891, overlap = 156.531 +PHY-3002 : Step(172): len = 499031, overlap = 157.719 +PHY-3002 : Step(173): len = 498589, overlap = 156.281 +PHY-3002 : Step(174): len = 498494, overlap = 157.719 +PHY-3002 : Step(175): len = 498990, overlap = 159.594 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100707 +PHY-3002 : Step(176): len = 503830, overlap = 152.062 +PHY-3002 : Step(177): len = 509893, overlap = 150.5 +PHY-3002 : Step(178): len = 511435, overlap = 152.344 +PHY-3002 : Step(179): len = 512388, overlap = 133.812 +PHY-3002 : Step(180): len = 513505, overlap = 133.719 +PHY-3002 : Step(181): len = 514467, overlap = 129.719 +PHY-3002 : Step(182): len = 515230, overlap = 135.812 +PHY-3002 : Step(183): len = 516003, overlap = 136.906 +PHY-3002 : Step(184): len = 516865, overlap = 134.562 +PHY-3002 : Step(185): len = 517779, overlap = 130.688 +PHY-3002 : Step(186): len = 518736, overlap = 132.719 +PHY-3002 : Step(187): len = 519811, overlap = 126.688 +PHY-3002 : Step(188): len = 520285, overlap = 126.156 +PHY-3002 : Step(189): len = 520609, overlap = 125.312 +PHY-3002 : Step(190): len = 521783, overlap = 127.844 +PHY-3002 : Step(191): len = 524804, overlap = 133.906 +PHY-3002 : Step(192): len = 525311, overlap = 128.094 +PHY-3002 : Step(193): len = 525522, overlap = 127.75 +PHY-3002 : Step(194): len = 525992, overlap = 130.906 +PHY-3002 : Step(195): len = 526317, overlap = 127.812 +PHY-3002 : Step(196): len = 526461, overlap = 129.562 +PHY-3002 : Step(197): len = 526651, overlap = 128.719 +PHY-3002 : Step(198): len = 526598, overlap = 125.625 +PHY-3002 : Step(199): len = 526598, overlap = 125.625 +PHY-3002 : Step(200): len = 526552, overlap = 127.5 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00175132 +PHY-3002 : Step(201): len = 530576, overlap = 126.094 +PHY-3002 : Step(202): len = 538601, overlap = 110.594 +PHY-3002 : Step(203): len = 541750, overlap = 108.5 +PHY-3002 : Step(204): len = 544652, overlap = 105.531 +PHY-3002 : Step(205): len = 547197, overlap = 106.688 +PHY-3002 : Step(206): len = 548616, overlap = 102.438 +PHY-3002 : Step(207): len = 548103, overlap = 107.719 +PHY-3002 : Step(208): len = 547931, overlap = 106.031 +PHY-3002 : Step(209): len = 548688, overlap = 104.594 +PHY-3002 : Step(210): len = 548850, overlap = 104.406 +PHY-3002 : Step(211): len = 548658, overlap = 104.156 +PHY-3002 : Step(212): len = 548451, overlap = 102.812 +PHY-3002 : Step(213): len = 548705, overlap = 102.719 +PHY-3002 : Step(214): len = 549232, overlap = 110.531 +PHY-3002 : Step(215): len = 548966, overlap = 110.062 +PHY-3002 : Step(216): len = 548965, overlap = 106.812 +PHY-3002 : Step(217): len = 549793, overlap = 107.031 +PHY-3002 : Step(218): len = 550809, overlap = 106.312 +PHY-3002 : Step(219): len = 550869, overlap = 103.344 +PHY-3002 : Step(220): len = 550943, overlap = 103.188 +PHY-3002 : Step(221): len = 551329, overlap = 103.625 +PHY-3002 : Step(222): len = 551423, overlap = 103.688 +PHY-3002 : Step(223): len = 551233, overlap = 103.312 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00283364 +PHY-3002 : Step(224): len = 553382, overlap = 104.562 +PHY-3002 : Step(225): len = 556308, overlap = 104.5 +PHY-3002 : Step(226): len = 557092, overlap = 103.656 +PHY-3002 : Step(227): len = 557701, overlap = 103.594 +PHY-3002 : Step(228): len = 559575, overlap = 101.031 +PHY-3002 : Step(229): len = 561650, overlap = 102.812 +PHY-3002 : Step(230): len = 561954, overlap = 101.875 +PHY-3002 : Step(231): len = 562121, overlap = 101.688 +PHY-3002 : Step(232): len = 562575, overlap = 103.812 +PHY-3002 : Step(233): len = 563080, overlap = 103.562 +PHY-3002 : Step(234): len = 563399, overlap = 102.906 +PHY-3002 : Step(235): len = 563656, overlap = 109.125 +PHY-3002 : Step(236): len = 564193, overlap = 114.281 +PHY-3002 : Step(237): len = 564456, overlap = 114.406 +PHY-3002 : Step(238): len = 564464, overlap = 115.469 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.014158s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (110.4%) + +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +RUN-1001 : Building simple global routing graph ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 0/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 742288, over cnt = 1602(4%), over = 6977, worst = 39 +PHY-1001 : End global iterations; 0.659622s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (139.8%) + +PHY-1001 : Congestion index: top1 = 77.52, top5 = 59.55, top10 = 51.12, top15 = 45.77. +PHY-3001 : End congestion estimation; 0.889029s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (128.3%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.874409s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.1%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000134098 +PHY-3002 : Step(239): len = 674162, overlap = 73.5 +PHY-3002 : Step(240): len = 670596, overlap = 61.3125 +PHY-3002 : Step(241): len = 668312, overlap = 59.5625 +PHY-3002 : Step(242): len = 662072, overlap = 55.0625 +PHY-3002 : Step(243): len = 659219, overlap = 46.6562 +PHY-3002 : Step(244): len = 654533, overlap = 41.7188 +PHY-3002 : Step(245): len = 653845, overlap = 38.3438 +PHY-3002 : Step(246): len = 652502, overlap = 32.7812 +PHY-3002 : Step(247): len = 651565, overlap = 29 +PHY-3002 : Step(248): len = 649002, overlap = 29.2812 +PHY-3002 : Step(249): len = 647118, overlap = 26.875 +PHY-3002 : Step(250): len = 645340, overlap = 23.5 +PHY-3002 : Step(251): len = 644071, overlap = 22.3125 +PHY-3002 : Step(252): len = 642522, overlap = 22.6562 +PHY-3002 : Step(253): len = 643069, overlap = 19.5 +PHY-3002 : Step(254): len = 642226, overlap = 19.8438 +PHY-3002 : Step(255): len = 641386, overlap = 18.8438 +PHY-3002 : Step(256): len = 640522, overlap = 20.3125 +PHY-3002 : Step(257): len = 641564, overlap = 18.2188 +PHY-3002 : Step(258): len = 641706, overlap = 18.5938 +PHY-3002 : Step(259): len = 640729, overlap = 18.1875 +PHY-3002 : Step(260): len = 639333, overlap = 17.6562 +PHY-3002 : Step(261): len = 637600, overlap = 21.125 +PHY-3002 : Step(262): len = 635940, overlap = 22.1875 +PHY-3002 : Step(263): len = 634881, overlap = 26.125 +PHY-3002 : Step(264): len = 633529, overlap = 27.4375 +PHY-3002 : Step(265): len = 632208, overlap = 30.0312 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000268196 +PHY-3002 : Step(266): len = 633978, overlap = 28.4688 +PHY-3002 : Step(267): len = 636544, overlap = 29.0625 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 55% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 44/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 722688, over cnt = 2639(7%), over = 11351, worst = 45 +PHY-1001 : End global iterations; 1.654921s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (135.0%) + +PHY-1001 : Congestion index: top1 = 79.96, top5 = 64.73, top10 = 56.49, top15 = 51.40. +PHY-3001 : End congestion estimation; 1.929596s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (130.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.882366s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.45711e-05 +PHY-3002 : Step(268): len = 634348, overlap = 279.812 +PHY-3002 : Step(269): len = 639507, overlap = 216.344 +PHY-3002 : Step(270): len = 638353, overlap = 198.625 +PHY-3002 : Step(271): len = 634382, overlap = 177.656 +PHY-3002 : Step(272): len = 632561, overlap = 168.781 +PHY-3002 : Step(273): len = 632299, overlap = 158.906 +PHY-3002 : Step(274): len = 629659, overlap = 151.312 +PHY-3002 : Step(275): len = 626125, overlap = 147.844 +PHY-3002 : Step(276): len = 625185, overlap = 141.875 +PHY-3002 : Step(277): len = 623351, overlap = 138.406 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000189142 +PHY-3002 : Step(278): len = 623152, overlap = 137.344 +PHY-3002 : Step(279): len = 625031, overlap = 133.312 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000341742 +PHY-3002 : Step(280): len = 627249, overlap = 124.875 +PHY-3002 : Step(281): len = 634382, overlap = 114.781 +PHY-3002 : Step(282): len = 641077, overlap = 110.656 +PHY-3002 : Step(283): len = 647090, overlap = 103.875 +PHY-3002 : Step(284): len = 649306, overlap = 99.7812 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.464396s wall, 1.375000s user + 0.078125s system = 1.453125s CPU (99.2%) + +RUN-1004 : used memory is 581 MB, reserved memory is 563 MB, peak memory is 716 MB +OPT-1001 : Total overflow 437.66 peak overflow 4.34 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 1293/20260. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 750200, over cnt = 3025(8%), over = 11597, worst = 30 +PHY-1001 : End global iterations; 1.164716s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (143.5%) + +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.18, top10 = 52.60, top15 = 48.96. +PHY-1001 : End incremental global routing; 1.501090s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (133.2%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20082 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.924389s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.4%) + +OPT-1001 : 51 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 17544 has valid locations, 333 needs to be replaced +PHY-3001 : design contains 17962 instances, 7448 luts, 9293 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6083 pins +PHY-3001 : Found 1246 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 673789 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16643/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 764288, over cnt = 3037(8%), over = 11623, worst = 30 +PHY-1001 : End global iterations; 0.245305s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (159.2%) + +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.30, top10 = 52.75, top15 = 49.18. +PHY-3001 : End congestion estimation; 0.512588s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (125.0%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85707, tnet num: 20364, tinst num: 17962, tnode num: 116573, tedge num: 137416. +TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.467541s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (100.1%) + +RUN-1004 : used memory is 626 MB, reserved memory is 630 MB, peak memory is 720 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.432119s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (100.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(285): len = 672646, overlap = 1.375 +PHY-3002 : Step(286): len = 672026, overlap = 1.375 +PHY-3002 : Step(287): len = 671652, overlap = 1.5 +PHY-3002 : Step(288): len = 671270, overlap = 1.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 56% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16759/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 761576, over cnt = 3040(8%), over = 11693, worst = 30 +PHY-1001 : End global iterations; 0.217945s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (121.9%) + +PHY-1001 : Congestion index: top1 = 69.40, top5 = 58.58, top10 = 52.80, top15 = 49.30. +PHY-3001 : End congestion estimation; 0.514184s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (109.4%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 1.041445s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (100.5%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000435663 +PHY-3002 : Step(289): len = 671244, overlap = 101.719 +PHY-3002 : Step(290): len = 671463, overlap = 101.938 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000871325 +PHY-3002 : Step(291): len = 671601, overlap = 101.75 +PHY-3002 : Step(292): len = 671936, overlap = 102.031 +PHY-3001 : Final: Len = 671936, Over = 102.031 +PHY-3001 : End incremental placement; 5.176966s wall, 5.546875s user + 0.250000s system = 5.796875s CPU (112.0%) + +OPT-1001 : Total overflow 441.78 peak overflow 4.34 +OPT-1001 : End high-fanout net optimization; 8.148556s wall, 9.125000s user + 0.265625s system = 9.390625s CPU (115.2%) + +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 740. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16686/20542. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 765152, over cnt = 3002(8%), over = 10538, worst = 30 +PHY-1002 : len = 812976, over cnt = 2132(6%), over = 5931, worst = 20 +PHY-1002 : len = 868056, over cnt = 761(2%), over = 1696, worst = 16 +PHY-1002 : len = 884888, over cnt = 289(0%), over = 690, worst = 16 +PHY-1002 : len = 896184, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.062124s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (132.6%) + +PHY-1001 : Congestion index: top1 = 58.60, top5 = 51.57, top10 = 47.85, top15 = 45.55. +OPT-1001 : End congestion update; 2.343490s wall, 3.000000s user + 0.015625s system = 3.015625s CPU (128.7%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20364 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.987732s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (99.7%) + +OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 111 cells processed and 15600 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 3350 slack improved +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 2850 slack improved +OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 300 slack improved +OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 600 slack improved +OPT-1001 : End bottleneck based optimization; 3.821868s wall, 4.453125s user + 0.031250s system = 4.484375s CPU (117.3%) + +OPT-1001 : Current memory(MB): used = 702, reserve = 693, peak = 740. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16732/20547. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 896176, over cnt = 90(0%), over = 123, worst = 4 +PHY-1002 : len = 895912, over cnt = 56(0%), over = 66, worst = 3 +PHY-1002 : len = 896008, over cnt = 6(0%), over = 6, worst = 1 +PHY-1002 : len = 896072, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 896248, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.741561s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.2%) + +PHY-1001 : Congestion index: top1 = 58.62, top5 = 51.34, top10 = 47.68, top15 = 45.38. +OPT-1001 : End congestion update; 1.009068s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (102.2%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 20369 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.793360s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 4050 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 1.917433s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (101.0%) + +OPT-1001 : Current memory(MB): used = 710, reserve = 697, peak = 740. +OPT-1001 : End physical optimization; 15.654895s wall, 17.265625s user + 0.421875s system = 17.687500s CPU (113.0%) + +PHY-3001 : Start packing ... +SYN-4007 : Packing 0 MUX to BLE ... +SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. +SYN-4007 : Packing 7448 LUT to BLE ... +SYN-4008 : Packed 7448 LUT and 3135 SEQ to BLE. +SYN-4003 : Packing 6163 remaining SEQ's ... +SYN-4005 : Packed 3681 SEQ with LUT/SLICE +SYN-4006 : 927 single LUT's are left +SYN-4006 : 2482 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9930/13785 primitive instances ... +PHY-3001 : End packing; 1.602062s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.5%) + +PHY-1001 : Populate physical database on model huagao_mipi_top. +RUN-1001 : There are total 6896 instances +RUN-1001 : 3374 mslices, 3374 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17545 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9851 nets have 2 pins +RUN-1001 : 6027 nets have [3 - 5] pins +RUN-1001 : 967 nets have [6 - 10] pins +RUN-1001 : 327 nets have [11 - 20] pins +RUN-1001 : 341 nets have [21 - 99] pins +RUN-1001 : 12 nets have 100+ pins +PHY-3001 : design contains 6894 instances, 6748 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3610 pins +PHY-3001 : Found 501 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 682532, Over = 287.5 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 7667/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 840296, over cnt = 1918(5%), over = 3183, worst = 8 +PHY-1002 : len = 848552, over cnt = 1237(3%), over = 1777, worst = 7 +PHY-1002 : len = 859040, over cnt = 629(1%), over = 897, worst = 7 +PHY-1002 : len = 867864, over cnt = 283(0%), over = 378, worst = 7 +PHY-1002 : len = 874280, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.605348s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (145.0%) + +PHY-1001 : Congestion index: top1 = 58.90, top5 = 50.94, top10 = 47.01, top15 = 44.61. +PHY-3001 : End congestion estimation; 1.995014s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (137.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73662, tnet num: 17367, tinst num: 6894, tnode num: 96251, tedge num: 123708. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.617917s wall, 1.562500s user + 0.046875s system = 1.609375s CPU (99.5%) + +RUN-1004 : used memory is 622 MB, reserved memory is 612 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.530576s wall, 2.468750s user + 0.062500s system = 2.531250s CPU (100.0%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.53163e-05 +PHY-3002 : Step(293): len = 672031, overlap = 281.5 +PHY-3002 : Step(294): len = 665879, overlap = 283.75 +PHY-3002 : Step(295): len = 661339, overlap = 284.25 +PHY-3002 : Step(296): len = 657755, overlap = 275.5 +PHY-3002 : Step(297): len = 655544, overlap = 272.25 +PHY-3002 : Step(298): len = 653398, overlap = 277.75 +PHY-3002 : Step(299): len = 651231, overlap = 279.75 +PHY-3002 : Step(300): len = 649348, overlap = 278.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.06325e-05 +PHY-3002 : Step(301): len = 652932, overlap = 268 +PHY-3002 : Step(302): len = 657516, overlap = 255 +PHY-3002 : Step(303): len = 658296, overlap = 254 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000181265 +PHY-3002 : Step(304): len = 669665, overlap = 239.25 +PHY-3002 : Step(305): len = 678322, overlap = 229.75 +PHY-3002 : Step(306): len = 677223, overlap = 229 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.330318s wall, 0.234375s user + 0.578125s system = 0.812500s CPU (246.0%) + +PHY-3001 : Trial Legalized: Len = 757736 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 73% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 793/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 877440, over cnt = 2744(7%), over = 4613, worst = 8 +PHY-1002 : len = 893744, over cnt = 1693(4%), over = 2544, worst = 8 +PHY-1002 : len = 917680, over cnt = 558(1%), over = 770, worst = 8 +PHY-1002 : len = 925560, over cnt = 213(0%), over = 305, worst = 4 +PHY-1002 : len = 929944, over cnt = 17(0%), over = 22, worst = 3 +PHY-1001 : End global iterations; 2.288810s wall, 3.515625s user + 0.046875s system = 3.562500s CPU (155.6%) + +PHY-1001 : Congestion index: top1 = 57.26, top5 = 50.76, top10 = 47.63, top15 = 45.52. +PHY-3001 : End congestion estimation; 2.745855s wall, 3.984375s user + 0.046875s system = 4.031250s CPU (146.8%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.856888s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.3%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140758 +PHY-3002 : Step(307): len = 731886, overlap = 40 +PHY-3002 : Step(308): len = 715385, overlap = 69.75 +PHY-3002 : Step(309): len = 702138, overlap = 103.25 +PHY-3002 : Step(310): len = 694199, overlap = 126.5 +PHY-3002 : Step(311): len = 689561, overlap = 142.25 +PHY-3002 : Step(312): len = 686302, overlap = 161 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000281517 +PHY-3002 : Step(313): len = 691059, overlap = 155.75 +PHY-3002 : Step(314): len = 696867, overlap = 151.5 +PHY-3002 : Step(315): len = 700207, overlap = 154.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000563034 +PHY-3002 : Step(316): len = 704208, overlap = 152 +PHY-3002 : Step(317): len = 716769, overlap = 142.75 +PHY-3002 : Step(318): len = 726097, overlap = 147.5 +PHY-3002 : Step(319): len = 724477, overlap = 152.25 +PHY-3002 : Step(320): len = 722958, overlap = 150.75 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.035588s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (87.8%) + +PHY-3001 : Legalized: Len = 753230, Over = 0 +PHY-3001 : Spreading special nets. 502 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.117334s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (93.2%) + +PHY-3001 : 763 instances has been re-located, deltaX = 218, deltaY = 480, maxDist = 4. +PHY-3001 : Final: Len = 763732, Over = 0 +PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 +PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 +OPT-1001 : Start physical optimization ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73662, tnet num: 17367, tinst num: 6897, tnode num: 96251, tedge num: 123708. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.925068s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.8%) + +RUN-1004 : used memory is 644 MB, reserved memory is 656 MB, peak memory is 740 MB +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : Start high-fanout net optimization ... +OPT-1001 : Update timing in global mode +PHY-1001 : Start incremental global routing, caller is place ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 3147/17545. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 892688, over cnt = 2553(7%), over = 4249, worst = 7 +PHY-1002 : len = 906992, over cnt = 1650(4%), over = 2401, worst = 6 +PHY-1002 : len = 922168, over cnt = 838(2%), over = 1189, worst = 5 +PHY-1002 : len = 932744, over cnt = 349(0%), over = 472, worst = 4 +PHY-1002 : len = 941992, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.055849s wall, 2.984375s user + 0.046875s system = 3.031250s CPU (147.4%) + +PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.40, top10 = 46.57, top15 = 44.78. +PHY-1001 : End incremental global routing; 2.432615s wall, 3.359375s user + 0.046875s system = 3.406250s CPU (140.0%) + +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17367 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.878006s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.7%) + +OPT-1001 : 5 high-fanout net processed. +PHY-3001 : Start incremental placement ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6804 has valid locations, 26 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Global placement ... +PHY-3001 : Initial: Len = 766643 +PHY-3001 : Run with size of 4 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16088/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 945112, over cnt = 91(0%), over = 106, worst = 5 +PHY-1002 : len = 945224, over cnt = 45(0%), over = 49, worst = 4 +PHY-1002 : len = 945592, over cnt = 12(0%), over = 12, worst = 1 +PHY-1002 : len = 945792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.605416s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (103.2%) + +PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.46, top10 = 46.63, top15 = 44.85. +PHY-3001 : End congestion estimation; 0.922613s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (103.3%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73870, tnet num: 17397, tinst num: 6918, tnode num: 96518, tedge num: 123998. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.866370s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.5%) + +RUN-1004 : used memory is 653 MB, reserved memory is 642 MB, peak memory is 740 MB +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 2.760902s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (100.2%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 +PHY-3002 : Step(321): len = 766643, overlap = 0.25 +PHY-3002 : Step(322): len = 766643, overlap = 0.25 +PHY-3001 : Run with size of 2 +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Analyzing congestion ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Incremental mode ON +PHY-1001 : Reuse net number 16108/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 945792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.141181s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%) + +PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.46, top10 = 46.63, top15 = 44.85. +PHY-3001 : End congestion estimation; 0.479341s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.1%) + +PHY-3001 : Update density targets... +PHY-3001 : Update congestion history... +PHY-3001 : Update timing in global mode ... +TMR-2503 : Start to update net delay, extr mode = 5. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 5. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-3001 : End timing update; 0.876138s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%) + +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000660531 +PHY-3002 : Step(323): len = 766351, overlap = 0.5 +PHY-3002 : Step(324): len = 766411, overlap = 1 +PHY-3001 : Legalization ... +PHY-3001 : End legalization; 0.005803s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) + +PHY-3001 : Legalized: Len = 766540, Over = 0 +PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059511s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.0%) + +PHY-3001 : 2 instances has been re-located, deltaX = 6, deltaY = 0, maxDist = 3. +PHY-3001 : Final: Len = 766658, Over = 0 +PHY-3001 : End incremental placement; 5.508754s wall, 5.671875s user + 0.031250s system = 5.703125s CPU (103.5%) + +OPT-1001 : Total overflow 0.00 peak overflow 0.00 +OPT-1001 : End high-fanout net optimization; 9.492859s wall, 10.562500s user + 0.093750s system = 10.656250s CPU (112.3%) + +OPT-1001 : Current memory(MB): used = 745, reserve = 741, peak = 751. +OPT-1001 : Start bottleneck based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16078/17575. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 945224, over cnt = 95(0%), over = 106, worst = 5 +PHY-1002 : len = 945368, over cnt = 50(0%), over = 54, worst = 4 +PHY-1002 : len = 945840, over cnt = 17(0%), over = 17, worst = 1 +PHY-1002 : len = 946056, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.622496s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (107.9%) + +PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.41, top10 = 46.58, top15 = 44.81. +OPT-1001 : End congestion update; 0.938541s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (104.9%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17397 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.718193s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%) + +OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 772964, Over = 0 +PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062103s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%) + +PHY-3001 : 32 instances has been re-located, deltaX = 16, deltaY = 24, maxDist = 3. +PHY-3001 : Final: Len = 773674, Over = 0 +PHY-3001 : End incremental legalization; 0.426299s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.6%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 53 cells processed and 16636 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 776062, Over = 0 +PHY-3001 : Spreading special nets. 22 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062992s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.2%) + +PHY-3001 : 29 instances has been re-located, deltaX = 23, deltaY = 20, maxDist = 3. +PHY-3001 : Final: Len = 776308, Over = 0 +PHY-3001 : End incremental legalization; 0.381739s wall, 0.531250s user + 0.031250s system = 0.562500s CPU (147.4%) + +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 29 cells processed and 8130 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 776400, Over = 0 +PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059385s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.2%) + +PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 7, maxDist = 2. +PHY-3001 : Final: Len = 776724, Over = 0 +PHY-3001 : End incremental legalization; 0.381257s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (110.7%) + +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 913 slack improved +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6921 instances, 6772 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 777060, Over = 0 +PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060879s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.7%) + +PHY-3001 : 6 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 2. +PHY-3001 : Final: Len = 777170, Over = 0 +PHY-3001 : End incremental legalization; 0.380412s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (123.2%) + +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 350 slack improved +OPT-1001 : End bottleneck based optimization; 3.782100s wall, 4.171875s user + 0.062500s system = 4.234375s CPU (112.0%) + +OPT-1001 : Current memory(MB): used = 744, reserve = 740, peak = 751. +OPT-1001 : Start path based optimization ... +OPT-1001 : Start congestion update ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 15628/17578. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 955952, over cnt = 203(0%), over = 264, worst = 4 +PHY-1002 : len = 955872, over cnt = 112(0%), over = 128, worst = 4 +PHY-1002 : len = 956728, over cnt = 49(0%), over = 51, worst = 2 +PHY-1002 : len = 957264, over cnt = 5(0%), over = 6, worst = 2 +PHY-1002 : len = 957432, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.903488s wall, 0.984375s user + 0.046875s system = 1.031250s CPU (114.1%) + +PHY-1001 : Congestion index: top1 = 55.75, top5 = 49.94, top10 = 46.93, top15 = 45.03. +OPT-1001 : End congestion update; 1.223481s wall, 1.296875s user + 0.046875s system = 1.343750s CPU (109.8%) + +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17400 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.735771s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%) + +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 +PHY-3001 : Start incremental legalization ... +PHY-1001 : Populate physical database on model huagao_mipi_top. +PHY-3001 : Initial placement ... +PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced +PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced +PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6921 instances, 6772 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 777382, Over = 0 +PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060935s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%) + +PHY-3001 : 15 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2. +PHY-3001 : Final: Len = 777438, Over = 0 +PHY-3001 : End incremental legalization; 0.379118s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (94.8%) + +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 1850 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.473393s wall, 2.515625s user + 0.046875s system = 2.562500s CPU (103.6%) + +OPT-1001 : Current memory(MB): used = 745, reserve = 740, peak = 751. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17400 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.721478s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%) + +OPT-1001 : Start pin optimization... +OPT-1001 : skip pin optimization... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Reuse net number 16047/17578. +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 957536, over cnt = 65(0%), over = 68, worst = 2 +PHY-1002 : len = 957520, over cnt = 34(0%), over = 35, worst = 2 +PHY-1002 : len = 957720, over cnt = 13(0%), over = 13, worst = 1 +PHY-1002 : len = 957808, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 957856, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.771293s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.3%) + +PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.90, top10 = 46.89, top15 = 45.00. +OPT-1001 : Update timing in Manhattan mode +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17400 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +OPT-1001 : End timing update; 0.743694s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.7%) + +RUN-1001 : QoR Analysis: +OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.379310 +RUN-1001 : Top critical paths +RUN-1001 : #1 path slack 171ps with logic level 1 +OPT-1001 : End physical optimization; 20.502210s wall, 21.984375s user + 0.234375s system = 22.218750s CPU (108.4%) + +RUN-1003 : finish command "place" in 65.321814s wall, 93.562500s user + 6.406250s system = 99.968750s CPU (153.0%) + +RUN-1004 : used memory is 619 MB, reserved memory is 620 MB, peak memory is 751 MB +RUN-1002 : start command "export_db hg_anlogic_place.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.688800s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (173.9%) + +RUN-1004 : used memory is 619 MB, reserved memory is 620 MB, peak memory is 751 MB +RUN-1002 : start command "route" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Route Property +RUN-1001 : ------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------- +RUN-1001 : effort | medium | medium | +RUN-1001 : fix_hold | off | off | +RUN-1001 : opt_timing | medium | medium | +RUN-1001 : phy_sim_model | off | off | +RUN-1001 : priority | timing | timing | +RUN-1001 : swap_pin | on | on | +RUN-1001 : ------------------------------------------------------- +PHY-1001 : Route runs in 8 thread(s) +RUN-1001 : There are total 6923 instances +RUN-1001 : 3390 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17578 nets +RUN-6004 WARNING: There are 20 nets with only 1 pin. +RUN-1001 : 9863 nets have 2 pins +RUN-1001 : 6029 nets have [3 - 5] pins +RUN-1001 : 968 nets have [6 - 10] pins +RUN-1001 : 331 nets have [11 - 20] pins +RUN-1001 : 359 nets have [21 - 99] pins +RUN-1001 : 8 nets have 100+ pins +RUN-1002 : start command "start_timer -report" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73898, tnet num: 17400, tinst num: 6921, tnode num: 96556, tedge num: 124038. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -report" in 1.613675s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (99.7%) + +RUN-1004 : used memory is 612 MB, reserved memory is 603 MB, peak memory is 751 MB +PHY-1001 : 3390 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps +TMR-2503 : Start to update net delay, extr mode = 3. +TMR-2504 : Update delay of 17400 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 3. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +PHY-1001 : Start global routing, caller is route ... +RUN-1001 : Generating global routing grids ... +PHY-1001 : Generate routing nets ... +PHY-1001 : Global iterations in 8 thread ... +PHY-1002 : len = 886744, over cnt = 2771(7%), over = 4543, worst = 7 +PHY-1002 : len = 906680, over cnt = 1612(4%), over = 2237, worst = 7 +PHY-1002 : len = 927336, over cnt = 465(1%), over = 635, worst = 6 +PHY-1002 : len = 938064, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 938224, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.112924s wall, 4.328125s user + 0.062500s system = 4.390625s CPU (141.0%) + +PHY-1001 : Congestion index: top1 = 55.43, top5 = 49.50, top10 = 46.60, top15 = 44.64. +PHY-1001 : End global routing; 3.440037s wall, 4.656250s user + 0.062500s system = 4.718750s CPU (137.2%) + +PHY-1001 : Start detail routing ... +PHY-1001 : Current memory(MB): used = 719, reserve = 714, peak = 751. +PHY-1001 : Detailed router is running in normal mode. +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : Current memory(MB): used = 991, reserve = 986, peak = 991. +PHY-1001 : End build detailed router design. 3.984718s wall, 3.906250s user + 0.062500s system = 3.968750s CPU (99.6%) + +PHY-1001 : Detail Route ... +PHY-1001 : ===== Detail Route Phase 1 ===== +PHY-1001 : Clock net routing..... +PHY-1001 : Routed 0% nets. +PHY-1022 : len = 274696, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 4.987476s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (100.3%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 274752, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.428174s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.5%) + +PHY-1001 : Current memory(MB): used = 1027, reserve = 1023, peak = 1027. +PHY-1001 : End phase 1; 5.429324s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (100.2%) + +PHY-1001 : ===== Detail Route Phase 2 ===== +PHY-1001 : Initial routing..... +PHY-1001 : Routed 44% nets. +PHY-1001 : Routed 50% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 72% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.37878e+06, over cnt = 1768(0%), over = 1777, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1046, reserve = 1042, peak = 1046. +PHY-1001 : End initial routed; 26.947337s wall, 64.171875s user + 0.281250s system = 64.453125s CPU (239.2%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16501(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.512 | -0.512 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.271242s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.3%) + +PHY-1001 : Current memory(MB): used = 1066, reserve = 1063, peak = 1066. +PHY-1001 : End phase 2; 30.218646s wall, 67.453125s user + 0.281250s system = 67.734375s CPU (224.1%) + +PHY-1001 : ===== Detail Route Phase 3 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.512ns STNS -0.512ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.135394s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%) + +PHY-1022 : len = 2.37878e+06, over cnt = 1768(0%), over = 1777, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.403136s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%) + +PHY-1001 : Ripup-reroute..... +PHY-1001 : ===== DR Iter 1 ===== +PHY-1022 : len = 2.35112e+06, over cnt = 741(0%), over = 741, worst = 1, crit = 0 +PHY-1001 : End DR Iter 1; 1.141622s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (190.2%) + +PHY-1001 : ===== DR Iter 2 ===== +PHY-1022 : len = 2.34766e+06, over cnt = 186(0%), over = 186, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.787219s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (152.8%) + +PHY-1001 : ===== DR Iter 3 ===== +PHY-1022 : len = 2.34914e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.439321s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (113.8%) + +PHY-1001 : ===== DR Iter 4 ===== +PHY-1022 : len = 2.34927e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.228050s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.6%) + +PHY-1001 : ===== DR Iter 5 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 5; 0.200645s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.2%) + +PHY-1001 : ===== DR Iter 6 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 6; 0.244432s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.9%) + +PHY-1001 : ===== DR Iter 7 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 7; 0.339440s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (96.7%) + +PHY-1001 : ===== DR Iter 8 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 8; 0.174811s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.3%) + +PHY-1001 : ==== DR Iter 9 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 9; 0.171525s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.2%) + +PHY-1001 : ==== DR Iter 10 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 10; 0.197391s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.9%) + +PHY-1001 : ==== DR Iter 11 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 11; 0.238155s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%) + +PHY-1001 : ==== DR Iter 12 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 12; 0.420331s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%) + +PHY-1001 : ===== DR Iter 13 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 13; 0.186551s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.5%) + +PHY-1001 : ==== DR Iter 14 ==== +PHY-1022 : len = 2.34933e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 14; 0.166296s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.4%) + +PHY-1001 : Update timing..... +PHY-1001 : 1/16501(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.512 | -0.512 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.263322s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%) + +PHY-1001 : Commit to database..... +PHY-1001 : 539 feed throughs used by 407 nets +PHY-1001 : End commit to database; 2.244404s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (99.6%) + +PHY-1001 : Current memory(MB): used = 1167, reserve = 1166, peak = 1167. +PHY-1001 : End phase 3; 11.268225s wall, 12.765625s user + 0.015625s system = 12.781250s CPU (113.4%) + +PHY-1001 : ===== Detail Route Phase 4 ===== +PHY-1001 : Optimize timing..... +PHY-1001 : ===== OPT Iter 1 ===== +PHY-1001 : Processed 1 pins with SWNS -0.512ns STNS -0.512ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.134571s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.5%) + +PHY-1022 : len = 2.34933e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.375858s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%) + +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.512ns, -0.512ns, 1} +PHY-1001 : Update timing..... +PHY-1001 : 1/16501(0%) critical/total net(s). +RUN-1001 : -------------------------------------- +RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP +RUN-1001 : -------------------------------------- +RUN-1001 : Setup | -0.512 | -0.512 | 1 +RUN-1001 : Hold | 0.067 | 0.000 | 0 +RUN-1001 : -------------------------------------- +PHY-1001 : End update timing; 3.302470s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%) + +PHY-1001 : Commit to database..... +PHY-1001 : 539 feed throughs used by 407 nets +PHY-1001 : End commit to database; 2.338182s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (99.6%) + +PHY-1001 : Current memory(MB): used = 1175, reserve = 1175, peak = 1175. +PHY-1001 : End phase 4; 6.043345s wall, 6.046875s user + 0.000000s system = 6.046875s CPU (100.1%) + +PHY-1003 : Routed, final wirelength = 2.34933e+06 +PHY-1001 : Current memory(MB): used = 1177, reserve = 1178, peak = 1177. +PHY-1001 : End export database. 0.063897s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.8%) + +PHY-1001 : End detail routing; 57.404755s wall, 96.062500s user + 0.359375s system = 96.421875s CPU (168.0%) + +RUN-1003 : finish command "route" in 63.537357s wall, 103.375000s user + 0.468750s system = 103.843750s CPU (163.4%) + +RUN-1004 : used memory is 1100 MB, reserved memory is 1098 MB, peak memory is 1177 MB +RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Utilization Statistics +#lut 10230 out of 19600 52.19% +#reg 9451 out of 19600 48.22% +#le 12649 + #lut only 3198 out of 12649 25.28% + #reg only 2419 out of 12649 19.12% + #lut® 7032 out of 12649 55.59% +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% +#gclk 6 out of 16 37.50% + +Clock Resource Statistics +Index ClockNet Type DriverType Driver Fanout +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1415 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 989 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70 +#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26 +#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2 +#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 +#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 +#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 +#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1 + + +Detailed IO Report + + Name Direction Location IOStandard DriveStrength PullType PackReg + a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE + a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1 + a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1 + a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1 + b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE + b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1 + b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1 + b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1 + clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE + global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE + onoff_in INPUT P141 LVCMOS33 N/A N/A NONE + paper_in INPUT P17 LVCMOS25 N/A N/A NONE + rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG + O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L + O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L + O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE + O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG + O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2 + O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2 + O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2 + O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2 + O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2 + O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE + O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE + O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE + O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE + O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG + O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG + O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG + O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG + a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE + a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE + a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE + a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG + b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE + b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE + b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE + b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG + debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG + debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE + debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG + debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG + debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG + debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG + debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG + debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE + frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG + onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE + paper_out OUTPUT P106 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE + txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG + +Report Hierarchy Area: ++---------------------------------------------------------------------------------------------------------+ +|Instance |Module |le |lut |ripple |seq |bram |dsp | ++---------------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |12649 |9203 |1027 |9485 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |559 |475 |23 |441 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |52 |52 |0 |23 |0 |0 | +| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 | +| exdev_ctl_a |exdev_ctl |761 |324 |96 |573 |0 |0 | +| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 | +| u_gen_sp |gen_sp |265 |152 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |766 |382 |96 |571 |0 |0 | +| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 | +| u_gen_sp |gen_sp |262 |156 |71 |119 |0 |0 | +| sampling_fe_a |sampling_fe |2990 |2397 |306 |2064 |25 |0 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort |2777 |2276 |289 |1889 |25 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_data_prebuffer |data_prebuffer |2369 |2001 |253 |1552 |22 |0 | +| channelPart |channel_part_8478 |179 |175 |3 |146 |0 |0 | +| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 | +| ram_switch |ram_switch |1838 |1538 |197 |1145 |0 |0 | +| adc_addr_gen |adc_addr_gen |234 |206 |27 |125 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| insert |insert |955 |683 |170 |644 |0 |0 | +| ram_switch_state |ram_switch_state |649 |649 |0 |376 |0 |0 | +| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 | +| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 | +| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |295 |175 |36 |264 |3 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3425 |2768 |349 |2117 |25 |1 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_ad_sampling |ad_sampling |186 |118 |17 |151 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort_rev |3208 |2632 |332 |1935 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2742 |2267 |290 |1583 |22 |1 | +| channelPart |channel_part_8478 |263 |250 |3 |149 |0 |0 | +| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 | +| ram_switch |ram_switch |1999 |1658 |197 |1136 |0 |0 | +| adc_addr_gen |adc_addr_gen |221 |194 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| insert |insert |972 |659 |170 |667 |0 |0 | +| ram_switch_state |ram_switch_state |806 |805 |0 |363 |0 |0 | +| read_ram_i |read_ram_rev |376 |267 |81 |214 |0 |0 | +| read_ram_addr |read_ram_addr_rev |307 |222 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |69 |45 |8 |52 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- |- | ++---------------------------------------------------------------------------------------------------------+ + + +DataNet Average Fanout: + + Index Fanout Nets + #1 1 9801 + #2 2 3950 + #3 3 1453 + #4 4 623 + #5 5-10 1031 + #6 11-50 602 + #7 51-100 22 + #8 >500 1 + Average 2.91 + +RUN-1002 : start command "export_db hg_anlogic_pr.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.081133s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (173.4%) + +RUN-1004 : used memory is 1101 MB, reserved memory is 1100 MB, peak memory is 1177 MB +RUN-1002 : start command "start_timer" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73898, tnet num: 17400, tinst num: 6921, tnode num: 96556, tedge num: 124038. +TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer" in 1.622712s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (98.2%) + +RUN-1004 : used memory is 1106 MB, reserved memory is 1105 MB, peak memory is 1177 MB +RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" +TMR-2503 : Start to update net delay, extr mode = 6. +TMR-2504 : Update delay of 17400 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 6. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +TMR-3506 : Start to generate timing report. +TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted). +TMR-5009 WARNING: No clock constraint on 3 clock net(s): + exdev_ctl_a/u_ADconfig/clk_config_syn_4 + exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 + exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 +TMR-3508 : Export timing summary. +TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.496224s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (100.3%) + +RUN-1004 : used memory is 1109 MB, reserved memory is 1107 MB, peak memory is 1177 MB +RUN-1002 : start command "export_bid hg_anlogic_inst.bid" +PRG-1000 : +RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" +BIT-1003 : Start to generate bitstream. +BIT-1002 : Init instances with 8 threads. +BIT-1002 : Init instances completely, inst num: 6921 +BIT-1002 : Init pips with 8 threads. +BIT-1002 : Init pips completely, net num: 17578, pip num: 173874 +BIT-1002 : Init feedthrough with 8 threads. +BIT-1002 : Init feedthrough completely, num: 539 +BIT-1003 : Multithreading accelaration with 8 threads. +BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 481518 bits set as '1'. +BIT-1004 : the usercode register value: 00000000101110110000000000000000 +BIT-1004 : PLL setting string = 1011 +BIT-1004 : Generate bits file hg_anlogic.bit. +BIT-1004 : Generate bin file hg_anlogic.bin. +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.230834s wall, 69.484375s user + 0.203125s system = 69.687500s CPU (681.2%) + +RUN-1004 : used memory is 1269 MB, reserved memory is 1265 MB, peak memory is 1384 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_164001.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151000.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151000.log new file mode 100644 index 0000000..9c9de07 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151000.log @@ -0,0 +1,1896 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:10:00 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.073400s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.0%) + +RUN-1004 : used memory is 200 MB, reserved memory is 171 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54097/19243 useful/useless nets, 20839/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38316 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42624/8976 useful/useless nets, 11086/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40297/363 useful/useless nets, 37494/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29924 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25923/1547 useful/useless nets, 23212/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25674/80 useful/useless nets, 22995/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25581/93 useful/useless nets, 22913/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25303/20 useful/useless nets, 22651/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.919789s wall, 16.656250s user + 2.203125s system = 18.859375s CPU (99.7%) + +RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 13998 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 206 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 617 + #FADD 0 + #DFF 9137 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4855 |9143 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.103612s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (154.3%) + +RUN-1004 : used memory is 345 MB, reserved memory is 314 MB, peak memory is 403 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs BUSY_MIPI" +RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25337/24 useful/useless nets, 22700/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25655/670 useful/useless nets, 23034/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29091/338 useful/useless nets, 26471/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36635/296 useful/useless nets, 33909/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122075, tnet num: 36637, tinst num: 33909, tnode num: 156327, tedge num: 179790. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.362332s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (100.9%) + +RUN-1004 : used memory is 522 MB, reserved memory is 498 MB, peak memory is 522 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36637 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7499 (3.86), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7387 (3.95), #lev = 7 (3.05) +SYN-3001 : Logic optimization runtime opt = 1.22 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18920 instances into 7415 LUTs, name keeping = 58%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9990 + #lut4 5314 + #lut5 2121 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9990 out of 19600 50.97% +#reg 9217 out of 19600 47.03% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7435 |2555 |9249 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |338 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |286 |234 |559 |0 |0 | +| u_ADconfig |AD_config |99 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |129 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |278 |234 |546 |0 |0 | +| u_ADconfig |AD_config |93 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |127 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2323 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2253 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1478 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 | +| read_ram_i |read_ram |198 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |168 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |29 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2342 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2272 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1929 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1484 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9217 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.510626s wall, 58.156250s user + 0.343750s system = 58.500000s CPU (100.0%) + +RUN-1004 : used memory is 398 MB, reserved memory is 383 MB, peak memory is 706 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.554266s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (172.9%) + +RUN-1004 : used memory is 406 MB, reserved memory is 390 MB, peak memory is 706 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_151000.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151954.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151954.log new file mode 100644 index 0000000..4b13d61 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_151954.log @@ -0,0 +1,1546 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:19:54 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(763) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(771) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(774) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(945) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1034) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1335) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1346) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1364) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1546) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1942) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(606) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(744) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1346) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1425) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1508) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1546) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1942) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.093946s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (100.0%) + +RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54164/19276 useful/useless nets, 20886/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42693/8971 useful/useless nets, 11135/4738 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "BUSY_MIPI_sync_d0_syn_3" in ../../../../hg_mp/drx_top/huagao_mipi_top.v(566) +SYN-5014 WARNING: the net's pin: pin "i" in ../../../../hg_mp/drx_top/huagao_mipi_top.v(566) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40365/363 useful/useless nets, 37563/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3949 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6250 instances. +SYN-1015 : Optimize round 1, 29934 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25995/1547 useful/useless nets, 23285/7581 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9425 better +SYN-1032 : 25746/80 useful/useless nets, 23068/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25653/93 useful/useless nets, 22986/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25375/20 useful/useless nets, 22724/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.889419s wall, 16.593750s user + 2.296875s system = 18.890625s CPU (100.0%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 353 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14025 + #and 2485 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9157 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4862 |9163 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1852 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1808 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1553 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |126 |164 |32 | +| read_ram_addr |read_ram_addr |74 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.061108s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (163.4%) + +RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 403 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u2_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u2_BUSY_MIPI//temp[*]" +USR-8133 ERROR: No register match the pattern: u2_BUSY_MIPI//temp[*]. +USR-8159 ERROR: ../../hg_anlogic.sdc Line: 28, set_false_path -from [get_nets {u2_BUSY_MIPI/signal_from[*]}] -to [get_regs {u2_BUSY_MIPI//temp[*]}] fails. +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_151954.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_152528.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_152528.log new file mode 100644 index 0000000..fd91983 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_152528.log @@ -0,0 +1,1900 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:25:28 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(763) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(771) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(774) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(945) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1034) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1335) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1346) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1364) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1546) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1942) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(606) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(744) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1346) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1425) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1508) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1546) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1942) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1308) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.061257s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (100.1%) + +RUN-1004 : used memory is 199 MB, reserved memory is 171 MB, peak memory is 241 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54194/19276 useful/useless nets, 20906/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42723/8971 useful/useless nets, 11155/4738 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "BUSY_MIPI_sync_d0_syn_3" in ../../../../hg_mp/drx_top/huagao_mipi_top.v(566) +SYN-5014 WARNING: the net's pin: pin "i" in ../../../../hg_mp/drx_top/huagao_mipi_top.v(566) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40395/363 useful/useless nets, 37593/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3949 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6250 instances. +SYN-1015 : Optimize round 1, 29944 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 26025/1547 useful/useless nets, 23315/7581 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9425 better +SYN-1032 : 25776/80 useful/useless nets, 23098/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25683/93 useful/useless nets, 23016/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25405/20 useful/useless nets, 22754/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.750855s wall, 16.781250s user + 1.640625s system = 18.421875s CPU (98.2%) + +RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14035 + #and 2485 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9167 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4862 |9173 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1852 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1808 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1553 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |126 |164 |32 | +| read_ram_addr |read_ram_addr |74 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.093225s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (157.2%) + +RUN-1004 : used memory is 331 MB, reserved memory is 300 MB, peak memory is 404 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u2_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u2_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25439/24 useful/useless nets, 22803/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25757/670 useful/useless nets, 23137/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 315 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29191/338 useful/useless nets, 26572/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36735/296 useful/useless nets, 34010/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122345, tnet num: 36737, tinst num: 34010, tnode num: 156789, tedge num: 180225. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.286578s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (100.8%) + +RUN-1004 : used memory is 522 MB, reserved memory is 498 MB, peak memory is 522 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36737 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7496 (3.86), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7364 (3.96), #lev = 7 (3.09) +SYN-3001 : Logic optimization runtime opt = 1.21 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18925 instances into 7392 LUTs, name keeping = 58%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9967 + #lut4 5250 + #lut5 2162 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9967 out of 19600 50.85% +#reg 9247 out of 19600 47.18% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7412 |2555 |9279 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |334 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |49 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |285 |234 |559 |0 |0 | +| u_ADconfig |AD_config |98 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |129 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |125 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2320 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2250 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1911 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1483 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 | +| read_ram_i |read_ram |195 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |168 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |26 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2332 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2262 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1923 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1480 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1086 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |208 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |180 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9247 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 57.061084s wall, 56.687500s user + 0.375000s system = 57.062500s CPU (100.0%) + +RUN-1004 : used memory is 400 MB, reserved memory is 390 MB, peak memory is 705 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.553140s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (177.1%) + +RUN-1004 : used memory is 407 MB, reserved memory is 388 MB, peak memory is 705 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_152528.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_153428.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_153428.log new file mode 100644 index 0000000..fcd14b1 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_153428.log @@ -0,0 +1,1893 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:34:28 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.051877s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (101.0%) + +RUN-1004 : used memory is 199 MB, reserved memory is 173 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54097/19243 useful/useless nets, 20839/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38316 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42624/8976 useful/useless nets, 11086/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40297/363 useful/useless nets, 37494/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29924 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25923/1547 useful/useless nets, 23212/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25674/80 useful/useless nets, 22995/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25581/93 useful/useless nets, 22913/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25303/20 useful/useless nets, 22651/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.806124s wall, 16.656250s user + 2.140625s system = 18.796875s CPU (100.0%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 13998 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 206 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 617 + #FADD 0 + #DFF 9137 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4855 |9143 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.052349s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (161.8%) + +RUN-1004 : used memory is 344 MB, reserved memory is 314 MB, peak memory is 403 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25337/24 useful/useless nets, 22700/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25655/670 useful/useless nets, 23034/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29091/338 useful/useless nets, 26471/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36635/296 useful/useless nets, 33909/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122075, tnet num: 36637, tinst num: 33909, tnode num: 156327, tedge num: 179790. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.274736s wall, 1.218750s user + 0.046875s system = 1.265625s CPU (99.3%) + +RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36637 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7499 (3.86), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7387 (3.95), #lev = 7 (3.05) +SYN-3001 : Logic optimization runtime opt = 1.32 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18920 instances into 7415 LUTs, name keeping = 58%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9990 + #lut4 5314 + #lut5 2121 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9990 out of 19600 50.97% +#reg 9217 out of 19600 47.03% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7435 |2555 |9249 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |338 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |286 |234 |559 |0 |0 | +| u_ADconfig |AD_config |99 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |129 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |278 |234 |546 |0 |0 | +| u_ADconfig |AD_config |93 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |127 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2323 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2253 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1478 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 | +| read_ram_i |read_ram |198 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |168 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |29 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2342 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2272 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1929 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1484 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9217 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 60.043018s wall, 59.625000s user + 0.375000s system = 60.000000s CPU (99.9%) + +RUN-1004 : used memory is 397 MB, reserved memory is 380 MB, peak memory is 703 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.563382s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (173.9%) + +RUN-1004 : used memory is 405 MB, reserved memory is 383 MB, peak memory is 703 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_153428.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154318.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154318.log new file mode 100644 index 0000000..355ac04 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154318.log @@ -0,0 +1,1898 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:43:18 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.102425s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.6%) + +RUN-1004 : used memory is 200 MB, reserved memory is 170 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54149/19275 useful/useless nets, 20878/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29939 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 19.015761s wall, 16.937500s user + 1.593750s system = 18.531250s CPU (97.5%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 356 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14015 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9152 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4857 |9158 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.108924s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (157.8%) + +RUN-1004 : used memory is 350 MB, reserved memory is 319 MB, peak memory is 404 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u1_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u1_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122206, tnet num: 36686, tinst num: 33958, tnode num: 156552, tedge num: 180003. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.275405s wall, 1.187500s user + 0.062500s system = 1.250000s CPU (98.0%) + +RUN-1004 : used memory is 522 MB, reserved memory is 498 MB, peak memory is 522 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36686 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7496 (3.86), #lev = 9 (3.13) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7391 (3.95), #lev = 7 (3.07) +SYN-3001 : Logic optimization runtime opt = 1.19 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18922 instances into 7419 LUTs, name keeping = 58%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9994 + #lut4 5324 + #lut5 2115 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9994 out of 19600 50.99% +#reg 9232 out of 19600 47.10% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7439 |2555 |9264 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |338 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |289 |234 |559 |0 |0 | +| u_ADconfig |AD_config |103 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |275 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |125 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2327 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2257 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1918 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1478 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 | +| read_ram_i |read_ram |207 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |174 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |32 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2335 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2265 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1926 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1479 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1085 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |212 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |184 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9232 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.058941s wall, 57.687500s user + 0.328125s system = 58.015625s CPU (99.9%) + +RUN-1004 : used memory is 394 MB, reserved memory is 366 MB, peak memory is 705 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.558037s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (175.5%) + +RUN-1004 : used memory is 430 MB, reserved memory is 411 MB, peak memory is 705 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_154318.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154921.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154921.log new file mode 100644 index 0000000..c48b9d4 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_154921.log @@ -0,0 +1,1543 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:49:21 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(721) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(754) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(756) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(762) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(936) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1025) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1326) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1337) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1355) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1537) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1933) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(597) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(735) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1337) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1416) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1499) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1537) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1933) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.135487s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.5%) + +RUN-1004 : used memory is 200 MB, reserved memory is 170 MB, peak memory is 241 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54097/19243 useful/useless nets, 20839/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38316 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42624/8976 useful/useless nets, 11086/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40297/363 useful/useless nets, 37494/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29924 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25923/1547 useful/useless nets, 23212/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25674/80 useful/useless nets, 22995/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25581/93 useful/useless nets, 22913/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25303/20 useful/useless nets, 22651/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.688670s wall, 16.968750s user + 1.718750s system = 18.687500s CPU (100.0%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 13998 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 206 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 617 + #FADD 0 + #DFF 9137 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4855 |9143 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.093164s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (157.2%) + +RUN-1004 : used memory is 331 MB, reserved memory is 300 MB, peak memory is 404 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u1_BUSY_MIPI/signal_from[*]" +USR-8132 ERROR: No net match the pattern: u1_BUSY_MIPI/signal_from[*]. +USR-8159 ERROR: ../../hg_anlogic.sdc Line: 28, set_false_path -from [get_nets {u1_BUSY_MIPI/signal_from[*]}] -to [get_regs {u1_BUSY_MIPI/temp[*]}] fails. +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_154921.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_155007.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_155007.log new file mode 100644 index 0000000..f84a584 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_155007.log @@ -0,0 +1,1893 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 15:50:07 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(721) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(730) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(754) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(756) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(762) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(765) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(936) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1025) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1326) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1337) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1355) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1537) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1933) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(597) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(735) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1337) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1416) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1499) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1537) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1933) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1299) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.093293s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (98.6%) + +RUN-1004 : used memory is 200 MB, reserved memory is 168 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54097/19243 useful/useless nets, 20839/1798 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38316 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42624/8976 useful/useless nets, 11086/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40297/363 useful/useless nets, 37494/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29924 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25923/1547 useful/useless nets, 23212/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25674/80 useful/useless nets, 22995/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25581/93 useful/useless nets, 22913/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25303/20 useful/useless nets, 22651/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.514365s wall, 16.937500s user + 1.562500s system = 18.500000s CPU (99.9%) + +RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 356 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 13998 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 206 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 617 + #FADD 0 + #DFF 9137 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4855 |9143 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.105817s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (155.4%) + +RUN-1004 : used memory is 329 MB, reserved memory is 299 MB, peak memory is 402 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25337/24 useful/useless nets, 22700/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25655/670 useful/useless nets, 23034/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29091/338 useful/useless nets, 26471/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36635/296 useful/useless nets, 33909/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122075, tnet num: 36637, tinst num: 33909, tnode num: 156327, tedge num: 179790. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.306709s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (100.4%) + +RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36637 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 13 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7499 (3.86), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7387 (3.95), #lev = 7 (3.05) +SYN-3001 : Logic optimization runtime opt = 1.29 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18920 instances into 7415 LUTs, name keeping = 58%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9990 + #lut4 5314 + #lut5 2121 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9990 out of 19600 50.97% +#reg 9217 out of 19600 47.03% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 19 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7435 |2555 |9249 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |338 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |286 |234 |559 |0 |0 | +| u_ADconfig |AD_config |99 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |129 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |278 |234 |546 |0 |0 | +| u_ADconfig |AD_config |93 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |127 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2323 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2253 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1909 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1478 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1084 |0 |216 |0 |0 | +| read_ram_i |read_ram |198 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |168 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |29 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2342 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2272 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1929 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1484 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9217 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 61.388381s wall, 61.093750s user + 0.218750s system = 61.312500s CPU (99.9%) + +RUN-1004 : used memory is 398 MB, reserved memory is 386 MB, peak memory is 704 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568796s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (172.3%) + +RUN-1004 : used memory is 405 MB, reserved memory is 389 MB, peak memory is 704 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_155007.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_161136.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_161136.log new file mode 100644 index 0000000..e486fa4 --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_161136.log @@ -0,0 +1,1898 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:11:37 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.105644s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.3%) + +RUN-1004 : used memory is 199 MB, reserved memory is 172 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29939 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 19.142923s wall, 16.796875s user + 1.906250s system = 18.703125s CPU (97.7%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 355 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14015 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9152 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4857 |9158 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.104196s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (159.9%) + +RUN-1004 : used memory is 345 MB, reserved memory is 314 MB, peak memory is 403 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" +RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" +RUN-1002 : start command "set_false_path -setup -from -to " +RUN-1002 : start command "get_nets u1_BUSY_MIPI/signal_from[*]" +RUN-1002 : start command "get_regs u1_BUSY_MIPI/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets a_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_regs clkubus_rstn" +RUN-1002 : start command "get_nets b_pclk_rstn" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.295900s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (100.1%) + +RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36686 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04) +SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9912 + #lut4 5066 + #lut5 2291 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9912 out of 19600 50.57% +#reg 9232 out of 19600 47.10% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 | +| u_ADconfig |AD_config |102 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |126 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2207 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1444 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 | +| read_ram_i |read_ram |189 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |27 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2227 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1443 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9232 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 59.251886s wall, 58.921875s user + 0.265625s system = 59.187500s CPU (99.9%) + +RUN-1004 : used memory is 398 MB, reserved memory is 388 MB, peak memory is 705 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.577354s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (171.4%) + +RUN-1004 : used memory is 405 MB, reserved memory is 386 MB, peak memory is 705 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_161136.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_162936.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_162936.log new file mode 100644 index 0000000..6e4722d --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_162936.log @@ -0,0 +1,1856 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:29:36 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.081212s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (101.2%) + +RUN-1004 : used memory is 200 MB, reserved memory is 171 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29939 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.862598s wall, 16.609375s user + 2.234375s system = 18.843750s CPU (99.9%) + +RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14015 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9152 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4857 |9158 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.056264s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (164.2%) + +RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 403 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.372219s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (100.2%) + +RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36686 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 0 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04) +SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9912 + #lut4 5066 + #lut5 2291 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9912 out of 19600 50.57% +#reg 9232 out of 19600 47.10% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 | +| u_ADconfig |AD_config |102 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |126 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2207 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1444 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 | +| read_ram_i |read_ram |189 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |27 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2227 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1443 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9232 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 56.820661s wall, 56.421875s user + 0.359375s system = 56.781250s CPU (99.9%) + +RUN-1004 : used memory is 394 MB, reserved memory is 379 MB, peak memory is 704 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.550849s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (176.3%) + +RUN-1004 : used memory is 405 MB, reserved memory is 386 MB, peak memory is 704 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_162936.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_163838.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_163838.log new file mode 100644 index 0000000..bb5b04c --- /dev/null +++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_163838.log @@ -0,0 +1,1862 @@ +============================================================ + Tang Dynasty, V5.6.71036 + Copyright (c) 2012-2023 Anlogic Inc. + Executable = D:/Anlogic/TD5.6.2/bin/td.exe + Built at = 20:34:38 Mar 21 2023 + Run by = holdtecs + Run Date = Tue Mar 12 16:38:38 2024 + + Run on = DESKTOP-5MQL5VE +============================================================ +RUN-1002 : start command "open_project hg_anlogic.prj" +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v +HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101) +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v +HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v +HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v +HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v +HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v +HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v +Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved. +This product includes software developed by the OpenSSL Project +for use in the OpenSSL Toolkit (http://www.openssl.org/) +Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) +All rights reserved. +This product includes cryptographic software written by Eric Young (eay@cryptsoft.com) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v +HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139) +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v +HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115) +HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v +HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257) +HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v +HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215) +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v +HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46) +HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61) +HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145) +HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v +RUN-1001 : Project manager successfully analyzed 61 source files. +RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176" +ARC-1001 : Device Initialization. +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : OPTION | IO | SETTING +ARC-1001 : ---------------------------------------------------------------------- +ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio +ARC-1001 : done | P10 | gpio +ARC-1001 : program_b | P134 | dedicate +ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate +ARC-1001 : ---------------------------------------------------------------------- +ARC-1004 : Device setting, marked 5 dedicate IOs in total. +RUN-1002 : start command "elaborate -top huagao_mipi_top" +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Design Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : default_reg_initial | auto | auto | +RUN-1001 : infer_add | on | on | +RUN-1001 : infer_fsm | off | off | +RUN-1001 : infer_mult | on | on | +RUN-1001 : infer_ram | on | on | +RUN-1001 : infer_reg | on | on | +RUN-1001 : infer_reg_init_value | on | on | +RUN-1001 : infer_rom | on | on | +RUN-1001 : infer_shifter | on | on | +RUN-1001 : -------------------------------------------------------------- +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) +HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) +HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) +HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24) +HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147) +HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3) +HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) +HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) +HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) +HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) +HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) +HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506) +HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507) +HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95) +HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116) +HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1) +HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345) +HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196) +HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3) +HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6) +HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1) +HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107) +HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2) +HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1) +HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3) +HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5) +HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1) +HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1) +HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1) +HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1) +HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1) +HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1) +HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14) +HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38) +HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336) +HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1) +HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1) +HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14) +HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032) +HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69) +HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313) +HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124) +HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1) +HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348) +HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378) +HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196) +HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3) +HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1) +HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1) +HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1) +HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368) +HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1) +HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72) +HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74) +HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1) +HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) +HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) +HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) +HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) +HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) +HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) +HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426) +HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) +HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) +HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) +HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3) +HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130) +HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3) +HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2) +HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3) +HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14) +HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142) +HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) +HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) +HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509) +HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) +HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) +HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed +HDL-1200 : Current top model is huagao_mipi_top +HDL-1100 : Inferred 1 RAMs. +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.113594s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (99.6%) + +RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB +RUN-1002 : start command "export_db hg_anlogic_elaborate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1002 : start command "read_adc ../../hg_anlogic.adc" +RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; " +RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; " +RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; " +RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;" +RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 " +RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper " +RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper " +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO setups legality check. +RUN-1001 : Starting of IO vref setups legality check. +USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint. +USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint. +USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint. +USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint. +USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint. +USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint. +USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint. +USR-6010 Similar messages will be suppressed. +RUN-1002 : start command "optimize_rtl" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Print Rtl Property +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : -------------------------------------------------------------- +RUN-1001 : compress_add | ripple | ripple | +RUN-1001 : elf_sload | off | off | +RUN-1001 : fix_undriven | 0 | 0 | +RUN-1001 : flatten | off | off | +RUN-1001 : gate_sharing | on | on | +RUN-1001 : hdl_warning_level | normal | normal | +RUN-1001 : impl_internal_tribuf | on | on | +RUN-1001 : impl_set_reset | on | on | +RUN-1001 : infer_gsr | off | off | +RUN-1001 : keep_hierarchy | auto | auto | +RUN-1001 : max_fanout | 9999 | 9999 | +RUN-1001 : max_oh2bin_len | 10 | 10 | +RUN-1001 : merge_equal | on | on | +RUN-1001 : merge_equiv | on | on | +RUN-1001 : merge_mux | off | off | +RUN-1001 : min_control_set | 8 | 8 | +RUN-1001 : min_ripple_len | auto | auto | +RUN-1001 : oh2bin_ratio | 0.08 | 0.08 | +RUN-1001 : opt_adder_fanout | on | on | +RUN-1001 : opt_arith | on | on | +RUN-1001 : opt_big_gate | off | off | +RUN-1001 : opt_const | on | on | +RUN-1001 : opt_const_mult | on | on | +RUN-1001 : opt_lessthan | on | on | +RUN-1001 : opt_mux | off | off | +RUN-1001 : opt_ram | high | high | +RUN-1001 : rtl_sim_model | off | off | +RUN-1001 : seq_syn | on | on | +RUN-1001 : -------------------------------------------------------------- +SYN-1012 : SanityCheck: Model "huagao_mipi_top" +SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage" +SYN-1012 : SanityCheck: Model "crc16_24b" +SYN-1012 : SanityCheck: Model "ecc_gen" +SYN-1012 : SanityCheck: Model "fifo_w32_d8192" +SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "AD_config" +SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)" +SYN-1012 : SanityCheck: Model "ad_sampling" +SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer" +SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)" +SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)" +SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)" +SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)" +SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)" +SYN-1012 : SanityCheck: Model "SORT_RAM_9k" +SYN-1012 : SanityCheck: Model "transfer_300_to_200" +SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI" +SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)" +SYN-1012 : SanityCheck: Model "data_prebuffer_rev" +SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)" +SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" +SYN-1012 : SanityCheck: Model "scan_start_diff" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" +SYN-1012 : SanityCheck: Model "ubus_top" +SYN-1012 : SanityCheck: Model "local_bus_slve_cis" +SYN-1012 : SanityCheck: Model "CRC4_D16" +SYN-1012 : SanityCheck: Model "uart_2dsp" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)" +SYN-1012 : SanityCheck: Model "fan_ctrl" +SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper" +SYN-1012 : SanityCheck: Model "hs_tx_wrapper" +SYN-1012 : SanityCheck: Model "data_lane_wrapper" +SYN-1012 : SanityCheck: Model "data_hs_generate" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)" +SYN-1012 : SanityCheck: Model "d1024_w8_fifo" +SYN-1012 : SanityCheck: Model "data_lp_generate" +SYN-1012 : SanityCheck: Model "clk_lane_wrapper" +SYN-1012 : SanityCheck: Model "clk_hs_generate" +SYN-1012 : SanityCheck: Model "clk_lp_generate" +SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)" +SYN-1012 : SanityCheck: Model "lp_tx_wrapper" +SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)" +SYN-1012 : SanityCheck: Model "pixel_cdc" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)" +SYN-1012 : SanityCheck: Model "pll" +SYN-1012 : SanityCheck: Model "pll_lvds" +SYN-1012 : SanityCheck: Model "lscc_sensor" +SYN-1012 : SanityCheck: Model "lvds_rx" +SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")" +SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr +SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr +SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback +SYN-1043 : Mark pll as IO macro for instance bufg_feedback +SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i +SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate +SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i +SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate +SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper +SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper +SYN-1011 : Flatten model huagao_mipi_top +SYN-1050 : Instances selected by 'keep_hierarchy': +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : instance | keep_hierarchy | down_module | file(line) +RUN-1001 : ------------------------------------------------------------------------------------------------ +RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t... +RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : ------------------------------------------------------------------------------------------------ +SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts +SYN-1001 : Optimize 156 less-than instances +SYN-1016 : Merged 38319 instances. +SYN-1025 : Merged 24 RAM ports. +SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 +SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. +SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts +SYN-1016 : Merged 1876 instances. +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203) +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0" +SYN-5011 Similar messages will be suppressed. +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14) +SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39) +SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16) +SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) +SYN-5014 Similar messages will be suppressed. +SYN-5025 WARNING: Using 0 for all undriven pins and nets +SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1017 : Remove 16 const input seq instances +SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 +SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10 +SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14 +SYN-1002 : u_bus_top/reg6_syn_19 +SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3 +SYN-1002 : u_senor/reg0_syn_10 +SYN-1002 : reg16_syn_2 +SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg +SYN-1002 : u_senor/reg1_syn_10 +SYN-1002 : reg17_syn_2 +SYN-1018 : Transformed 91 mux instances. +SYN-1019 : Optimized 127 mux instances. +SYN-1021 : Optimized 297 onehot mux instances. +SYN-1020 : Optimized 3951 distributor mux. +SYN-1001 : Optimize 12 less-than instances +SYN-1019 : Optimized 39 mux instances. +SYN-1016 : Merged 6256 instances. +SYN-1015 : Optimize round 1, 29939 better +SYN-1014 : Optimize round 2 +SYN-1044 : Optimized 15 inv instances. +SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts +SYN-1017 : Remove 29 const input seq instances +SYN-1002 : reg18_syn_2 +SYN-1002 : reg22_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16 +SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17 +SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3 +SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15 +SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15 +SYN-1002 : u_bus_top/reg8_syn_19 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8 +SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9 +SYN-1019 : Optimized 24 mux instances. +SYN-1020 : Optimized 43 distributor mux. +SYN-1016 : Merged 118 instances. +SYN-1015 : Optimize round 2, 9427 better +SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3004 : Optimized 8 const0 DFF(s) +SYN-3008 : Optimized 1 const1 DFF(s) +SYN-3004 : Optimized 1 const0 DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3003 : Optimized 1 equivalent DFF(s) +SYN-3004 : Optimized 2 const0 DFF(s) +SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts +SYN-1014 : Optimize round 1 +SYN-1019 : Optimized 228 mux instances. +SYN-1020 : Optimized 2 distributor mux. +SYN-1016 : Merged 3 instances. +SYN-1015 : Optimize round 1, 279 better +SYN-1014 : Optimize round 2 +SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts +SYN-1015 : Optimize round 2, 2 better +SYN-1014 : Optimize round 3 +SYN-1015 : Optimize round 3, 0 better +RUN-1003 : finish command "optimize_rtl" in 18.914664s wall, 16.640625s user + 2.218750s system = 18.859375s CPU (99.7%) + +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB +RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +Gate Statistics +#Basic gates 14015 + #and 2480 + #nand 0 + #or 1078 + #nor 0 + #xor 207 + #xnor 0 + #buf 0 + #not 469 + #bufif1 5 + #MX21 618 + #FADD 0 + #DFF 9152 + #LATCH 6 +#MACRO_ADD 497 +#MACRO_EQ 225 +#MACRO_MULT 4 +#MACRO_MUX 4813 +#MACRO_OTHERS 73 + +Report Hierarchy Area: ++----------------------------------------------------------------------------+ +|Instance |Module |gates |seq |macros | ++----------------------------------------------------------------------------+ +|top |huagao_mipi_top |4857 |9158 |799 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | +| U_crc16_24b |crc16_24b |67 |16 |0 | +| U_ecc_gen |ecc_gen |37 |6 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 | +| exdev_ctl_a |exdev_ctl |161 |559 |45 | +| u_ADconfig |AD_config |84 |138 |22 | +| u_gen_sp |gen_sp |76 |104 |19 | +| exdev_ctl_b |exdev_ctl |158 |546 |41 | +| u_ADconfig |AD_config |81 |125 |18 | +| u_gen_sp |gen_sp |76 |104 |19 | +| sampling_fe_a |sampling_fe |1847 |1919 |269 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |40 |147 |10 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort |1803 |1737 |258 | +| rddpram_ctl |rddpram_ctl |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer |data_prebuffer |1548 |1391 |118 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram |121 |164 |32 | +| read_ram_addr |read_ram_addr |69 |127 |22 | +| read_ram_data |read_ram_data |50 |32 |10 | +| mux_i |mux_i |0 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 | +| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | +| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_ad_sampling |ad_sampling |39 |147 |9 | +| u0_soft_n |cdc_sync |2 |5 |0 | +| u_sort |sort_rev |1765 |1754 |258 | +| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_rdsoft_n |cdc_sync |2 |5 |0 | +| u0_wrsoft_n |cdc_sync |2 |5 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 | +| channelPart |channel_part_8478 |865 |144 |8 | +| fifo_adc |fifo_adc |112 |41 |4 | +| ram_switch |ram_switch |60 |1023 |52 | +| adc_addr_gen |adc_addr_gen |25 |115 |9 | +| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 | +| insert |insert |5 |692 |37 | +| mapping |mapping |0 |0 |0 | +| ram_switch_state |ram_switch_state |27 |216 |4 | +| mux_addr |mux_e |0 |0 |0 | +| mux_data |mux_e |0 |0 |0 | +| mux_valid |mux_e |0 |0 |0 | +| read_ram_i |read_ram_rev |90 |181 |33 | +| read_ram_addr |read_ram_addr_rev |56 |139 |23 | +|...... |...... |- |- |- | ++----------------------------------------------------------------------------+ + +RUN-1002 : start command "export_db hg_anlogic_rtl.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.112412s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (155.9%) + +RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 404 MB +RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " +RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833. +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 " +RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417. +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]" +RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" +RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 " +RUN-1002 : start command "get_ports a_lvds_clk_p" +RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports b_lvds_clk_p" +RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]" +RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 " +RUN-1002 : start command "get_ports clock_source" +RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" +RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " +RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]" +RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]" +RUN-1002 : start command "set_false_path -from -to " +RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area" +RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic +RUN-1001 : Print Global Property +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : --------------------------------------------------------------- +RUN-1001 : message | standard | standard | +RUN-1001 : mixed_pack_place_flow | on | on | +RUN-1001 : qor_monitor | off | off | +RUN-1001 : syn_ip_flow | off | off | +RUN-1001 : thread | auto | auto | +RUN-1001 : --------------------------------------------------------------- +RUN-1002 : start command "set_param gate opt_area low" +RUN-1002 : start command "set_param gate opt_timing high" +RUN-1001 : Print Gate Property +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : Parameters | Settings | Default Values | Note +RUN-1001 : ------------------------------------------------------------------ +RUN-1001 : cascade_dsp | off | off | +RUN-1001 : cascade_eram | off | off | +RUN-1001 : gate_sim_model | off | off | +RUN-1001 : map_sim_model | off | off | +RUN-1001 : map_strategy | 1 | 1 | +RUN-1001 : opt_area | low | medium | * +RUN-1001 : opt_timing | high | auto | * +RUN-1001 : pack_effort | medium | medium | +RUN-1001 : pack_lslice_ripple | on | on | +RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 | +RUN-1001 : pack_seq_in_io | auto | auto | +RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 | +RUN-1001 : report | standard | standard | +RUN-1001 : retiming | off | off | +RUN-1001 : ------------------------------------------------------------------ +SYN-2001 : Map 61 IOs to PADs +SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts +RUN-1002 : start command "update_pll_param -module huagao_mipi_top" +SYN-2501 : Processed 0 LOGIC_BUF instances. +SYN-2501 : 3 BUFG to GCLK +SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo" +SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst" +SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" +SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif" +SYN-2542 : Parsing MIF init file +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2541 : Write 1024x8, read 1024x8. +SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 +SYN-2571 : Map 4 macro multiplier +SYN-2571 : Optimize after map_dsp, round 1 +SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts +SYN-1016 : Merged 11 instances. +SYN-2571 : Optimize after map_dsp, round 1, 1181 better +SYN-2571 : Optimize after map_dsp, round 2 +SYN-2571 : Optimize after map_dsp, round 2, 0 better +SYN-1001 : Throwback 317 control mux instances +SYN-1001 : Convert 12 adder +SYN-2501 : Optimize round 1 +SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts +SYN-1016 : Merged 396 instances. +SYN-2501 : Optimize round 1, 1774 better +SYN-2501 : Optimize round 2 +SYN-2501 : Optimize round 2, 0 better +SYN-2501 : Map 498 macro adder +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. +SYN-2501 : Inferred 22 ROM instances +SYN-1019 : Optimized 9690 mux instances. +SYN-1016 : Merged 12105 instances. +SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts +RUN-1002 : start command "start_timer -prepack" +TMR-2505 : Start building timing graph for model huagao_mipi_top. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011. +TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. +TMR-2501 : Timing graph initialized successfully. +RUN-1003 : finish command "start_timer -prepack" in 1.289776s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.3%) + +RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB +TMR-2503 : Start to update net delay, extr mode = 2. +TMR-2504 : Update delay of 36686 nets completely. +TMR-2502 : Annotate delay completely, extr mode = 2. +TMR-3001 : Initiate 12 clocks from SDC. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. +TMR-3003 : Constraints initiated successfully. +TMR-3501 : Forward propagation: start to calculate arrival time... +TMR-3502 : Backward propagation: start to calculate required time... +TMR-3503 : Timing propagation completes. +SYN-3001 : Running gate level optimization. +SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15) +SYN-2551 : Post LUT mapping optimization. +SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04) +SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%. +SYN-3001 : Mapper removed 2 lut buffers +RUN-1002 : start command "report_area -file hg_anlogic_gate.area" +RUN-1001 : standard +***Report Model: huagao_mipi_top Device: EG4D20EG176*** + +IO Statistics +#IO 61 + #input 21 + #output 40 + #inout 0 + +LUT Statistics +#Total_luts 9912 + #lut4 5066 + #lut5 2291 + #lut6 0 + #lut5_mx41 0 + #lut4_alu1b 2555 + +Utilization Statistics +#lut 9912 out of 19600 50.57% +#reg 9232 out of 19600 47.10% +#le 0 +#dsp 3 out of 29 10.34% +#bram 54 out of 64 84.38% + #bram9k 50 + #fifo9k 4 +#bram32k 4 out of 16 25.00% +#dram 16 +#pad 75 out of 130 57.69% + #ireg 13 + #oreg 21 + #treg 0 +#pll 3 out of 4 75.00% + +Report Hierarchy Area: ++-------------------------------------------------------------------------------------------------+ +|Instance |Module |lut |ripple |seq |bram |dsp | ++-------------------------------------------------------------------------------------------------+ +|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 | +| U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | +| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | +| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 | +| u_ADconfig |AD_config |102 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | +| u_gen_sp |gen_sp |126 |185 |104 |0 |0 | +| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort |2207 |691 |1737 |25 |0 | +| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |0 | +| ram_switch |ram_switch |1444 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 | +| read_ram_i |read_ram |189 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |27 |13 |32 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | +| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_sort |sort_rev |2227 |704 |1754 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 | +| channelPart |channel_part_8478 |146 |11 |144 |0 |0 | +| fifo_adc |fifo_adc |51 |24 |41 |0 |1 | +| ram_switch |ram_switch |1443 |422 |1023 |0 |0 | +| adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | +| insert |insert |265 |323 |692 |0 |0 | +| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 | +|...... |...... |- |- |- |- |- | ++-------------------------------------------------------------------------------------------------+ + +SYN-1001 : Packing model "huagao_mipi_top" ... +SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks +SYN-1014 : Optimize round 1 +SYN-1015 : Optimize round 1, 0 better +SYN-4002 : Packing 9232 DFF/LATCH to SEQ ... +SYN-4009 : Pack 83 carry chain into lslice +SYN-4007 : Packing 1278 adder to BLE ... +SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. +SYN-4007 : Packing 0 gate4 to BLE ... +SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. +SYN-4012 : Packed 0 FxMUX +SYN-4013 : Packed 16 DRAM and 4 SEQ. +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.555008s wall, 58.328125s user + 0.187500s system = 58.515625s CPU (99.9%) + +RUN-1004 : used memory is 399 MB, reserved memory is 388 MB, peak memory is 704 MB +RUN-1002 : start command "legalize_phy_inst" +SYN-1011 : Flatten model huagao_mipi_top +SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" +RUN-1002 : start command "export_db hg_anlogic_gate.db" +RUN-1001 : Exported / +RUN-1001 : Exported flow parameters +RUN-1001 : Exported libs +RUN-1001 : Exported entities +RUN-1001 : Exported ports +RUN-1001 : Exported pins +RUN-1001 : Exported instances +RUN-1001 : Exported nets +RUN-1001 : Exported buses +RUN-1001 : Exported models +RUN-1001 : Exported congestions +RUN-1001 : Exported violations +RUN-1001 : Exported timing constraints +RUN-1001 : Exported IO constraints +RUN-1001 : Exported Inst constraints +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568878s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (173.3%) + +RUN-1004 : used memory is 406 MB, reserved memory is 382 MB, peak memory is 704 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_163838.log" diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f index 1f12086..8d0b355 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f index 1f12086..8d0b355 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f index 1f12086..8d0b355 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin new file mode 100644 index 0000000..029042c Binary files /dev/null and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bin differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit index 34ba510..cc54c36 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj index 8657074..eb4b154 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj @@ -1,5 +1,5 @@ - + UTF-8 5.6.71036 diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf index 7cc7e00..35c864a 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin deleted file mode 100644 index 32571c4..0000000 Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin and /dev/null differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area index 5fa516d..1461991 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area @@ -8,12 +8,12 @@ IO Statistics #inout 0 Utilization Statistics -#lut 10421 out of 19600 53.17% -#reg 9955 out of 19600 50.79% -#le 13076 - #lut only 3121 out of 13076 23.87% - #reg only 2655 out of 13076 20.30% - #lut® 7300 out of 13076 55.83% +#lut 10230 out of 19600 52.19% +#reg 9451 out of 19600 48.22% +#le 12649 + #lut only 3198 out of 12649 25.28% + #reg only 2419 out of 12649 19.12% + #lut® 7032 out of 12649 55.59% #dsp 3 out of 29 10.34% #bram 54 out of 64 84.38% #bram9k 50 @@ -21,24 +21,24 @@ Utilization Statistics #bram32k 4 out of 16 25.00% #pad 75 out of 130 57.69% #ireg 13 - #oreg 19 + #oreg 21 #treg 0 #pll 3 out of 4 75.00% #gclk 6 out of 16 37.50% Clock Resource Statistics Index ClockNet Type DriverType Driver Fanout -#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1825 -#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1432 -#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1342 -#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1235 -#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 140 -#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71 -#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70 +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1415 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 989 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70 #8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26 #9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 -#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_299.f1 3 -#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0 3 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2 #12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 #13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 #14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 @@ -77,7 +77,7 @@ Detailed IO Report clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE onoff_in INPUT P141 LVCMOS33 N/A N/A NONE - paper_in INPUT P16 LVCMOS25 N/A N/A NONE + paper_in INPUT P17 LVCMOS25 N/A N/A NONE rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L @@ -103,7 +103,7 @@ Detailed IO Report a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG - a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE @@ -113,114 +113,59 @@ Detailed IO Report debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG - debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE - debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG + debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE - fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG - onoff_out OUTPUT P111 LVCMOS25 8 N/A NONE + onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE paper_out OUTPUT P106 LVCMOS25 8 N/A NONE - scan_out OUTPUT P84 LVCMOS25 8 N/A NONE - sys_initial_done OUTPUT P71 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG Report Hierarchy Area: +---------------------------------------------------------------------------------------------------------+ |Instance |Module |le |lut |ripple |seq |bram |dsp | +---------------------------------------------------------------------------------------------------------+ -|top |huagao_mipi_top |13076 |9394 |1027 |9987 |58 |3 | -| U_rgb_to_csi_pakage |rgb_to_csi_pakage |544 |438 |23 |443 |4 |1 | -| U_fifo_w32_d8192 |fifo_w32_d8192 |100 |80 |4 |87 |4 |0 | -| U_crc16_24b |crc16_24b |35 |35 |0 |24 |0 |0 | -| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 | -| exdev_ctl_a |exdev_ctl |779 |386 |96 |580 |0 |0 | -| u_ADconfig |AD_config |204 |138 |25 |151 |0 |0 | -| u_gen_sp |gen_sp |263 |160 |71 |117 |0 |0 | -| exdev_ctl_b |exdev_ctl |739 |378 |96 |562 |0 |0 | -| u_ADconfig |AD_config |167 |122 |25 |125 |0 |0 | -| u_gen_sp |gen_sp |255 |147 |71 |120 |0 |0 | -| sampling_fe_a |sampling_fe |3214 |2625 |306 |2077 |25 |0 | -| u0_soft_n |cdc_sync |7 |2 |0 |7 |0 |0 | -| u_ad_sampling |ad_sampling |184 |145 |17 |136 |0 |0 | -| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | -| u_sort |sort |2998 |2468 |289 |1909 |25 |0 | -| rddpram_ctl |rddpram_ctl |5 |4 |0 |5 |0 |0 | -| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | -| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 | -| u0_wrsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | -| u_data_prebuffer |data_prebuffer |2596 |2148 |253 |1582 |22 |0 | -| channelPart |channel_part_8478 |160 |155 |3 |126 |0 |0 | -| fifo_adc |fifo_adc |56 |47 |9 |39 |0 |0 | -| ram_switch |ram_switch |2024 |1637 |197 |1169 |0 |0 | -| adc_addr_gen |adc_addr_gen |255 |227 |27 |113 |0 |0 | -| [0]$ch_addr_gen |ch_addr_gen |11 |7 |3 |5 |0 |0 | -| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 | -| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 | -| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 | -| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 | -| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 | -| [6]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | -| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 | -| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |10 |0 |0 | -| insert |insert |987 |628 |170 |682 |0 |0 | -| ram_switch_state |ram_switch_state |782 |782 |0 |374 |0 |0 | -| read_ram_i |read_ram |313 |266 |44 |209 |0 |0 | -| read_ram_addr |read_ram_addr |251 |211 |40 |166 |0 |0 | -| read_ram_data |read_ram_data |57 |51 |4 |38 |0 |0 | -| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | -| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u_transfer_300_to_200 |transfer_300_to_200 |326 |252 |36 |271 |3 |0 | -| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 | -| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | -| sampling_fe_b |sampling_fe_rev |3165 |2462 |349 |2109 |25 |1 | -| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | -| u_ad_sampling |ad_sampling |187 |105 |17 |148 |0 |0 | -| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 | -| u_sort |sort_rev |2946 |2342 |332 |1929 |25 |1 | -| rddpram_ctl |rddpram_ctl_rev |6 |5 |0 |6 |0 |0 | -| u0_rdsoft_n |cdc_sync |6 |5 |0 |6 |0 |0 | -| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 | -| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | -| u_data_prebuffer_rev |data_prebuffer_rev |2485 |1993 |290 |1576 |22 |1 | -| channelPart |channel_part_8478 |275 |272 |3 |151 |0 |0 | -| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 | -| ram_switch |ram_switch |1756 |1391 |197 |1140 |0 |0 | -| adc_addr_gen |adc_addr_gen |198 |169 |27 |122 |0 |0 | -| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |9 |0 |0 | -| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |18 |0 |0 | -| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 | -| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |18 |0 |0 | -| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 | -| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 | -| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 | -| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 | -| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 | -| insert |insert |1012 |680 |170 |674 |0 |0 | -| ram_switch_state |ram_switch_state |546 |542 |0 |344 |0 |0 | -| read_ram_i |read_ram_rev |363 |258 |81 |213 |0 |0 | -| read_ram_addr |read_ram_addr_rev |298 |218 |73 |166 |0 |0 | -| read_ram_data |read_ram_data_rev |65 |40 |8 |47 |0 |0 | +|top |huagao_mipi_top |12649 |9203 |1027 |9485 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |559 |475 |23 |441 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |52 |52 |0 |23 |0 |0 | +| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 | +| exdev_ctl_a |exdev_ctl |761 |324 |96 |573 |0 |0 | +| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 | +| u_gen_sp |gen_sp |265 |152 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |766 |382 |96 |571 |0 |0 | +| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 | +| u_gen_sp |gen_sp |262 |156 |71 |119 |0 |0 | +| sampling_fe_a |sampling_fe |2990 |2397 |306 |2064 |25 |0 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort |2777 |2276 |289 |1889 |25 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_data_prebuffer |data_prebuffer |2369 |2001 |253 |1552 |22 |0 | +| channelPart |channel_part_8478 |179 |175 |3 |146 |0 |0 | +| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 | +| ram_switch |ram_switch |1838 |1538 |197 |1145 |0 |0 | +| adc_addr_gen |adc_addr_gen |234 |206 |27 |125 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| insert |insert |955 |683 |170 |644 |0 |0 | +| ram_switch_state |ram_switch_state |649 |649 |0 |376 |0 |0 | +| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 | +| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 | +| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | @@ -243,81 +188,133 @@ Report Hierarchy Area: | u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u_transfer_300_to_200 |transfer_300_to_200 |348 |260 |42 |273 |3 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |295 |175 |36 |264 |3 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3425 |2768 |349 |2117 |25 |1 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_ad_sampling |ad_sampling |186 |118 |17 |151 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort_rev |3208 |2632 |332 |1935 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2742 |2267 |290 |1583 |22 |1 | +| channelPart |channel_part_8478 |263 |250 |3 |149 |0 |0 | +| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 | +| ram_switch |ram_switch |1999 |1658 |197 |1136 |0 |0 | +| adc_addr_gen |adc_addr_gen |221 |194 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| insert |insert |972 |659 |170 |667 |0 |0 | +| ram_switch_state |ram_switch_state |806 |805 |0 |363 |0 |0 | +| read_ram_i |read_ram_rev |376 |267 |81 |214 |0 |0 | +| read_ram_addr |read_ram_addr_rev |307 |222 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |69 |45 |8 |52 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |366 |288 |42 |281 |3 |0 | | u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 | | u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | -| scan_start_diff |scan_start_diff |26 |26 |0 |14 |0 |0 | -| u0_test_en |cdc_sync |5 |5 |0 |5 |0 |0 | -| u1_test_en |cdc_sync |5 |5 |0 |5 |0 |0 | -| u2_test_en |cdc_sync |4 |3 |0 |4 |0 |0 | -| u_O_clk_lp_n |cdc_sync |270 |209 |0 |269 |0 |0 | -| u_O_clk_lp_p |cdc_sync |285 |48 |0 |285 |0 |0 | +| scan_start_diff |scan_start_diff |21 |20 |0 |14 |0 |0 | +| u0_test_en |cdc_sync |5 |1 |0 |5 |0 |0 | +| u1_BUSY_MIPI |cdc_sync |3 |2 |0 |3 |0 |0 | +| u1_test_en |cdc_sync |1 |1 |0 |1 |0 |0 | +| u2_test_en |cdc_sync |7 |6 |0 |7 |0 |0 | +| u_O_clk_lp_n |cdc_sync |17 |17 |0 |17 |0 |0 | +| u_O_clk_lp_p |cdc_sync |12 |12 |0 |12 |0 |0 | | u_a_pclk |cdc_sync |4 |4 |0 |4 |0 |0 | -| u_a_sp_sampling |cdc_sync |6 |6 |0 |6 |0 |0 | -| u_a_sp_sampling_cam |cdc_sync |3 |3 |0 |3 |0 |0 | -| u_a_sp_sampling_last |cdc_sync |4 |4 |0 |4 |0 |0 | -| u_b_pclk |cdc_sync |2 |2 |0 |2 |0 |0 | -| u_b_sp_sampling |cdc_sync |5 |2 |0 |5 |0 |0 | -| u_b_sp_sampling_cam |cdc_sync |8 |1 |0 |8 |0 |0 | -| u_b_sp_sampling_last |cdc_sync |2 |2 |0 |2 |0 |0 | -| u_bus_top |ubus_top |1297 |953 |22 |1222 |0 |0 | -| u_local_bus_slve_cis |local_bus_slve_cis |784 |645 |22 |709 |0 |0 | -| u_uart_2dsp |uart_2dsp |87 |72 |12 |56 |0 |0 | -| u_dpi_mode |cdc_sync |8 |8 |0 |8 |0 |0 | -| u_eot |cdc_sync |3 |3 |0 |3 |0 |0 | -| u_lv_en_flag |cdc_sync |2 |2 |0 |2 |0 |0 | -| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |269 |213 |20 |220 |4 |0 | -| u_hs_tx_wrapper |hs_tx_wrapper |226 |170 |20 |188 |4 |0 | -| [0]$u_data_lane_wrapper |data_lane_wrapper |110 |77 |15 |85 |1 |0 | -| u_data_hs_generate |data_hs_generate |106 |73 |15 |81 |1 |0 | +| u_a_sp_sampling |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_a_sp_sampling_cam |cdc_sync |6 |5 |0 |6 |0 |0 | +| u_b_pclk |cdc_sync |5 |4 |0 |5 |0 |0 | +| u_b_sp_sampling |cdc_sync |5 |5 |0 |5 |0 |0 | +| u_b_sp_sampling_cam |cdc_sync |3 |3 |0 |3 |0 |0 | +| u_b_sp_sampling_last |cdc_sync |6 |6 |0 |6 |0 |0 | +| u_bus_top |ubus_top |1360 |952 |22 |1258 |0 |0 | +| u_local_bus_slve_cis |local_bus_slve_cis |846 |713 |22 |744 |0 |0 | +| u_uart_2dsp |uart_2dsp |135 |120 |12 |66 |0 |0 | +| u_dpi_mode |cdc_sync |9 |6 |0 |9 |0 |0 | +| u_lv_en_flag |cdc_sync |6 |6 |0 |6 |0 |0 | +| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |275 |206 |20 |224 |4 |0 | +| u_hs_tx_wrapper |hs_tx_wrapper |233 |164 |20 |195 |4 |0 | +| [0]$u_data_lane_wrapper |data_lane_wrapper |116 |85 |15 |89 |1 |0 | +| u_data_hs_generate |data_hs_generate |113 |82 |15 |86 |1 |0 | | u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 | | u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 | -| u_data_lp_generate |data_lp_generate |4 |4 |0 |4 |0 |0 | -| [1]$u_data_lane_wrapper |data_lane_wrapper |26 |15 |0 |26 |1 |0 | -| u_data_hs_generate |data_hs_generate |26 |15 |0 |26 |1 |0 | +| u_data_lp_generate |data_lp_generate |3 |3 |0 |3 |0 |0 | +| [1]$u_data_lane_wrapper |data_lane_wrapper |35 |20 |0 |35 |1 |0 | +| u_data_hs_generate |data_hs_generate |35 |20 |0 |35 |1 |0 | | u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 | | u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 | -| [2]$u_data_lane_wrapper |data_lane_wrapper |37 |32 |0 |36 |1 |0 | -| u_data_hs_generate |data_hs_generate |37 |32 |0 |36 |1 |0 | -| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |1 |1 |0 | -| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |1 |1 |0 | -| [3]$u_data_lane_wrapper |data_lane_wrapper |21 |19 |0 |19 |1 |0 | -| u_data_hs_generate |data_hs_generate |21 |19 |0 |19 |1 |0 | -| u_dphy_tx_fifo |dphy_tx_fifo |2 |2 |0 |1 |1 |0 | -| u_d1024_w8_fifo |d1024_w8_fifo |2 |2 |0 |1 |1 |0 | -| u_hs_tx_controler |hs_tx_controler |24 |19 |5 |14 |0 |0 | +| [2]$u_data_lane_wrapper |data_lane_wrapper |29 |13 |0 |29 |1 |0 | +| u_data_hs_generate |data_hs_generate |29 |13 |0 |29 |1 |0 | +| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 | +| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 | +| [3]$u_data_lane_wrapper |data_lane_wrapper |20 |18 |0 |20 |1 |0 | +| u_data_hs_generate |data_hs_generate |20 |18 |0 |20 |1 |0 | +| u_dphy_tx_fifo |dphy_tx_fifo |0 |0 |0 |0 |1 |0 | +| u_d1024_w8_fifo |d1024_w8_fifo |0 |0 |0 |0 |1 |0 | +| u_hs_tx_controler |hs_tx_controler |25 |20 |5 |14 |0 |0 | | u_clk_lane_wrapper |clk_lane_wrapper |8 |8 |0 |8 |0 |0 | -| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 | | u_clk_hs_generate |clk_hs_generate |4 |4 |0 |4 |0 |0 | -| u_mipi_eot_min |cdc_sync |60 |57 |0 |60 |0 |0 | -| u_mipi_sot_min |cdc_sync |58 |55 |0 |58 |0 |0 | -| u_pic_cnt |cdc_sync |117 |58 |0 |117 |0 |0 | -| u_pixel_cdc |pixel_cdc |697 |517 |0 |695 |0 |1 | -| u_clk_cis_frame_num |cdc_sync |73 |62 |0 |73 |0 |0 | -| u_clk_cis_pixel_y |cdc_sync |77 |73 |0 |75 |0 |0 | -| u_clk_mipi_pixel_y |cdc_sync |73 |67 |0 |73 |0 |0 | -| u_clka_cis_total_num |cdc_sync |100 |94 |0 |100 |0 |0 | -| u_clka_mipi_total_num |cdc_sync |101 |60 |0 |101 |0 |0 | -| u_clkb_cis_total_num |cdc_sync |108 |46 |0 |108 |0 |0 | -| u_clkb_mipi_total_num |cdc_sync |98 |66 |0 |98 |0 |0 | +| u_clk_lp_generate |clk_lp_generate |4 |4 |0 |4 |0 |0 | +| u_mipi_eot_min |cdc_sync |65 |58 |0 |65 |0 |0 | +| u_mipi_sot_min |cdc_sync |58 |56 |0 |58 |0 |0 | +| u_pic_cnt |cdc_sync |115 |72 |0 |115 |0 |0 | +| u_pixel_cdc |pixel_cdc |675 |580 |0 |672 |0 |1 | +| u_clk_cis_frame_num |cdc_sync |68 |60 |0 |68 |0 |0 | +| u_clk_cis_pixel_y |cdc_sync |65 |59 |0 |65 |0 |0 | +| u_clk_mipi_pixel_y |cdc_sync |74 |73 |0 |72 |0 |0 | +| u_clka_cis_total_num |cdc_sync |94 |83 |0 |94 |0 |0 | +| u_clka_mipi_total_num |cdc_sync |102 |88 |0 |102 |0 |0 | +| u_clkb_cis_total_num |cdc_sync |100 |85 |0 |99 |0 |0 | +| u_clkb_mipi_total_num |cdc_sync |100 |77 |0 |100 |0 |0 | | u_pll |pll |0 |0 |0 |0 |0 |0 | | u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 | -| u_softrst_done |cdc_sync |5 |5 |0 |5 |0 |0 | -| ua_lvds_rx |lvds_rx |278 |194 |19 |198 |0 |0 | -| ub_lvds_rx |lvds_rx |288 |192 |19 |209 |0 |0 | +| u_softrst_done |cdc_sync |4 |4 |0 |4 |0 |0 | +| ua_lvds_rx |lvds_rx |278 |218 |19 |197 |0 |0 | +| ub_lvds_rx |lvds_rx |287 |192 |19 |207 |0 |0 | | uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 |0 | +---------------------------------------------------------------------------------------------------------+ DataNet Average Fanout: - Index Fanout Nets - #1 1 10415 - #2 2 3902 - #3 3 1365 - #4 4 552 - #5 5-10 1241 - #6 11-50 592 - #7 51-100 26 - #8 >500 1 - Average 2.89 + Index Fanout Nets + #1 1 9801 + #2 2 3950 + #3 3 1453 + #4 4 623 + #5 5-10 1031 + #6 11-50 602 + #7 51-100 22 + #8 >500 1 + Average 2.91 diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing index 78bbea1..fea5bf9 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing @@ -1,7 +1,7 @@ ========================================================================================================= Auto created by Tang Dynasty v5.6.71036 Copyright (c) 2012-2023 Anlogic Inc. -Tue Mar 12 14:54:41 2024 +Tue Mar 12 16:42:20 2024 ========================================================================================================= @@ -25,175 +25,19 @@ Minimum period is 0ns Timing constraint: clock: a_pclk Clock = a_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns -6154 endpoints analyzed totally, and 105576 paths analyzed +6178 endpoints analyzed totally, and 104162 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 12.828ns ---------------------------------------------------------------------------------------------------------- - -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 (691 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 8.005 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1] (rising edge triggered by clock a_pclk) - Clock group: a_lvds_clk_p - Process: Slow - Data Path Delay: 12.648ns (logic 6.774ns, net 5.874ns, 53% logic) - Logic Levels: 7 ( LUT5=3 ADDER=2 MULT18=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[23] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net (fanout = 1) 1.643 r 9.229 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.706 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.471 r 14.192 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0 0.732 14.924 - Arrival time 14.924 (7 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.167 22.929 - Required time 22.929 ---------------------------------------------------------------------------------------------------------- - Slack 8.005ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 8.005 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (rising edge triggered by clock a_pclk) - Clock group: a_lvds_clk_p - Process: Slow - Data Path Delay: 12.648ns (logic 6.774ns, net 5.874ns, 53% logic) - Logic Levels: 7 ( LUT5=3 ADDER=2 MULT18=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[23] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net (fanout = 1) 1.643 r 9.229 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.706 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.471 r 14.192 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0 0.732 14.924 - Arrival time 14.924 (7 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.167 22.929 - Required time 22.929 ---------------------------------------------------------------------------------------------------------- - Slack 8.005ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 8.005 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (rising edge triggered by clock a_pclk) - Clock group: a_lvds_clk_p - Process: Slow - Data Path Delay: 12.648ns (logic 6.920ns, net 5.728ns, 54% logic) - Logic Levels: 7 ( LUT5=3 ADDER=2 MULT18=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.497 r 9.083 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.471 r 14.192 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0 0.732 14.924 - Arrival time 14.924 (7 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.167 22.929 - Required time 22.929 ---------------------------------------------------------------------------------------------------------- - Slack 8.005ns - +Minimum period is 12.866ns --------------------------------------------------------------------------------------------------------- Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 (659 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 8.153 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) + Slack (setup check): 7.967 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 12.500ns (logic 6.774ns, net 5.726ns, 54% logic) + Data Path Delay: 12.686ns (logic 6.921ns, net 5.765ns, 54% logic) Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) Point Type Incr Path Info @@ -202,25 +46,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[23] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net (fanout = 1) 1.643 r 9.229 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.706 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.323 r 14.044 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.776 - Arrival time 14.776 (7 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.282 r 14.230 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.962 + Arrival time 14.962 (7 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 @@ -234,16 +84,72 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( clock recovergence pessimism 0.167 22.929 Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 8.153ns + Slack 7.967ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 8.153 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) + Slack (setup check): 7.967 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (rising edge triggered by clock a_pclk) + Clock group: a_lvds_clk_p + Process: Slow + Data Path Delay: 12.686ns (logic 6.921ns, net 5.765ns, 54% logic) + Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.282 r 14.230 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.962 + Arrival time 14.962 (7 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 +--------------------------------------------------------------------------------------------------------- + Slack 7.967ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 7.967 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 12.500ns (logic 6.774ns, net 5.726ns, 54% logic) + Data Path Delay: 12.686ns (logic 6.921ns, net 5.765ns, 54% logic) Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) Point Type Incr Path Info @@ -252,25 +158,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[23] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net (fanout = 1) 1.643 r 9.229 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.706 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.323 r 14.044 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.776 - Arrival time 14.776 (7 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.282 r 14.230 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.962 + Arrival time 14.962 (7 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 @@ -284,16 +196,18 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( clock recovergence pessimism 0.167 22.929 Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 8.153ns + Slack 7.967ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 8.153 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (rising edge triggered by clock a_pclk) +Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (691 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 7.968 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 12.500ns (logic 6.920ns, net 5.580ns, 55% logic) + Data Path Delay: 12.685ns (logic 6.921ns, net 5.764ns, 54% logic) Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) Point Type Incr Path Info @@ -302,35 +216,37 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.601 r 4.023 ../../../../hg_mp/fe/prebuffer.v(109) - U_rgb_to_csi_pakage/mult0_syn_4.p[19] cell (MULT18) 3.563 r 7.586 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.497 r 9.083 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 9.789 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.789 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.862 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.862 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.935 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 10.290 - ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.664 r 10.954 - ua_lvds_rx/reg8_syn_170.f[0] cell (LUT5) 0.424 r 11.378 - u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net (fanout = 1) 0.757 r 12.135 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[1] cell (LUT5) 0.424 r 12.559 - u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.738 r 13.297 ../../../../hg_mp/fe/fifo_adc.v(36) - u_pic_cnt/reg1_syn_370.f[0] cell (LUT5) 0.424 r 13.721 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 0.323 r 14.044 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 path2reg0 (LUT5) 0.732 14.776 - Arrival time 14.776 (7 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.281 r 14.229 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.961 + Arrival time 14.961 (7 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- cell setup -0.116 22.762 @@ -338,153 +254,275 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 ( clock recovergence pessimism 0.167 22.929 Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 8.153ns + Slack 7.968ns --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 (12 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 12.557 ns - Start Point: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1] (rising edge triggered by clock a_pclk) + Slack (setup check): 7.968 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 7.929ns (logic 2.338ns, net 5.591ns, 29% logic) - Logic Levels: 6 ( LUT4=5 LUT3=1 ) + Data Path Delay: 12.685ns (logic 6.921ns, net 5.764ns, 54% logic) + Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net (fanout = 36) 1.618 r 4.040 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56) - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0] cell (LUT3) 0.251 r 4.291 - reg14_syn_50.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net (fanout = 52) 1.283 r 5.574 ../../../../hg_mp/fe/ram_switch_state.v(47) - reg14_syn_50.f[0] cell (LUT4) 0.408 r 5.982 - ua_lvds_rx/reg8_syn_184.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5086) net (fanout = 5) 0.901 r 6.883 ../../../../hg_mp/fe/mux_e.v(24) - ua_lvds_rx/reg8_syn_184.f[0] cell (LUT4) 0.408 r 7.291 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_10) net (fanout = 1) 0.594 r 7.885 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.f[1] cell (LUT4) 0.251 r 8.136 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_12) net (fanout = 3) 0.601 r 8.737 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.f[0] cell (LUT4) 0.408 r 9.145 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[50]_syn_2) net (fanout = 1) 0.594 r 9.739 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4) 0.466 10.205 - Arrival time 10.205 (6 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.281 r 14.229 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.961 + Arrival time 14.961 (7 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- cell setup -0.116 22.762 clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.000 22.762 - Required time 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 12.557ns + Slack 7.968ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 13.869 ns - Start Point: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (rising edge triggered by clock a_pclk) + Slack (setup check): 7.968 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 6.617ns (logic 2.126ns, net 4.491ns, 32% logic) - Logic Levels: 5 ( LUT4=4 LUT3=1 ) + Data Path Delay: 12.685ns (logic 6.921ns, net 5.764ns, 54% logic) + Logic Levels: 7 ( LUT5=4 ADDER=2 MULT18=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net (fanout = 36) 1.618 r 4.040 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56) - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0] cell (LUT3) 0.251 r 4.291 - reg14_syn_50.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net (fanout = 52) 1.283 r 5.574 ../../../../hg_mp/fe/ram_switch_state.v(47) - reg14_syn_50.f[1] cell (LUT4) 0.408 r 5.982 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3436) net (fanout = 5) 0.664 r 6.646 ../../../../hg_mp/fe/mux_e.v(24) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[0] cell (LUT4) 0.424 r 7.070 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20) net (fanout = 1) 0.456 r 7.526 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[1] cell (LUT4) 0.348 r 7.874 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22) net (fanout = 3) 0.470 r 8.344 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4) 0.549 8.893 - Arrival time 8.893 (5 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net (fanout = 4) 1.618 r 4.040 ../../../../hg_mp/fe/prebuffer.v(109) + U_rgb_to_csi_pakage/mult0_syn_4.p[18] cell (MULT18) 3.563 r 7.603 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 1.011 r 8.614 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 9.241 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 9.314 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 9.387 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 9.460 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 9.815 + u_bus_top/reg0_syn_156.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.790 r 10.605 + u_bus_top/reg0_syn_156.f[0] cell (LUT5) 0.424 r 11.029 + u_bus_top/reg0_syn_158.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233) net (fanout = 1) 0.608 r 11.637 ../../../../hg_mp/fe/fifo_adc.v(36) + u_bus_top/reg0_syn_158.f[0] cell (LUT5) 0.424 r 12.061 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net (fanout = 1) 0.456 r 12.517 ../../../../hg_mp/fe/fifo_adc.v(36) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.f[0] cell (LUT5) 0.431 r 12.948 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net (fanout = 4) 1.281 r 14.229 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 14.961 + Arrival time 14.961 (7 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- cell setup -0.116 22.762 clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.000 22.762 - Required time 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 13.869ns + Slack 7.968ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 14.080 ns - Start Point: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (rising edge triggered by clock a_pclk) +Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 (85 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 11.979 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 6.406ns (logic 2.133ns, net 4.273ns, 33% logic) - Logic Levels: 5 ( LUT4=4 LUT3=1 ) + Data Path Delay: 8.674ns (logic 2.428ns, net 6.246ns, 27% logic) + Logic Levels: 6 ( LUT4=3 LUT5=2 LUT2=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0] clk2q 0.146 r 2.422 - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net (fanout = 36) 1.618 r 4.040 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56) - U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0] cell (LUT3) 0.251 r 4.291 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net (fanout = 52) 1.091 r 5.382 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.f[1] cell (LUT4) 0.408 r 5.790 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4536) net (fanout = 5) 0.638 r 6.428 ../../../../hg_mp/fe/mux_e.v(24) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[0] cell (LUT4) 0.431 r 6.859 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20) net (fanout = 1) 0.456 r 7.315 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[1] cell (LUT4) 0.348 r 7.663 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22) net (fanout = 3) 0.470 r 8.133 ../../../../hg_mp/fe/ram_switch_state.v(47) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4) 0.549 8.682 - Arrival time 8.682 (5 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.q[1] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[4]_syn_19_syn_2.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0]) net (fanout = 88) 2.358 r 4.780 ../../../../hg_mp/fe/ram_switch.v(33) + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[4]_syn_19_syn_2.f[0] cell (LUT2) 0.205 r 4.985 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_34) net (fanout = 34) 0.771 r 5.756 ../../../../hg_mp/fe/ram_switch_state.v(64) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.f[1] cell (LUT5) 0.431 r 6.187 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471) net (fanout = 5) 0.987 r 7.174 ../../../../hg_mp/fe/mux_e.v(24) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.f[1] cell (LUT5) 0.424 r 7.598 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4) net (fanout = 1) 0.911 r 8.509 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.f[1] cell (LUT4) 0.348 r 8.857 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6) net (fanout = 3) 0.625 r 9.482 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.f[1] cell (LUT4) 0.408 r 9.890 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6) net (fanout = 1) 0.594 r 10.484 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 path2reg1 (LUT4) 0.466 10.950 + Arrival time 10.950 (6 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- cell setup -0.116 22.762 clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.000 22.762 - Required time 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 --------------------------------------------------------------------------------------------------------- - Slack 14.080ns + Slack 11.979ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 12.328 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (rising edge triggered by clock a_pclk) + Clock group: a_lvds_clk_p + Process: Slow + Data Path Delay: 8.325ns (logic 2.647ns, net 5.678ns, 31% logic) + Logic Levels: 6 ( LUT4=3 LUT5=2 LUT3=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.q[0] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net (fanout = 89) 1.650 r 4.072 ../../../../hg_mp/fe/ram_switch.v(33) + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.f[0] cell (LUT3) 0.431 r 4.503 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_35) net (fanout = 39) 0.911 r 5.414 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.f[1] cell (LUT5) 0.424 r 5.838 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471) net (fanout = 5) 0.987 r 6.825 ../../../../hg_mp/fe/mux_e.v(24) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.f[1] cell (LUT5) 0.424 r 7.249 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4) net (fanout = 1) 0.911 r 8.160 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.f[1] cell (LUT4) 0.348 r 8.508 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6) net (fanout = 3) 0.625 r 9.133 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.f[1] cell (LUT4) 0.408 r 9.541 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6) net (fanout = 1) 0.594 r 10.135 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 path2reg1 (LUT4) 0.466 10.601 + Arrival time 10.601 (6 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 +--------------------------------------------------------------------------------------------------------- + Slack 12.328ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 12.623 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (rising edge triggered by clock a_pclk) + Clock group: a_lvds_clk_p + Process: Slow + Data Path Delay: 8.030ns (logic 2.478ns, net 5.552ns, 30% logic) + Logic Levels: 6 ( LUT4=3 LUT5=2 LUT3=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.q[1] clk2q 0.146 r 2.422 + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.d[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0]) net (fanout = 88) 1.524 r 3.946 ../../../../hg_mp/fe/ram_switch.v(33) + U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.f[0] cell (LUT3) 0.262 r 4.208 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_35) net (fanout = 39) 0.911 r 5.119 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.f[1] cell (LUT5) 0.424 r 5.543 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471) net (fanout = 5) 0.987 r 6.530 ../../../../hg_mp/fe/mux_e.v(24) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.f[1] cell (LUT5) 0.424 r 6.954 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4) net (fanout = 1) 0.911 r 7.865 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.f[1] cell (LUT4) 0.348 r 8.213 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6) net (fanout = 3) 0.625 r 8.838 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.f[1] cell (LUT4) 0.408 r 9.246 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6) net (fanout = 1) 0.594 r 9.840 ../../../../hg_mp/fe/ram_switch_state.v(47) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 path2reg1 (LUT4) 0.466 10.306 + Arrival time 10.306 (6 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.clk (u_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.167 22.929 + Required time 22.929 +--------------------------------------------------------------------------------------------------------- + Slack 12.623ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 (8 paths) +Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 (10 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.080 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7] (rising edge triggered by clock a_pclk) + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_627.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[8] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic) @@ -496,19 +534,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_627.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.q[0] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[71]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer.v(329) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB) 0.000 2.263 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_627.q[1] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[8] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[55]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.263 Arrival time 2.263 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -520,12 +558,12 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.251 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk) + Slack (hold check): 0.195 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[4] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast - Data Path Delay: 0.496ns (logic 0.109ns, net 0.387ns, 21% logic) + Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic) Logic Levels: 1 ( EMB=1 ) Point Type Incr Path Info @@ -534,19 +572,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.q[1] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[67]) net (fanout = 2) 0.387 r 2.434 ../../../../hg_mp/fe/prebuffer.v(329) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB) 0.000 2.434 - Arrival time 2.434 (1 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.q[0] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[4] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[51]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.378 + Arrival time 2.378 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -554,16 +592,16 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s clock recovergence pessimism -0.147 2.183 Required time 2.183 --------------------------------------------------------------------------------------------------------- - Slack 0.251ns + Slack 0.195ns --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.336 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4] (rising edge triggered by clock a_pclk) + Slack (hold check): 0.205 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[6] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast - Data Path Delay: 0.581ns (logic 0.109ns, net 0.472ns, 18% logic) + Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic) Logic Levels: 1 ( EMB=1 ) Point Type Incr Path Info @@ -572,19 +610,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.q[0] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[68]) net (fanout = 2) 0.472 r 2.519 ../../../../hg_mp/fe/prebuffer.v(329) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB) 0.000 2.519 - Arrival time 2.519 (1 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.q[1] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[6] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[53]) net (fanout = 2) 0.341 r 2.388 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB) 0.000 2.388 + Arrival time 2.388 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -592,53 +630,15 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_s clock recovergence pessimism -0.147 2.183 Required time 2.183 --------------------------------------------------------------------------------------------------------- - Slack 0.336ns + Slack 0.205ns --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 (10 paths) +Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 (10 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.089 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11] (rising edge triggered by clock a_pclk) - Clock group: a_lvds_clk_p - Process: Fast - Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic) - Logic Levels: 1 ( EMB=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.q[0] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[18]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer.v(331) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB) 0.000 2.272 - Arrival time 2.272 (1 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.200 2.330 - clock uncertainty 0.000 2.330 - clock recovergence pessimism -0.147 2.183 - Required time 2.183 ---------------------------------------------------------------------------------------------------------- - Slack 0.089ns - ---------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.130 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7] (rising edge triggered by clock a_pclk) + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[6] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast Data Path Delay: 0.375ns (logic 0.109ns, net 0.266ns, 29% logic) @@ -650,19 +650,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_s u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.q[1] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[14]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer.v(331) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB) 0.000 2.313 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.q[1] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[6] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[13]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.313 Arrival time 2.313 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -674,12 +674,12 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_s --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.234 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12] (rising edge triggered by clock a_pclk) + Slack (hold check): 0.246 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_data_tmp[7]_syn_8.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[8] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast - Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic) + Data Path Delay: 0.491ns (logic 0.109ns, net 0.382ns, 22% logic) Logic Levels: 1 ( EMB=1 ) Point Type Incr Path Info @@ -688,19 +688,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_s u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_data_tmp[7]_syn_8.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.q[0] clk2q 0.109 r 2.047 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[19]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer.v(331) - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB) 0.000 2.417 - Arrival time 2.417 (1 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_data_tmp[7]_syn_8.q[0] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[8] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[15]) net (fanout = 2) 0.382 r 2.429 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.429 + Arrival time 2.429 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -708,15 +708,53 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_s clock recovergence pessimism -0.147 2.183 Required time 2.183 --------------------------------------------------------------------------------------------------------- - Slack 0.234ns + Slack 0.246ns --------------------------------------------------------------------------------------------------------- -Paths for end point u0_test_en/reg0_syn_26 (1 paths) + Slack (hold check): 0.336 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk (rising edge triggered by clock a_pclk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[4] (rising edge triggered by clock a_pclk) + Clock group: a_lvds_clk_p + Process: Fast + Data Path Delay: 0.581ns (logic 0.109ns, net 0.472ns, 18% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk (u_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.q[0] clk2q 0.109 r 2.047 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[4] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[11]) net (fanout = 2) 0.472 r 2.519 ../../../../hg_mp/fe/prebuffer.v(331) + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB) 0.000 2.519 + Arrival time 2.519 (1 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.336ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point u0_test_en/reg0_syn_16 (1 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.167 ns - Start Point: u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk (rising edge triggered by clock clk_adc) - End Point: u0_test_en/reg0_syn_26.mi[0] (rising edge triggered by clock a_pclk) + Start Point: u_bus_top/u_local_bus_slve_cis/reg46_syn_230.clk (rising edge triggered by clock clk_adc) + End Point: u0_test_en/reg0_syn_16.mi[0] (rising edge triggered by clock a_pclk) Clock group: a_lvds_clk_p Process: Fast Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) @@ -726,19 +764,19 @@ Paths for end point u0_test_en/reg0_syn_26 (1 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/u_local_bus_slve_cis/reg46_syn_230.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - u_bus_top/u_local_bus_slve_cis/reg46_syn_241.q[0] clk2q 0.109 r 2.047 - u0_test_en/reg0_syn_26.mi[0] (u0_test_en/signal_from[0]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) - u0_test_en/reg0_syn_26 path2reg0 0.095 2.358 + u_bus_top/u_local_bus_slve_cis/reg46_syn_230.q[0] clk2q 0.109 r 2.047 + u0_test_en/reg0_syn_16.mi[0] (u0_test_en/signal_from[0]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) + u0_test_en/reg0_syn_16 path2reg0 0.095 2.358 Arrival time 2.358 (0 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u0_test_en/reg0_syn_26.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + u0_test_en/reg0_syn_16.clk (u_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.191 @@ -755,34 +793,34 @@ Paths for end point u0_test_en/reg0_syn_26 (1 paths) Timing constraint: clock: a_sclk Clock = a_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns -282 endpoints analyzed totally, and 698 paths analyzed +282 endpoints analyzed totally, and 706 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 1.906ns +Minimum period is 1.86ns --------------------------------------------------------------------------------------------------------- Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.046 ns - Start Point: ua_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock a_sclk) + Slack (setup check): 4.092 ns + Start Point: ua_lvds_rx/reg7_syn_36.clk (rising edge triggered by clock a_sclk) End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.726ns (logic 0.948ns, net 0.778ns, 54% logic) + Data Path Delay: 1.708ns (logic 0.948ns, net 0.760ns, 55% logic) Logic Levels: 2 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg7_syn_33.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg7_syn_36.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg7_syn_33.q[1] clk2q 0.146 r 2.556 - ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ua_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.620 r 3.176 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.607 - ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.765 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.136 - Arrival time 4.136 (2 lvl) + ua_lvds_rx/reg7_syn_36.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ua_lvds_rx/rx_clk_sft[1]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.431 r 3.589 + ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.747 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.118 + Arrival time 4.118 (2 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -791,34 +829,34 @@ Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) --------------------------------------------------------------------------------------------------------- cell setup -0.116 8.002 clock uncertainty -0.000 8.002 - clock recovergence pessimism 0.180 8.182 - Required time 8.182 + clock recovergence pessimism 0.208 8.210 + Required time 8.210 --------------------------------------------------------------------------------------------------------- - Slack 4.046ns + Slack 4.092ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.086 ns - Start Point: ua_lvds_rx/reg7_syn_24.clk (rising edge triggered by clock a_sclk) + Slack (setup check): 4.099 ns + Start Point: ua_lvds_rx/reg7_syn_39.clk (rising edge triggered by clock a_sclk) End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.686ns (logic 0.779ns, net 0.907ns, 46% logic) + Data Path Delay: 1.701ns (logic 0.941ns, net 0.760ns, 55% logic) Logic Levels: 2 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg7_syn_24.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg7_syn_39.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg7_syn_24.q[1] clk2q 0.146 r 2.556 - ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ua_lvds_rx/rx_clk_sft[3]) net (fanout = 2) 0.749 r 3.305 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.262 r 3.567 - ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.725 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.096 - Arrival time 4.096 (2 lvl) + ua_lvds_rx/reg7_syn_39.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.582 + ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.740 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.111 + Arrival time 4.111 (2 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -827,196 +865,264 @@ Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) --------------------------------------------------------------------------------------------------------- cell setup -0.116 8.002 clock uncertainty -0.000 8.002 - clock recovergence pessimism 0.180 8.182 - Required time 8.182 + clock recovergence pessimism 0.208 8.210 + Required time 8.210 --------------------------------------------------------------------------------------------------------- - Slack 4.086ns + Slack 4.099ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.194 ns - Start Point: ua_lvds_rx/reg7_syn_30.clk (rising edge triggered by clock a_sclk) + Slack (setup check): 4.261 ns + Start Point: ua_lvds_rx/reg7_syn_39.clk (rising edge triggered by clock a_sclk) End Point: ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.578ns (logic 0.941ns, net 0.637ns, 59% logic) + Data Path Delay: 1.539ns (logic 0.779ns, net 0.760ns, 50% logic) Logic Levels: 2 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg7_syn_30.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg7_syn_39.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg7_syn_30.q[1] clk2q 0.146 r 2.556 - ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.479 r 3.035 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.459 - ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.617 encrypted_text(0) - ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.988 - Arrival time 3.988 (2 lvl) + ua_lvds_rx/reg7_syn_39.q[0] clk2q 0.146 r 2.556 + ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ua_lvds_rx/rx_clk_sft[3]) net (fanout = 2) 0.602 r 3.158 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.262 r 3.420 + ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.578 encrypted_text(0) + ua_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.949 + Arrival time 3.949 (2 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 5.952 8.118 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.208 8.210 + Required time 8.210 +--------------------------------------------------------------------------------------------------------- + Slack 4.261ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point ua_lvds_rx/reg8_syn_174 (9 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 4.121 ns + Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_174.d[1] (rising edge triggered by clock a_sclk) + Clock group: a_lvds_clk_p + Process: Slow + Data Path Delay: 1.651ns (logic 0.655ns, net 0.996ns, 39% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_174.d[1] (ua_lvds_rx/sync0) net (fanout = 43) 0.996 r 3.552 encrypted_text(0) + ua_lvds_rx/reg8_syn_174 path2reg0 0.509 4.061 + Arrival time 4.061 (1 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/reg8_syn_174.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 8.118 --------------------------------------------------------------------------------------------------------- cell setup -0.116 8.002 clock uncertainty -0.000 8.002 clock recovergence pessimism 0.180 8.182 Required time 8.182 --------------------------------------------------------------------------------------------------------- - Slack 4.194ns + Slack 4.121ns --------------------------------------------------------------------------------------------------------- -Paths for end point ua_lvds_rx/ramread0_syn_88 (2 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.116 ns - Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_88.c[0] (rising edge triggered by clock a_sclk) + Slack (setup check): 4.121 ns + Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_174.d[0] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.663ns (logic 0.146ns, net 1.517ns, 8% logic) + Data Path Delay: 1.651ns (logic 0.655ns, net 0.996ns, 39% logic) Logic Levels: 1 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.146 r 2.556 - ua_lvds_rx/ramread0_syn_88.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 1.517 r 4.073 encrypted_text(0) - ua_lvds_rx/ramread0_syn_88 path2reg 0.000 4.073 - Arrival time 4.073 (1 lvl) + ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_174.d[0] (ua_lvds_rx/sync0) net (fanout = 43) 0.996 r 3.552 encrypted_text(0) + ua_lvds_rx/reg8_syn_174 path2reg0 0.509 4.061 + Arrival time 4.061 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_88.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg8_syn_174.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 5.952 8.118 --------------------------------------------------------------------------------------------------------- - cell setup -0.109 8.009 - clock uncertainty -0.000 8.009 - clock recovergence pessimism 0.180 8.189 - Required time 8.189 + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.180 8.182 + Required time 8.182 --------------------------------------------------------------------------------------------------------- - Slack 4.116ns + Slack 4.121ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 5.160 ns - Start Point: ua_lvds_rx/reg8_syn_157.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_88.c[1] (rising edge triggered by clock a_sclk) + Slack (setup check): 4.198 ns + Start Point: ua_lvds_rx/reg8_syn_174.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_174.a[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 0.619ns (logic 0.146ns, net 0.473ns, 23% logic) + Data Path Delay: 1.638ns (logic 0.878ns, net 0.760ns, 53% logic) Logic Levels: 1 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg8_syn_174.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg8_syn_157.q[0] clk2q 0.146 r 2.556 - ua_lvds_rx/ramread0_syn_88.c[1] (ua_lvds_rx/para_data[22]) net (fanout = 3) 0.473 r 3.029 encrypted_text(0) - ua_lvds_rx/ramread0_syn_88 path2reg 0.000 3.029 - Arrival time 3.029 (1 lvl) + ua_lvds_rx/reg8_syn_174.q[0] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_174.a[1] (ua_lvds_rx/para_data[20]) net (fanout = 3) 0.760 r 3.316 encrypted_text(0) + ua_lvds_rx/reg8_syn_174 path2reg0 0.732 4.048 + Arrival time 4.048 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_88.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg8_syn_174.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 5.952 8.118 --------------------------------------------------------------------------------------------------------- - cell setup -0.109 8.009 - clock uncertainty -0.000 8.009 - clock recovergence pessimism 0.180 8.189 - Required time 8.189 + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.244 8.246 + Required time 8.246 --------------------------------------------------------------------------------------------------------- - Slack 5.160ns + Slack 4.198ns --------------------------------------------------------------------------------------------------------- -Paths for end point ua_lvds_rx/ramread0_syn_46 (2 paths) +Paths for end point ua_lvds_rx/reg8_syn_160 (9 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.116 ns - Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_46.c[0] (rising edge triggered by clock a_sclk) + Slack (setup check): 4.121 ns + Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_160.d[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.663ns (logic 0.146ns, net 1.517ns, 8% logic) + Data Path Delay: 1.651ns (logic 0.655ns, net 0.996ns, 39% logic) Logic Levels: 1 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.146 r 2.556 - ua_lvds_rx/ramread0_syn_46.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 1.517 r 4.073 encrypted_text(0) - ua_lvds_rx/ramread0_syn_46 path2reg 0.000 4.073 - Arrival time 4.073 (1 lvl) + ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_160.d[1] (ua_lvds_rx/sync0) net (fanout = 43) 0.996 r 3.552 encrypted_text(0) + ua_lvds_rx/reg8_syn_160 path2reg0 0.509 4.061 + Arrival time 4.061 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg8_syn_160.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 5.952 8.118 --------------------------------------------------------------------------------------------------------- - cell setup -0.109 8.009 - clock uncertainty -0.000 8.009 - clock recovergence pessimism 0.180 8.189 - Required time 8.189 + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.180 8.182 + Required time 8.182 --------------------------------------------------------------------------------------------------------- - Slack 4.116ns + Slack 4.121ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.574 ns - Start Point: ua_lvds_rx/reg8_syn_153.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_46.c[1] (rising edge triggered by clock a_sclk) + Slack (setup check): 4.121 ns + Start Point: ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_160.d[0] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Slow - Data Path Delay: 1.205ns (logic 0.146ns, net 1.059ns, 12% logic) + Data Path Delay: 1.651ns (logic 0.655ns, net 0.996ns, 39% logic) Logic Levels: 1 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg8_syn_153.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg8_syn_153.q[0] clk2q 0.146 r 2.556 - ua_lvds_rx/ramread0_syn_46.c[1] (ua_lvds_rx/para_data[10]) net (fanout = 3) 1.059 r 3.615 encrypted_text(0) - ua_lvds_rx/ramread0_syn_46 path2reg 0.000 3.615 - Arrival time 3.615 (1 lvl) + ua_lvds_rx/sync0_reg_syn_4.q[1] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_160.d[0] (ua_lvds_rx/sync0) net (fanout = 43) 0.996 r 3.552 encrypted_text(0) + ua_lvds_rx/reg8_syn_160 path2reg0 0.509 4.061 + Arrival time 4.061 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg8_syn_160.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 5.952 8.118 --------------------------------------------------------------------------------------------------------- - cell setup -0.109 8.009 - clock uncertainty -0.000 8.009 - clock recovergence pessimism 0.180 8.189 - Required time 8.189 + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.180 8.182 + Required time 8.182 --------------------------------------------------------------------------------------------------------- - Slack 4.574ns + Slack 4.121ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 4.198 ns + Start Point: ua_lvds_rx/reg8_syn_160.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/reg8_syn_160.a[1] (rising edge triggered by clock a_sclk) + Clock group: a_lvds_clk_p + Process: Slow + Data Path Delay: 1.638ns (logic 0.878ns, net 0.760ns, 53% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/reg8_syn_160.clk (ua_lvds_rx/sclk) net 2.410 2.410 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + ua_lvds_rx/reg8_syn_160.q[0] clk2q 0.146 r 2.556 + ua_lvds_rx/reg8_syn_160.a[1] (ua_lvds_rx/para_data[11]) net (fanout = 3) 0.760 r 3.316 encrypted_text(0) + ua_lvds_rx/reg8_syn_160 path2reg0 0.732 4.048 + Arrival time 4.048 (1 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/reg8_syn_160.clk (ua_lvds_rx/sclk) net 2.166 2.166 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 8.118 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 8.002 + clock uncertainty -0.000 8.002 + clock recovergence pessimism 0.244 8.246 + Required time 8.246 +--------------------------------------------------------------------------------------------------------- + Slack 4.198ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) +Paths for end point ua_lvds_rx/ramread0_syn_18 (2 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.092 ns - Start Point: ua_lvds_rx/reg3_syn_184.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock a_sclk) + Start Point: ua_lvds_rx/reg3_syn_163.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_18.c[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Fast Data Path Delay: 0.220ns (logic 0.109ns, net 0.111ns, 49% logic) @@ -1026,17 +1132,17 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg3_syn_184.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg3_syn_163.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg3_syn_184.q[1] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.c[1] (ua_lvds_rx/para_data[26]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.249 + ua_lvds_rx/reg3_syn_163.q[1] clk2q 0.109 r 2.138 + ua_lvds_rx/ramread0_syn_18.c[1] (ua_lvds_rx/para_data[2]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0) + ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.249 Arrival time 2.249 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.113 2.343 @@ -1048,12 +1154,12 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.700 ns + Slack (hold check): 0.316 ns Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_18.c[0] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Fast - Data Path Delay: 0.858ns (logic 0.109ns, net 0.749ns, 12% logic) + Data Path Delay: 0.458ns (logic 0.109ns, net 0.349ns, 23% logic) Logic Levels: 1 Point Type Incr Path Info @@ -1064,29 +1170,29 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.749 r 2.887 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.887 - Arrival time 2.887 (1 lvl) + ua_lvds_rx/ramread0_syn_18.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.349 r 2.487 encrypted_text(0) + ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.487 + Arrival time 2.487 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.113 2.343 clock uncertainty 0.000 2.343 - clock recovergence pessimism -0.156 2.187 - Required time 2.187 + clock recovergence pessimism -0.172 2.171 + Required time 2.171 --------------------------------------------------------------------------------------------------------- - Slack 0.700ns + Slack 0.316ns --------------------------------------------------------------------------------------------------------- -Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) +Paths for end point ua_lvds_rx/ramread0_syn_18 (2 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.092 ns - Start Point: ua_lvds_rx/reg3_syn_184.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.b[1] (rising edge triggered by clock a_sclk) + Start Point: ua_lvds_rx/reg3_syn_163.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_18.b[1] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Fast Data Path Delay: 0.220ns (logic 0.109ns, net 0.111ns, 49% logic) @@ -1096,17 +1202,17 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg3_syn_184.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/reg3_syn_163.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg3_syn_184.q[0] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.b[1] (ua_lvds_rx/para_data[25]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.249 + ua_lvds_rx/reg3_syn_163.q[0] clk2q 0.109 r 2.138 + ua_lvds_rx/ramread0_syn_18.b[1] (ua_lvds_rx/para_data[1]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0) + ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.249 Arrival time 2.249 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.113 2.343 @@ -1118,82 +1224,12 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.403 ns - Start Point: ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.b[0] (rising edge triggered by clock a_sclk) - Clock group: a_lvds_clk_p - Process: Fast - Data Path Delay: 0.561ns (logic 0.109ns, net 0.452ns, 19% logic) - Logic Levels: 1 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg16_syn_33.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.029 ---------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1]) net (fanout = 10) 0.452 r 2.590 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.590 - Arrival time 2.590 (1 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 0.000 2.230 ---------------------------------------------------------------------------------------------------------- - cell hold 0.113 2.343 - clock uncertainty 0.000 2.343 - clock recovergence pessimism -0.156 2.187 - Required time 2.187 ---------------------------------------------------------------------------------------------------------- - Slack 0.403ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) ---------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.167 ns - Start Point: ua_lvds_rx/reg3_syn_181.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.a[1] (rising edge triggered by clock a_sclk) - Clock group: a_lvds_clk_p - Process: Fast - Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic) - Logic Levels: 1 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/reg3_syn_181.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.029 ---------------------------------------------------------------------------------------------------------- - ua_lvds_rx/reg3_syn_181.q[0] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.a[1] (ua_lvds_rx/para_data[24]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.354 - Arrival time 2.354 (1 lvl) - - source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 0.000 2.230 ---------------------------------------------------------------------------------------------------------- - cell hold 0.113 2.343 - clock uncertainty 0.000 2.343 - clock recovergence pessimism -0.156 2.187 - Required time 2.187 ---------------------------------------------------------------------------------------------------------- - Slack 0.167ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.412 ns + Slack (hold check): 0.517 ns Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk) - End Point: ua_lvds_rx/ramread0_syn_102.a[0] (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_18.b[0] (rising edge triggered by clock a_sclk) Clock group: a_lvds_clk_p Process: Fast - Data Path Delay: 0.570ns (logic 0.109ns, net 0.461ns, 19% logic) + Data Path Delay: 0.659ns (logic 0.109ns, net 0.550ns, 16% logic) Logic Levels: 1 Point Type Incr Path Info @@ -1204,21 +1240,91 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- ua_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.138 - ua_lvds_rx/ramread0_syn_102.a[0] (ua_lvds_rx/wcnt[0]) net (fanout = 11) 0.461 r 2.599 encrypted_text(0) - ua_lvds_rx/ramread0_syn_102 path2reg 0.000 2.599 - Arrival time 2.599 (1 lvl) + ua_lvds_rx/ramread0_syn_18.b[0] (ua_lvds_rx/wcnt[1]) net (fanout = 10) 0.550 r 2.688 encrypted_text(0) + ua_lvds_rx/ramread0_syn_18 path2reg 0.000 2.688 + Arrival time 2.688 (1 lvl) source latency 0.000 0.000 u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ua_lvds_rx/ramread0_syn_18.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.113 2.343 clock uncertainty 0.000 2.343 - clock recovergence pessimism -0.156 2.187 - Required time 2.187 + clock recovergence pessimism -0.172 2.171 + Required time 2.171 --------------------------------------------------------------------------------------------------------- - Slack 0.412ns + Slack 0.517ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point ua_lvds_rx/ramread0_syn_46 (2 paths) +--------------------------------------------------------------------------------------------------------- + Slack (hold check): 0.092 ns + Start Point: ua_lvds_rx/reg3_syn_168.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_46.c[1] (rising edge triggered by clock a_sclk) + Clock group: a_lvds_clk_p + Process: Fast + Data Path Delay: 0.220ns (logic 0.109ns, net 0.111ns, 49% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/reg3_syn_168.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.029 +--------------------------------------------------------------------------------------------------------- + ua_lvds_rx/reg3_syn_168.q[1] clk2q 0.109 r 2.138 + ua_lvds_rx/ramread0_syn_46.c[1] (ua_lvds_rx/para_data[10]) net (fanout = 2) 0.111 r 2.249 encrypted_text(0) + ua_lvds_rx/ramread0_syn_46 path2reg 0.000 2.249 + Arrival time 2.249 (1 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 0.000 2.230 +--------------------------------------------------------------------------------------------------------- + cell hold 0.113 2.343 + clock uncertainty 0.000 2.343 + clock recovergence pessimism -0.186 2.157 + Required time 2.157 +--------------------------------------------------------------------------------------------------------- + Slack 0.092ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.191 ns + Start Point: ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk) + End Point: ua_lvds_rx/ramread0_syn_46.c[0] (rising edge triggered by clock a_sclk) + Clock group: a_lvds_clk_p + Process: Fast + Data Path Delay: 0.333ns (logic 0.109ns, net 0.224ns, 32% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk) net 2.029 2.029 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.029 +--------------------------------------------------------------------------------------------------------- + ua_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.138 + ua_lvds_rx/ramread0_syn_46.c[0] (ua_lvds_rx/wcnt[2]) net (fanout = 9) 0.224 r 2.362 encrypted_text(0) + ua_lvds_rx/ramread0_syn_46 path2reg 0.000 2.362 + Arrival time 2.362 (1 lvl) + + source latency 0.000 0.000 + u_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk) net 2.230 2.230 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 0.000 2.230 +--------------------------------------------------------------------------------------------------------- + cell hold 0.113 2.343 + clock uncertainty 0.000 2.343 + clock recovergence pessimism -0.172 2.171 + Required time 2.171 +--------------------------------------------------------------------------------------------------------- + Slack 0.191ns --------------------------------------------------------------------------------------------------------- @@ -1237,175 +1343,19 @@ Minimum period is 0ns Timing constraint: clock: b_pclk Clock = b_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns -5792 endpoints analyzed totally, and 101792 paths analyzed +5884 endpoints analyzed totally, and 105460 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 10.513ns ---------------------------------------------------------------------------------------------------------- - -Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 (139 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 10.320 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 10.470ns (logic 6.651ns, net 3.819ns, 63% logic) - Logic Levels: 6 ( LUT5=4 ADDER=2 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.067 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.253 r 6.753 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.960 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.871 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.295 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.967 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.391 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.906 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.337 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.805 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 12.537 - Arrival time 12.537 (6 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.095 22.857 - Required time 22.857 ---------------------------------------------------------------------------------------------------------- - Slack 10.320ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 10.320 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 10.470ns (logic 6.651ns, net 3.819ns, 63% logic) - Logic Levels: 6 ( LUT5=4 ADDER=2 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.067 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.253 r 6.753 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.960 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.871 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.295 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.967 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.391 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.906 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.337 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.805 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 12.537 - Arrival time 12.537 (6 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.095 22.857 - Required time 22.857 ---------------------------------------------------------------------------------------------------------- - Slack 10.320ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 10.553 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 10.237ns (logic 6.578ns, net 3.659ns, 64% logic) - Logic Levels: 6 ( LUT5=4 ADDER=2 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.067 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net (fanout = 1) 1.093 r 6.593 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.706 r 7.299 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.299 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.372 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.372 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.727 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.638 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.062 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.734 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.158 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.673 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.104 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.572 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 12.304 - Arrival time 12.304 (6 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 20.833 22.878 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 22.762 - clock uncertainty -0.000 22.762 - clock recovergence pessimism 0.095 22.857 - Required time 22.857 ---------------------------------------------------------------------------------------------------------- - Slack 10.553ns - +Minimum period is 9.922ns --------------------------------------------------------------------------------------------------------- Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 (171 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 10.320 ns + Slack (setup check): 10.911 ns Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 10.470ns (logic 6.651ns, net 3.819ns, 63% logic) + Data Path Delay: 9.879ns (logic 6.651ns, net 3.228ns, 67% logic) Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info @@ -1418,23 +1368,23 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.253 r 6.753 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.960 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.871 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.295 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.967 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.391 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.906 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.337 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.805 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.537 - Arrival time 12.537 (6 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.338 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.009 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.433 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.996 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.420 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.888 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.319 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.895 r 11.214 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 11.946 + Arrival time 11.946 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 @@ -1448,16 +1398,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ clock recovergence pessimism 0.095 22.857 Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 10.320ns + Slack 10.911ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 10.320 ns + Slack (setup check): 10.911 ns Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 10.470ns (logic 6.651ns, net 3.819ns, 63% logic) + Data Path Delay: 9.879ns (logic 6.651ns, net 3.228ns, 67% logic) Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info @@ -1470,23 +1420,23 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 1.253 r 6.753 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 7.459 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.532 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.605 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.960 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.871 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.295 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.967 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.391 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.906 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.337 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.805 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.537 - Arrival time 12.537 (6 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.338 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.009 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.433 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.996 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.420 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.888 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.319 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.895 r 11.214 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 11.946 + Arrival time 11.946 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 @@ -1500,16 +1450,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ clock recovergence pessimism 0.095 22.857 Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 10.320ns + Slack 10.911ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 10.553 ns + Slack (setup check): 10.917 ns Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 10.237ns (logic 6.578ns, net 3.659ns, 64% logic) + Data Path Delay: 9.873ns (logic 6.645ns, net 3.228ns, 67% logic) Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info @@ -1521,22 +1471,26 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q 3.433 r 5.500 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net (fanout = 1) 1.093 r 6.593 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.706 r 7.299 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 7.299 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 7.372 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 7.372 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.727 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.911 r 8.638 - u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0] cell (LUT5) 0.424 r 9.062 - u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.672 r 9.734 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_213.f[1] cell (LUT5) 0.424 r 10.158 - u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.515 r 10.673 ../../../../hg_mp/fe/fifo_adc.v(36) - u_bus_top/reg14_syn_210.f[0] cell (LUT5) 0.431 r 11.104 - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.468 r 11.572 ../../../../hg_mp/fe/fifo_adc.v(36) - sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 12.304 - Arrival time 12.304 (6 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 6.758 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 6.758 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 6.831 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.831 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.904 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.904 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.977 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.977 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.332 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.003 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.427 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.990 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.414 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.882 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.313 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.895 r 11.208 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5) 0.732 11.940 + Arrival time 11.940 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 @@ -1550,19 +1504,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_ clock recovergence pessimism 0.095 22.857 Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 10.553ns + Slack 10.917ns --------------------------------------------------------------------------------------------------------- -Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_89 (214 paths) +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 (139 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 12.376 ns - Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_73.clk (rising edge triggered by clock b_pclk) - End Point: exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk) + Slack (setup check): 10.979 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 8.206ns (logic 4.304ns, net 3.902ns, 52% logic) - Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 ) + Data Path Delay: 9.811ns (logic 6.651ns, net 3.160ns, 67% logic) + Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -1570,57 +1524,51 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_89 (214 paths) uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg9_syn_73.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- - exdev_ctl_b/u_gen_sp/reg9_syn_73.q[1] clk2q 0.146 r 2.422 - exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net (fanout = 1) 0.625 r 3.047 ../../../../hg_mp/fe/gen_sp.v(87) - exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.836 r 3.883 - exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.883 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 4.015 - exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 4.015 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.147 - exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.147 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.534 - exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.941 r 5.475 - exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0] cell (LUT4) 0.408 r 5.883 - sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net (fanout = 1) 0.309 r 6.192 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_48.f[1] cell (LUT5) 0.424 r 6.616 - sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 7.072 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_51.f[1] cell (LUT5) 0.424 r 7.496 - sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.307 r 7.803 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg2_syn_46.f[1] cell (LUT5) 0.424 r 8.227 - sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.158 r 8.385 - sampling_fe_b/reg2_syn_46.f[0] cell (LUT5) 0.424 r 8.809 - sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.456 r 9.265 - sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1] cell (LUT5) 0.424 r 9.689 - exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.650 r 10.339 ../../../../hg_mp/fe/gen_sp.v(137) - exdev_ctl_b/u_gen_sp/reg0_syn_89 path2reg 0.143 10.482 - Arrival time 10.482 (8 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.338 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.009 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.433 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.996 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.420 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.888 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.319 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.827 r 11.146 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 11.878 + Arrival time 11.878 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- - cell setup -0.187 22.691 - clock uncertainty -0.000 22.691 - clock recovergence pessimism 0.167 22.858 - Required time 22.858 + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 12.376ns + Slack 10.979ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 12.465 ns - Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_77.clk (rising edge triggered by clock b_pclk) - End Point: exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk) + Slack (setup check): 10.979 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 8.145ns (logic 4.349ns, net 3.796ns, 53% logic) - Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 ) + Data Path Delay: 9.811ns (logic 6.651ns, net 3.160ns, 67% logic) + Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -1628,57 +1576,51 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_89 (214 paths) uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg9_syn_77.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- - exdev_ctl_b/u_gen_sp/reg9_syn_77.q[1] clk2q 0.146 r 2.422 - exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net (fanout = 1) 0.519 r 2.941 ../../../../hg_mp/fe/gen_sp.v(87) - exdev_ctl_b/u_gen_sp/sub1_syn_102.fco cell (ADDER) 0.881 r 3.822 - exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net (fanout = 1) 0.000 f 3.822 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.132 r 3.954 - exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.954 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 4.086 - exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 4.086 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.473 - exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.941 r 5.414 - exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0] cell (LUT4) 0.408 r 5.822 - sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net (fanout = 1) 0.309 r 6.131 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_48.f[1] cell (LUT5) 0.424 r 6.555 - sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 7.011 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_51.f[1] cell (LUT5) 0.424 r 7.435 - sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.307 r 7.742 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg2_syn_46.f[1] cell (LUT5) 0.424 r 8.166 - sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.158 r 8.324 - sampling_fe_b/reg2_syn_46.f[0] cell (LUT5) 0.424 r 8.748 - sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.456 r 9.204 - sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1] cell (LUT5) 0.424 r 9.628 - exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.650 r 10.278 ../../../../hg_mp/fe/gen_sp.v(137) - exdev_ctl_b/u_gen_sp/reg0_syn_89 path2reg 0.143 10.421 - Arrival time 10.421 (8 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q 3.433 r 5.500 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.706 r 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.837 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.910 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.983 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.338 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.009 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.433 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.996 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.420 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.888 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.319 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.827 r 11.146 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 11.878 + Arrival time 11.878 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- - cell setup -0.187 22.691 - clock uncertainty -0.000 22.691 - clock recovergence pessimism 0.195 22.886 - Required time 22.886 + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 12.465ns + Slack 10.979ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 12.546 ns - Start Point: exdev_ctl_b/u_gen_sp/reg9_syn_97.clk (rising edge triggered by clock b_pclk) - End Point: exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk) + Slack (setup check): 10.985 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 8.036ns (logic 4.283ns, net 3.753ns, 53% logic) - Logic Levels: 8 ( LUT5=5 ADDER=2 LUT4=1 ) + Data Path Delay: 9.805ns (logic 6.645ns, net 3.160ns, 67% logic) + Logic Levels: 6 ( LUT5=4 ADDER=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -1686,58 +1628,196 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_89 (214 paths) uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg9_syn_97.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 2.276 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net 2.067 2.067 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.067 --------------------------------------------------------------------------------------------------------- - exdev_ctl_b/u_gen_sp/reg9_syn_97.q[1] clk2q 0.146 r 2.422 - exdev_ctl_b/u_gen_sp/sub1_syn_103.a[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[3]) net (fanout = 1) 0.476 r 2.898 ../../../../hg_mp/fe/gen_sp.v(87) - exdev_ctl_b/u_gen_sp/sub1_syn_103.fco cell (ADDER) 0.947 r 3.845 - exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net (fanout = 1) 0.000 f 3.845 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_104.fco cell (ADDER) 0.132 r 3.977 - exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net (fanout = 1) 0.000 f 3.977 ../../../../hg_mp/fe/gen_sp.v(142) - exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0] cell (ADDER) 0.387 r 4.364 - exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net (fanout = 1) 0.941 r 5.305 - exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0] cell (LUT4) 0.408 r 5.713 - sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net (fanout = 1) 0.309 r 6.022 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_48.f[1] cell (LUT5) 0.424 r 6.446 - sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net (fanout = 1) 0.456 r 6.902 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg1_syn_51.f[1] cell (LUT5) 0.424 r 7.326 - sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net (fanout = 1) 0.307 r 7.633 ../../../../hg_mp/fe/gen_sp.v(137) - sampling_fe_b/reg2_syn_46.f[1] cell (LUT5) 0.424 r 8.057 - sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net (fanout = 1) 0.158 r 8.215 - sampling_fe_b/reg2_syn_46.f[0] cell (LUT5) 0.424 r 8.639 - sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net (fanout = 1) 0.456 r 9.095 - sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1] cell (LUT5) 0.424 r 9.519 - exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net (fanout = 8) 0.650 r 10.169 ../../../../hg_mp/fe/gen_sp.v(137) - exdev_ctl_b/u_gen_sp/reg0_syn_89 path2reg 0.143 10.312 - Arrival time 10.312 (8 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q 3.433 r 5.500 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net (fanout = 1) 0.631 r 6.131 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER) 0.627 r 6.758 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net (fanout = 1) 0.000 f 6.758 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER) 0.073 r 6.831 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net (fanout = 1) 0.000 f 6.831 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER) 0.073 r 6.904 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net (fanout = 1) 0.000 f 6.904 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER) 0.073 r 6.977 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net (fanout = 1) 0.000 f 6.977 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER) 0.355 r 7.332 + u_pic_cnt/reg1_syn_406.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net (fanout = 2) 0.671 r 8.003 + u_pic_cnt/reg1_syn_406.f[0] cell (LUT5) 0.424 r 8.427 + reg36_syn_108.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net (fanout = 1) 0.563 r 8.990 ../../../../hg_mp/fe/fifo_adc.v(36) + reg36_syn_108.f[0] cell (LUT5) 0.424 r 9.414 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net (fanout = 1) 0.468 r 9.882 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.f[1] cell (LUT5) 0.431 r 10.313 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net (fanout = 4) 0.827 r 11.140 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5) 0.732 11.872 + Arrival time 11.872 (6 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 20.833 22.878 --------------------------------------------------------------------------------------------------------- - cell setup -0.187 22.691 - clock uncertainty -0.000 22.691 - clock recovergence pessimism 0.167 22.858 - Required time 22.858 + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 --------------------------------------------------------------------------------------------------------- - Slack 12.546ns + Slack 10.985ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 (21 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 11.503 ns + Start Point: ub_lvds_rx/reg4_syn_22.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 9.078ns (logic 1.985ns, net 7.093ns, 21% logic) + Logic Levels: 5 ( LUT2=1 LUT3=1 LUT5=1 LUT4=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + ub_lvds_rx/reg4_syn_22.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg4_syn_22.q[0] clk2q 0.146 r 2.422 + ub_lvds_rx/ramread0_syn_73.a[1] (ub_lvds_rx/rcnt[0]) net (fanout = 32) 2.098 r 4.520 encrypted_text(0) + ub_lvds_rx/ramread0_syn_73.f[1] cell 0.408 r 4.928 + u_pixel_cdc/reg2_syn_106.b[0] (ub_lvds_rx/rdata[19]) net (fanout = 2) 0.459 r 5.387 encrypted_text(0) + u_pixel_cdc/reg2_syn_106.f[0] cell (LUT4) 0.431 r 5.818 + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227) net (fanout = 1) 0.673 r 6.491 ../../../../hg_mp/fe/fifo_adc.v(36) + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.f[0] cell (LUT5) 0.424 r 6.915 + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229) net (fanout = 6) 1.953 r 8.868 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.f[0] cell (LUT3) 0.262 r 9.130 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4) net (fanout = 24) 1.910 r 11.040 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 path2reg0 (LUT2) 0.314 11.354 + Arrival time 11.354 (5 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 +--------------------------------------------------------------------------------------------------------- + Slack 11.503ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 11.589 ns + Start Point: ub_lvds_rx/reg4_syn_22.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 8.992ns (logic 1.902ns, net 7.090ns, 21% logic) + Logic Levels: 5 ( LUT2=1 LUT3=1 LUT5=1 LUT4=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + ub_lvds_rx/reg4_syn_22.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg4_syn_22.q[0] clk2q 0.146 r 2.422 + ub_lvds_rx/ramread0_syn_73.a[0] (ub_lvds_rx/rcnt[0]) net (fanout = 32) 2.098 r 4.520 encrypted_text(0) + ub_lvds_rx/ramread0_syn_73.f[0] cell 0.408 r 4.928 + u_pixel_cdc/reg2_syn_106.c[0] (ub_lvds_rx/rdata[18]) net (fanout = 1) 0.456 r 5.384 encrypted_text(0) + u_pixel_cdc/reg2_syn_106.f[0] cell (LUT4) 0.348 r 5.732 + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227) net (fanout = 1) 0.673 r 6.405 ../../../../hg_mp/fe/fifo_adc.v(36) + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.f[0] cell (LUT5) 0.424 r 6.829 + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229) net (fanout = 6) 1.953 r 8.782 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.f[0] cell (LUT3) 0.262 r 9.044 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4) net (fanout = 24) 1.910 r 10.954 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 path2reg0 (LUT2) 0.314 11.268 + Arrival time 11.268 (5 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 +--------------------------------------------------------------------------------------------------------- + Slack 11.589ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 11.795 ns + Start Point: ub_lvds_rx/reg4_syn_22.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 8.786ns (logic 1.816ns, net 6.970ns, 20% logic) + Logic Levels: 5 ( LUT2=1 LUT3=1 LUT5=1 LUT4=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + ub_lvds_rx/reg4_syn_22.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg4_syn_22.q[0] clk2q 0.146 r 2.422 + ub_lvds_rx/ramread0_syn_86.a[0] (ub_lvds_rx/rcnt[0]) net (fanout = 32) 1.959 r 4.381 encrypted_text(0) + ub_lvds_rx/ramread0_syn_86.f[0] cell 0.408 r 4.789 + u_pixel_cdc/reg2_syn_106.d[0] (ub_lvds_rx/rdata[20]) net (fanout = 18) 0.475 r 5.264 encrypted_text(0) + u_pixel_cdc/reg2_syn_106.f[0] cell (LUT4) 0.262 r 5.526 + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227) net (fanout = 1) 0.673 r 6.199 ../../../../hg_mp/fe/fifo_adc.v(36) + u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.f[0] cell (LUT5) 0.424 r 6.623 + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229) net (fanout = 6) 1.953 r 8.576 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.f[0] cell (LUT3) 0.262 r 8.838 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4) net (fanout = 24) 1.910 r 10.748 ../../../../hg_mp/fe/fifo_adc.v(36) + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 path2reg0 (LUT2) 0.314 11.062 + Arrival time 11.062 (5 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.clk (uu_pll_lvds/clk0_out) net 2.045 2.045 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 20.833 22.878 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 22.762 + clock uncertainty -0.000 22.762 + clock recovergence pessimism 0.095 22.857 + Required time 22.857 +--------------------------------------------------------------------------------------------------------- + Slack 11.795ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 (10 paths) +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 (10 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.130 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk) + Slack (hold check): 0.089 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_743.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[9] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Fast - Data Path Delay: 0.375ns (logic 0.109ns, net 0.266ns, 29% logic) + Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic) Logic Levels: 1 ( EMB=1 ) Point Type Incr Path Info @@ -1746,19 +1826,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_743.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.q[1] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[28]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer_rev.v(331) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.313 - Arrival time 2.313 (1 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_743.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[9] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[56]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 path2reg (EMB) 0.000 2.272 + Arrival time 2.272 (1 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -1766,16 +1846,286 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in clock recovergence pessimism -0.147 2.183 Required time 2.183 --------------------------------------------------------------------------------------------------------- - Slack 0.130ns + Slack 0.089ns --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.195 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk) + Slack (hold check): 0.271 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[17]_syn_17.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[12] (rising edge triggered by clock b_pclk) Clock group: b_lvds_clk_p Process: Fast - Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic) + Data Path Delay: 0.516ns (logic 0.109ns, net 0.407ns, 21% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[17]_syn_17.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[17]_syn_17.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[12] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[59]) net (fanout = 2) 0.407 r 2.454 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 path2reg (EMB) 0.000 2.454 + Arrival time 2.454 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.271ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.311 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_728.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[4] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_728.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_728.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[51]) net (fanout = 2) 0.447 r 2.494 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 path2reg (EMB) 0.000 2.494 + Arrival time 2.494 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.311ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 (10 paths) +--------------------------------------------------------------------------------------------------------- + Slack (hold check): 0.089 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.272 + Arrival time 2.272 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.089ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.171 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_682.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[8] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_682.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_682.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[8] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[35]) net (fanout = 2) 0.370 r 2.417 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.417 + Arrival time 2.417 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.084 2.246 + Required time 2.246 +--------------------------------------------------------------------------------------------------------- + Slack 0.171ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.196 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[4] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.q[1] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[31]) net (fanout = 2) 0.332 r 2.379 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB) 0.000 2.379 + Arrival time 2.379 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.196ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 (10 paths) +--------------------------------------------------------------------------------------------------------- + Slack (hold check): 0.114 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_704.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[12] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.359ns (logic 0.109ns, net 0.250ns, 30% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_704.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_704.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[12] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[109]) net (fanout = 2) 0.250 r 2.297 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 path2reg (EMB) 0.000 2.297 + Arrival time 2.297 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.114ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.292 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_707.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[9] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.537ns (logic 0.109ns, net 0.428ns, 20% logic) + Logic Levels: 1 ( EMB=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_707.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_707.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[9] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[106]) net (fanout = 2) 0.428 r 2.475 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 path2reg (EMB) 0.000 2.475 + Arrival time 2.475 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.200 2.330 + clock uncertainty 0.000 2.330 + clock recovergence pessimism -0.147 2.183 + Required time 2.183 +--------------------------------------------------------------------------------------------------------- + Slack 0.292ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.312 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[8] (rising edge triggered by clock b_pclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.557ns (logic 0.109ns, net 0.448ns, 19% logic) Logic Levels: 1 ( EMB=1 ) Point Type Incr Path Info @@ -1788,15 +2138,15 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.q[1] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[20]) net (fanout = 2) 0.331 r 2.378 ../../../../hg_mp/fe/prebuffer_rev.v(331) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.378 - Arrival time 2.378 (1 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[8] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[105]) net (fanout = 2) 0.448 r 2.495 ../../../../hg_mp/fe/prebuffer_rev.v(331) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 path2reg (EMB) 0.000 2.495 + Arrival time 2.495 (1 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.200 2.330 @@ -1804,199 +2154,7 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/in clock recovergence pessimism -0.147 2.183 Required time 2.183 --------------------------------------------------------------------------------------------------------- - Slack 0.195ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.248 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.493ns (logic 0.109ns, net 0.384ns, 22% logic) - Logic Levels: 1 ( EMB=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.q[1] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23]) net (fanout = 2) 0.384 r 2.431 ../../../../hg_mp/fe/prebuffer_rev.v(331) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB) 0.000 2.431 - Arrival time 2.431 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.200 2.330 - clock uncertainty 0.000 2.330 - clock recovergence pessimism -0.147 2.183 - Required time 2.183 ---------------------------------------------------------------------------------------------------------- - Slack 0.248ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 (8 paths) ---------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.130 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.375ns (logic 0.109ns, net 0.266ns, 29% logic) - Logic Levels: 1 ( EMB=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.q[1] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[19]) net (fanout = 2) 0.266 r 2.313 ../../../../hg_mp/fe/prebuffer_rev.v(329) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.313 - Arrival time 2.313 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.200 2.330 - clock uncertainty 0.000 2.330 - clock recovergence pessimism -0.147 2.183 - Required time 2.183 ---------------------------------------------------------------------------------------------------------- - Slack 0.130ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.232 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.477ns (logic 0.109ns, net 0.368ns, 22% logic) - Logic Levels: 1 ( EMB=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.q[0] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[20]) net (fanout = 2) 0.368 r 2.415 ../../../../hg_mp/fe/prebuffer_rev.v(329) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.415 - Arrival time 2.415 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.200 2.330 - clock uncertainty 0.000 2.330 - clock recovergence pessimism -0.147 2.183 - Required time 2.183 ---------------------------------------------------------------------------------------------------------- - Slack 0.232ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.236 ns - Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk (rising edge triggered by clock b_pclk) - End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.481ns (logic 0.109ns, net 0.372ns, 22% logic) - Logic Levels: 1 ( EMB=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.q[0] clk2q 0.109 r 2.047 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[21]) net (fanout = 2) 0.372 r 2.419 ../../../../hg_mp/fe/prebuffer_rev.v(329) - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB) 0.000 2.419 - Arrival time 2.419 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.200 2.330 - clock uncertainty 0.000 2.330 - clock recovergence pessimism -0.147 2.183 - Required time 2.183 ---------------------------------------------------------------------------------------------------------- - Slack 0.236ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point exdev_ctl_b/reg3_syn_190 (1 paths) ---------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.167 ns - Start Point: u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk (rising edge triggered by clock clk_adc) - End Point: exdev_ctl_b/reg3_syn_190.mi[1] (rising edge triggered by clock b_pclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - u_bus_top/u_local_bus_slve_cis/reg42_syn_205.q[0] clk2q 0.109 r 2.047 - exdev_ctl_b/reg3_syn_190.mi[1] (u_bus_top/u_local_bus_slve_cis/reg21[2]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/local_bus/local_bus_slve_cis.v(75) - exdev_ctl_b/reg3_syn_190 path2reg1 0.095 2.358 - Arrival time 2.358 (0 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - exdev_ctl_b/reg3_syn_190.clk (uu_pll_lvds/clk0_out) net 2.130 2.130 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.061 2.191 - clock uncertainty 0.000 2.191 - clock recovergence pessimism 0.000 2.191 - Required time 2.191 ---------------------------------------------------------------------------------------------------------- - Slack 0.167ns + Slack 0.312ns --------------------------------------------------------------------------------------------------------- @@ -2005,265 +2163,21 @@ Paths for end point exdev_ctl_b/reg3_syn_190 (1 paths) Timing constraint: clock: b_sclk Clock = b_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns -282 endpoints analyzed totally, and 714 paths analyzed +282 endpoints analyzed totally, and 706 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 2.08ns ---------------------------------------------------------------------------------------------------------- - -Paths for end point ub_lvds_rx/reg3_syn_179 (5 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 3.872 ns - Start Point: ub_lvds_rx/reg8_syn_219.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_179.b[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.900ns (logic 0.695ns, net 1.205ns, 36% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_219.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_219.q[0] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_179.b[0] (ub_lvds_rx/rx_data[26]) net (fanout = 4) 1.205 r 3.627 encrypted_text(0) - ub_lvds_rx/reg3_syn_179 path2reg0 (LUT5) 0.549 4.176 - Arrival time 4.176 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 3.872ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 4.385 ns - Start Point: ub_lvds_rx/reg8_syn_163.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_179.c[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.387ns (logic 0.612ns, net 0.775ns, 44% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_163.q[1] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_179.c[0] (ub_lvds_rx/rx_data[27]) net (fanout = 3) 0.775 r 3.197 encrypted_text(0) - ub_lvds_rx/reg3_syn_179 path2reg0 (LUT5) 0.466 3.663 - Arrival time 3.663 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.385ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 4.636 ns - Start Point: ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_179.d[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.136ns (logic 0.517ns, net 0.619ns, 45% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_197.q[0] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_179.d[0] (ub_lvds_rx/sync0) net (fanout = 44) 0.619 r 3.041 encrypted_text(0) - ub_lvds_rx/reg3_syn_179 path2reg0 (LUT5) 0.371 3.412 - Arrival time 3.412 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.636ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point ub_lvds_rx/reg3_syn_195 (5 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.034 ns - Start Point: ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_195.b[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.738ns (logic 0.695ns, net 1.043ns, 39% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_197.q[1] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_195.b[0] (ub_lvds_rx/rx_data[24]) net (fanout = 2) 1.043 r 3.465 encrypted_text(0) - ub_lvds_rx/reg3_syn_195 path2reg0 (LUT5) 0.549 4.014 - Arrival time 4.014 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.034ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 4.636 ns - Start Point: ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_195.d[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.136ns (logic 0.517ns, net 0.619ns, 45% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_197.q[0] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_195.d[0] (ub_lvds_rx/sync0) net (fanout = 44) 0.619 r 3.041 encrypted_text(0) - ub_lvds_rx/reg3_syn_195 path2reg0 (LUT5) 0.371 3.412 - Arrival time 3.412 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.636ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 4.678 ns - Start Point: ub_lvds_rx/reg8_syn_219.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/reg3_syn_195.c[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.094ns (logic 0.612ns, net 0.482ns, 55% logic) - Logic Levels: 1 ( LUT5=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg8_syn_219.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg8_syn_219.q[1] clk2q 0.146 r 2.422 - ub_lvds_rx/reg3_syn_195.c[0] (ub_lvds_rx/rx_data[25]) net (fanout = 4) 0.482 r 2.904 encrypted_text(0) - ub_lvds_rx/reg3_syn_195 path2reg0 (LUT5) 0.466 3.370 - Arrival time 3.370 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.678ns - +Minimum period is 2.151ns --------------------------------------------------------------------------------------------------------- Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.071 ns - Start Point: ub_lvds_rx/reg7_syn_34.clk (rising edge triggered by clock b_sclk) + Slack (setup check): 3.801 ns + Start Point: ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 1.701ns (logic 0.941ns, net 0.760ns, 55% logic) + Data Path Delay: 1.999ns (logic 0.941ns, net 1.058ns, 47% logic) Logic Levels: 2 ( LUT5=1 ) - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg7_syn_34.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg7_syn_34.q[1] clk2q 0.146 r 2.422 - ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0) - ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.448 - ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.606 encrypted_text(0) - ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.977 - Arrival time 3.977 (2 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 5.952 7.997 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 7.881 - clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.167 8.048 - Required time 8.048 ---------------------------------------------------------------------------------------------------------- - Slack 4.071ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 4.371 ns - Start Point: ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Slow - Data Path Delay: 1.444ns (logic 0.695ns, net 0.749ns, 48% logic) - Logic Levels: 1 - Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 @@ -2272,9 +2186,11 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- ub_lvds_rx/reg7_syn_28.q[1] clk2q 0.146 r 2.422 - ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1] (ub_lvds_rx/rx_clk_sft[5]) net (fanout = 1) 0.749 r 3.171 encrypted_text(0) - ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.549 3.720 - Arrival time 3.720 (1 lvl) + ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.424 r 3.448 + ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.904 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.275 + Arrival time 4.275 (2 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -2283,19 +2199,19 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) --------------------------------------------------------------------------------------------------------- cell setup -0.116 7.881 clock uncertainty -0.000 7.881 - clock recovergence pessimism 0.210 8.091 - Required time 8.091 + clock recovergence pessimism 0.195 8.076 + Required time 8.076 --------------------------------------------------------------------------------------------------------- - Slack 4.371ns + Slack 3.801ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 4.382 ns + Slack (setup check): 3.963 ns Start Point: ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Slow - Data Path Delay: 1.433ns (logic 0.799ns, net 0.634ns, 55% logic) + Data Path Delay: 1.837ns (logic 0.779ns, net 1.058ns, 42% logic) Logic Levels: 2 ( LUT5=1 ) Point Type Incr Path Info @@ -2306,11 +2222,47 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- ub_lvds_rx/reg7_syn_28.q[0] clk2q 0.146 r 2.422 - ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0] (ub_lvds_rx/rx_clk_sft[4]) net (fanout = 2) 0.476 r 2.898 encrypted_text(0) - ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.282 r 3.180 - ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.158 r 3.338 encrypted_text(0) - ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 3.709 - Arrival time 3.709 (2 lvl) + ub_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ub_lvds_rx/rx_clk_sft[3]) net (fanout = 2) 0.602 r 3.024 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.262 r 3.286 + ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.742 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.113 + Arrival time 4.113 (2 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/rx_clk_sync_reg_syn_5.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 7.997 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 7.881 + clock uncertainty -0.000 7.881 + clock recovergence pessimism 0.195 8.076 + Required time 8.076 +--------------------------------------------------------------------------------------------------------- + Slack 3.963ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 4.018 ns + Start Point: ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 1.797ns (logic 0.865ns, net 0.932ns, 48% logic) + Logic Levels: 2 ( LUT5=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg7_syn_25.q[1] clk2q 0.146 r 2.422 + ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ub_lvds_rx/rx_clk_sft[2]) net (fanout = 2) 0.476 r 2.898 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0] cell (LUT5) 0.348 r 3.246 + ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net (fanout = 1) 0.456 r 3.702 encrypted_text(0) + ub_lvds_rx/rx_clk_sync_reg_syn_5 path2reg1 0.371 4.073 + Arrival time 4.073 (2 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -2322,16 +2274,226 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths) clock recovergence pessimism 0.210 8.091 Required time 8.091 --------------------------------------------------------------------------------------------------------- - Slack 4.382ns + Slack 4.018ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point exdev_ctl_b/u_gen_sp/add2_syn_98 (1 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 3.873 ns + Start Point: ub_lvds_rx/reg8_syn_190.clk (rising edge triggered by clock b_sclk) + End Point: exdev_ctl_b/u_gen_sp/add2_syn_98.mi[0] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 1.827ns (logic 0.289ns, net 1.538ns, 15% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_190.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg8_syn_190.q[0] clk2q 0.146 r 2.422 + exdev_ctl_b/u_gen_sp/add2_syn_98.mi[0] (ub_lvds_rx/rx_data[32]) net (fanout = 1) 1.538 r 3.960 encrypted_text(0) + exdev_ctl_b/u_gen_sp/add2_syn_98 path2reg0 0.143 4.103 + Arrival time 4.103 (0 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + exdev_ctl_b/u_gen_sp/add2_syn_98.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 7.997 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 7.881 + clock uncertainty -0.000 7.881 + clock recovergence pessimism 0.095 7.976 + Required time 7.976 +--------------------------------------------------------------------------------------------------------- + Slack 3.873ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point ub_lvds_rx/reg8_syn_159 (9 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 4.145 ns + Start Point: ub_lvds_rx/reg8_syn_159.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/reg8_syn_159.a[1] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 1.691ns (logic 0.878ns, net 0.813ns, 51% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg8_syn_159.q[0] clk2q 0.146 r 2.422 + ub_lvds_rx/reg8_syn_159.a[1] (ub_lvds_rx/para_data[23]) net (fanout = 3) 0.813 r 3.235 encrypted_text(0) + ub_lvds_rx/reg8_syn_159 path2reg0 0.732 3.967 + Arrival time 3.967 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 7.997 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 7.881 + clock uncertainty -0.000 7.881 + clock recovergence pessimism 0.231 8.112 + Required time 8.112 +--------------------------------------------------------------------------------------------------------- + Slack 4.145ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 4.544 ns + Start Point: ub_lvds_rx/reg8_syn_159.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/reg8_syn_159.b[1] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 1.292ns (logic 0.803ns, net 0.489ns, 62% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg8_syn_159.q[1] clk2q 0.146 r 2.422 + ub_lvds_rx/reg8_syn_159.b[1] (ub_lvds_rx/rx_data[26]) net (fanout = 5) 0.489 r 2.911 encrypted_text(0) + ub_lvds_rx/reg8_syn_159 path2reg0 0.657 3.568 + Arrival time 3.568 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 7.997 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 7.881 + clock uncertainty -0.000 7.881 + clock recovergence pessimism 0.231 8.112 + Required time 8.112 +--------------------------------------------------------------------------------------------------------- + Slack 4.544ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 4.544 ns + Start Point: ub_lvds_rx/reg8_syn_159.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/reg8_syn_159.b[0] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Slow + Data Path Delay: 1.292ns (logic 0.803ns, net 0.489ns, 62% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.276 2.276 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg8_syn_159.q[1] clk2q 0.146 r 2.422 + ub_lvds_rx/reg8_syn_159.b[0] (ub_lvds_rx/rx_data[26]) net (fanout = 5) 0.489 r 2.911 encrypted_text(0) + ub_lvds_rx/reg8_syn_159 path2reg0 0.657 3.568 + Arrival time 3.568 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg8_syn_159.clk (ub_lvds_rx/sclk) net 2.045 2.045 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 5.952 7.997 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 7.881 + clock uncertainty -0.000 7.881 + clock recovergence pessimism 0.231 8.112 + Required time 8.112 +--------------------------------------------------------------------------------------------------------- + Slack 4.544ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- +Paths for end point ub_lvds_rx/ramread0_syn_32 (2 paths) +--------------------------------------------------------------------------------------------------------- + Slack (hold check): 0.167 ns + Start Point: ub_lvds_rx/reg3_syn_168.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/ramread0_syn_32.a[1] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg3_syn_168.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg3_syn_168.q[0] clk2q 0.109 r 2.047 + ub_lvds_rx/ramread0_syn_32.a[1] (ub_lvds_rx/para_data[4]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0) + ub_lvds_rx/ramread0_syn_32 path2reg 0.000 2.263 + Arrival time 2.263 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/ramread0_syn_32.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.113 2.243 + clock uncertainty 0.000 2.243 + clock recovergence pessimism -0.147 2.096 + Required time 2.096 +--------------------------------------------------------------------------------------------------------- + Slack 0.167ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.315 ns + Start Point: ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk) + End Point: ub_lvds_rx/ramread0_syn_32.a[0] (rising edge triggered by clock b_sclk) + Clock group: b_lvds_clk_p + Process: Fast + Data Path Delay: 0.473ns (logic 0.109ns, net 0.364ns, 23% logic) + Logic Levels: 1 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + launch clock edge 0.000 1.938 +--------------------------------------------------------------------------------------------------------- + ub_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.047 + ub_lvds_rx/ramread0_syn_32.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.364 r 2.411 encrypted_text(0) + ub_lvds_rx/ramread0_syn_32 path2reg 0.000 2.411 + Arrival time 2.411 (1 lvl) + + source latency 0.000 0.000 + uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 + ub_lvds_rx/ramread0_syn_32.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + capture clock edge 0.000 2.130 +--------------------------------------------------------------------------------------------------------- + cell hold 0.113 2.243 + clock uncertainty 0.000 2.243 + clock recovergence pessimism -0.147 2.096 + Required time 2.096 +--------------------------------------------------------------------------------------------------------- + Slack 0.315ns + +--------------------------------------------------------------------------------------------------------- + Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.167 ns - Start Point: ub_lvds_rx/reg3_syn_182.clk (rising edge triggered by clock b_sclk) + Start Point: ub_lvds_rx/reg3_syn_185.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Fast @@ -2342,10 +2504,10 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_182.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ub_lvds_rx/reg3_syn_185.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg3_syn_182.q[1] clk2q 0.109 r 2.047 + ub_lvds_rx/reg3_syn_185.q[1] clk2q 0.109 r 2.047 ub_lvds_rx/ramread0_syn_102.c[1] (ub_lvds_rx/para_data[26]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0) ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.263 Arrival time 2.263 (1 lvl) @@ -2364,12 +2526,12 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.548 ns + Slack (hold check): 0.393 ns Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Fast - Data Path Delay: 0.690ns (logic 0.109ns, net 0.581ns, 15% logic) + Data Path Delay: 0.551ns (logic 0.109ns, net 0.442ns, 19% logic) Logic Levels: 1 Point Type Incr Path Info @@ -2380,9 +2542,9 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- ub_lvds_rx/reg16_syn_31.q[0] clk2q 0.109 r 2.047 - ub_lvds_rx/ramread0_syn_102.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.581 r 2.628 encrypted_text(0) - ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.628 - Arrival time 2.628 (1 lvl) + ub_lvds_rx/ramread0_syn_102.c[0] (ub_lvds_rx/wcnt[2]) net (fanout = 9) 0.442 r 2.489 encrypted_text(0) + ub_lvds_rx/ramread0_syn_102 path2reg 0.000 2.489 + Arrival time 2.489 (1 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -2391,17 +2553,17 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths) --------------------------------------------------------------------------------------------------------- cell hold 0.113 2.243 clock uncertainty 0.000 2.243 - clock recovergence pessimism -0.163 2.080 - Required time 2.080 + clock recovergence pessimism -0.147 2.096 + Required time 2.096 --------------------------------------------------------------------------------------------------------- - Slack 0.548ns + Slack 0.393ns --------------------------------------------------------------------------------------------------------- Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.167 ns - Start Point: ub_lvds_rx/reg3_syn_174.clk (rising edge triggered by clock b_sclk) + Start Point: ub_lvds_rx/para_en_reg_syn_5.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/ramread0_syn_74.a[1] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Fast @@ -2412,10 +2574,10 @@ Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_174.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ub_lvds_rx/para_en_reg_syn_5.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg3_syn_174.q[0] clk2q 0.109 r 2.047 + ub_lvds_rx/para_en_reg_syn_5.q[0] clk2q 0.109 r 2.047 ub_lvds_rx/ramread0_syn_74.a[1] (ub_lvds_rx/para_data[16]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0) ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.263 Arrival time 2.263 (1 lvl) @@ -2434,25 +2596,25 @@ Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.207 ns - Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk) + Slack (hold check): 0.215 ns + Start Point: ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk) End Point: ub_lvds_rx/ramread0_syn_74.a[0] (rising edge triggered by clock b_sclk) Clock group: b_lvds_clk_p Process: Fast - Data Path Delay: 0.349ns (logic 0.109ns, net 0.240ns, 31% logic) + Data Path Delay: 0.357ns (logic 0.109ns, net 0.248ns, 30% logic) Logic Levels: 1 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) + ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.047 - ub_lvds_rx/ramread0_syn_74.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.240 r 2.287 encrypted_text(0) - ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.287 - Arrival time 2.287 (1 lvl) + ub_lvds_rx/reg16_syn_33.q[0] clk2q 0.109 r 2.047 + ub_lvds_rx/ramread0_syn_74.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.248 r 2.295 encrypted_text(0) + ub_lvds_rx/ramread0_syn_74 path2reg 0.000 2.295 + Arrival time 2.295 (1 lvl) source latency 0.000 0.000 uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 @@ -2464,77 +2626,7 @@ Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths) clock recovergence pessimism -0.163 2.080 Required time 2.080 --------------------------------------------------------------------------------------------------------- - Slack 0.207ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point ub_lvds_rx/ramread0_syn_60 (2 paths) ---------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.167 ns - Start Point: ub_lvds_rx/reg3_syn_190.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/ramread0_syn_60.a[1] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic) - Logic Levels: 1 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg3_syn_190.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg3_syn_190.q[0] clk2q 0.109 r 2.047 - ub_lvds_rx/ramread0_syn_60.a[1] (ub_lvds_rx/para_data[12]) net (fanout = 2) 0.216 r 2.263 encrypted_text(0) - ub_lvds_rx/ramread0_syn_60 path2reg 0.000 2.263 - Arrival time 2.263 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/ramread0_syn_60.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.113 2.243 - clock uncertainty 0.000 2.243 - clock recovergence pessimism -0.147 2.096 - Required time 2.096 ---------------------------------------------------------------------------------------------------------- - Slack 0.167ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.324 ns - Start Point: ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk) - End Point: ub_lvds_rx/ramread0_syn_60.a[0] (rising edge triggered by clock b_sclk) - Clock group: b_lvds_clk_p - Process: Fast - Data Path Delay: 0.482ns (logic 0.109ns, net 0.373ns, 22% logic) - Logic Levels: 1 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk) net 1.938 1.938 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - launch clock edge 0.000 1.938 ---------------------------------------------------------------------------------------------------------- - ub_lvds_rx/reg16_syn_31.q[1] clk2q 0.109 r 2.047 - ub_lvds_rx/ramread0_syn_60.a[0] (ub_lvds_rx/wcnt[0]) net (fanout = 11) 0.373 r 2.420 encrypted_text(0) - ub_lvds_rx/ramread0_syn_60 path2reg 0.000 2.420 - Arrival time 2.420 (1 lvl) - - source latency 0.000 0.000 - uu_pll_lvds/pll_inst.clkc[1] 0.000 0.000 - ub_lvds_rx/ramread0_syn_60.clk (ub_lvds_rx/sclk) net 2.130 2.130 ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21) - capture clock edge 0.000 2.130 ---------------------------------------------------------------------------------------------------------- - cell hold 0.113 2.243 - clock uncertainty 0.000 2.243 - clock recovergence pessimism -0.147 2.096 - Required time 2.096 ---------------------------------------------------------------------------------------------------------- - Slack 0.324ns + Slack 0.215ns --------------------------------------------------------------------------------------------------------- @@ -2553,42 +2645,42 @@ Minimum period is 0ns Timing constraint: clock: S_clk Clock = S_clk, period 9.258ns, rising at 0ns, falling at 4.63ns -8560 endpoints analyzed totally, and 109052 paths analyzed +8652 endpoints analyzed totally, and 106032 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 9.231ns +Minimum period is 9.216ns --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 (1 paths) +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.027 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0] (rising edge triggered by clock S_clk) + Slack (setup check): 0.042 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.014ns (logic 0.720ns, net 1.294ns, 35% logic) + Data Path Delay: 1.999ns (logic 0.720ns, net 1.279ns, 36% logic) Logic Levels: 1 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422 - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.675 r 3.097 ../../../../hg_mp/fe/prebuffer.v(272) - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0] cell (LUT5) 0.431 r 3.528 - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 10) 0.619 r 4.147 ../../../../hg_mp/fe/prebuffer.v(301) - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 path2reg0 0.143 4.290 - Arrival time 4.290 (1 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.q[1] clk2q 0.146 r 2.422 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer_rev.v(272) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.f[0] cell (LUT5) 0.431 r 3.513 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74.mi[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13) net (fanout = 6) 0.619 r 4.132 ../../../../hg_mp/fe/prebuffer_rev.v(301) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74 path2reg0 0.143 4.275 + Arrival time 4.275 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 2.267 4.433 --------------------------------------------------------------------------------------------------------- cell setup -0.116 4.317 @@ -2596,41 +2688,41 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_ad clock recovergence pessimism 0.000 4.317 Required time 4.317 --------------------------------------------------------------------------------------------------------- - Slack 0.027ns + Slack 0.042ns --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/reg14_syn_101_syn_2 (1 paths) +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.027 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk) - End Point: U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0] (rising edge triggered by clock S_clk) + Slack (setup check): 0.162 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.014ns (logic 0.720ns, net 1.294ns, 35% logic) + Data Path Delay: 1.879ns (logic 0.720ns, net 1.159ns, 38% logic) Logic Levels: 1 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422 - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.675 r 3.097 ../../../../hg_mp/fe/prebuffer.v(272) - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0] cell (LUT5) 0.431 r 3.528 - U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 10) 0.619 r 4.147 ../../../../hg_mp/fe/prebuffer.v(301) - U_rgb_to_csi_pakage/reg14_syn_101_syn_2 path2reg0 0.143 4.290 - Arrival time 4.290 (1 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.q[1] clk2q 0.146 r 2.422 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer_rev.v(272) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.f[0] cell (LUT5) 0.431 r 3.513 + sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79.mi[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13) net (fanout = 6) 0.499 r 4.012 ../../../../hg_mp/fe/prebuffer_rev.v(301) + sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79 path2reg0 0.143 4.155 + Arrival time 4.155 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/reg14_syn_101_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 2.267 4.433 --------------------------------------------------------------------------------------------------------- cell setup -0.116 4.317 @@ -2638,41 +2730,41 @@ Paths for end point U_rgb_to_csi_pakage/reg14_syn_101_syn_2 (1 paths) clock recovergence pessimism 0.000 4.317 Required time 4.317 --------------------------------------------------------------------------------------------------------- - Slack 0.027ns + Slack 0.162ns --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 (1 paths) +Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.027 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0] (rising edge triggered by clock S_clk) + Slack (setup check): 0.165 ns + Start Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.014ns (logic 0.720ns, net 1.294ns, 35% logic) + Data Path Delay: 1.876ns (logic 0.720ns, net 1.156ns, 38% logic) Logic Levels: 1 ( LUT5=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll_lvds/pll_inst.clkc[0] 0.000 0.000 - u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) - u_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (uu_pll_lvds/clk0_out) net 2.276 2.276 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1] clk2q 0.146 r 2.422 - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net (fanout = 14) 0.675 r 3.097 ../../../../hg_mp/fe/prebuffer.v(272) - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0] cell (LUT5) 0.431 r 3.528 - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net (fanout = 10) 0.619 r 4.147 ../../../../hg_mp/fe/prebuffer.v(301) - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 path2reg0 0.143 4.290 - Arrival time 4.290 (1 lvl) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.q[1] clk2q 0.146 r 2.422 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0]) net (fanout = 14) 0.660 r 3.082 ../../../../hg_mp/fe/prebuffer_rev.v(272) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.f[0] cell (LUT5) 0.431 r 3.513 + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72.mi[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13) net (fanout = 6) 0.496 r 4.009 ../../../../hg_mp/fe/prebuffer_rev.v(301) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72 path2reg0 0.143 4.152 + Arrival time 4.152 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 2.267 4.433 --------------------------------------------------------------------------------------------------------- cell setup -0.116 4.317 @@ -2680,17 +2772,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 (1 paths) clock recovergence pessimism 0.000 4.317 Required time 4.317 --------------------------------------------------------------------------------------------------------- - Slack 0.027ns + Slack 0.165ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point u_pic_cnt/reg1_syn_385 (1 paths) +Paths for end point u_mipi_eot_min/reg1_syn_266 (1 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.067 ns - Start Point: reg36_syn_108.clk (rising edge triggered by clock clk_adc) - End Point: u_pic_cnt/reg1_syn_385.mi[0] (rising edge triggered by clock S_clk) + Start Point: u_bus_top/reg18_syn_64.clk (rising edge triggered by clock clk_adc) + End Point: u_mipi_eot_min/reg1_syn_266.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) @@ -2700,19 +2792,19 @@ Paths for end point u_pic_cnt/reg1_syn_385 (1 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - reg36_syn_108.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/reg18_syn_64.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - reg36_syn_108.q[0] clk2q 0.109 r 2.047 - u_pic_cnt/reg1_syn_385.mi[0] (u_pic_cnt/signal_from[5]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) - u_pic_cnt/reg1_syn_385 path2reg0 0.095 2.358 + u_bus_top/reg18_syn_64.q[1] clk2q 0.109 r 2.047 + u_mipi_eot_min/reg1_syn_266.mi[0] (u_mipi_eot_min/signal_from[0]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_mipi_eot_min/reg1_syn_266 path2reg0 0.095 2.358 Arrival time 2.358 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_pic_cnt/reg1_syn_385.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + u_mipi_eot_min/reg1_syn_266.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.291 @@ -2724,33 +2816,35 @@ Paths for end point u_pic_cnt/reg1_syn_385 (1 paths) --------------------------------------------------------------------------------------------------------- -Paths for end point u_mipi_eot_min/reg1_syn_289 (1 paths) +Paths for end point sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.067 ns - Start Point: u_bus_top/reg18_syn_66.clk (rising edge triggered by clock clk_adc) - End Point: u_mipi_eot_min/reg1_syn_289.mi[1] (rising edge triggered by clock S_clk) + Slack (hold check): 0.075 ns + Start Point: u_b_pclk/signal_to_reg[0]_reg_syn_5.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast - Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) + Data Path Delay: 0.428ns (logic 0.204ns, net 0.224ns, 47% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/reg18_syn_66.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + u_b_pclk/signal_to_reg[0]_reg_syn_5.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - u_bus_top/reg18_syn_66.q[1] clk2q 0.109 r 2.047 - u_mipi_eot_min/reg1_syn_289.mi[1] (u_mipi_eot_min/signal_from[0]) net (fanout = 1) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) - u_mipi_eot_min/reg1_syn_289 path2reg1 0.095 2.358 - Arrival time 2.358 (0 lvl) + u_b_pclk/signal_to_reg[0]_reg_syn_5.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20.mi[0] (u_b_pclk/signal_to[0]) net (fanout = 3) 0.224 r 2.271 ../../../../hg_mp/cdc/cdc_sync.v(10) + sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20 path2reg0 0.095 2.366 + Arrival time 2.366 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_eot_min/reg1_syn_289.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.291 @@ -2758,37 +2852,39 @@ Paths for end point u_mipi_eot_min/reg1_syn_289 (1 paths) clock recovergence pessimism 0.000 2.291 Required time 2.291 --------------------------------------------------------------------------------------------------------- - Slack 0.067ns + Slack 0.075ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_pic_cnt/reg1_syn_436 (1 paths) +Paths for end point sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.067 ns - Start Point: reg36_syn_111.clk (rising edge triggered by clock clk_adc) - End Point: u_pic_cnt/reg1_syn_436.mi[1] (rising edge triggered by clock S_clk) + Slack (hold check): 0.075 ns + Start Point: u_b_pclk/signal_to_reg[0]_reg_syn_6.clk (rising edge triggered by clock b_pclk) + End Point: sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27.mi[0] (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast - Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) + Data Path Delay: 0.428ns (logic 0.204ns, net 0.224ns, 47% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - reg36_syn_111.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) + uu_pll_lvds/pll_inst.clkc[0] 0.000 0.000 + uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50) + uu_pll_lvds/bufg_feedback.clko cell (GCLK) 0.000 0.000 + u_b_pclk/signal_to_reg[0]_reg_syn_6.clk (uu_pll_lvds/clk0_out) net 1.938 1.938 ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- - reg36_syn_111.q[1] clk2q 0.109 r 2.047 - u_pic_cnt/reg1_syn_436.mi[1] (u_pic_cnt/signal_from[19]) net (fanout = 2) 0.216 r 2.263 ../../../../hg_mp/cdc/cdc_sync.v(9) - u_pic_cnt/reg1_syn_436 path2reg1 0.095 2.358 - Arrival time 2.358 (0 lvl) + u_b_pclk/signal_to_reg[0]_reg_syn_6.q[0] clk2q 0.109 r 2.047 + sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27.mi[0] (u_b_pclk/signal_to[0]_syn_11) net (fanout = 5) 0.224 r 2.271 ../../../../hg_mp/cdc/cdc_sync.v(10) + sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27 path2reg0 0.095 2.366 + Arrival time 2.366 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_pic_cnt/reg1_syn_436.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.291 @@ -2796,21 +2892,21 @@ Paths for end point u_pic_cnt/reg1_syn_436 (1 paths) clock recovergence pessimism 0.000 2.291 Required time 2.291 --------------------------------------------------------------------------------------------------------- - Slack 0.067ns + Slack 0.075ns --------------------------------------------------------------------------------------------------------- Recovery checks: --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 (2 paths) +Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 5.372 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (rising edge triggered by clock S_clk) + Slack (recovery check): 5.904 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 3.522ns (logic 0.756ns, net 2.766ns, 21% logic) - Logic Levels: 2 ( LUT3=1 LUT2=1 ) + Data Path Delay: 2.990ns (logic 0.756ns, net 2.234ns, 25% logic) + Logic Levels: 2 ( LUT2=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -2818,23 +2914,23 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.492 r 3.048 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0] cell (LUT2) 0.262 r 3.310 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net (fanout = 28) 1.256 r 4.566 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.262 r 4.828 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.018 r 5.846 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 path2reg 0.086 5.932 - Arrival time 5.932 (2 lvl) + eot_reg_syn_5.q[0] clk2q 0.146 r 2.556 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.588 r 3.144 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[1] cell (LUT2) 0.262 r 3.406 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net (fanout = 17) 0.572 r 3.978 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.262 r 4.240 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.314 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 path2reg 0.086 5.400 + Arrival time 5.400 (2 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -2842,17 +2938,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 5.372ns + Slack 5.904ns --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 6.051 ns + Slack (recovery check): 6.005 ns Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.843ns (logic 0.580ns, net 2.263ns, 20% logic) - Logic Levels: 1 ( LUT3=1 ) + Data Path Delay: 2.889ns (logic 0.580ns, net 2.309ns, 20% logic) + Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -2864,17 +2960,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.245 r 3.801 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.348 r 4.149 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.018 r 5.167 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 path2reg 0.086 5.253 - Arrival time 5.253 (1 lvl) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.235 r 3.791 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.348 r 4.139 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.213 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 path2reg 0.086 5.299 + Arrival time 5.299 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -2882,19 +2978,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 6.051ns + Slack 6.005ns --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 (2 paths) +Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 5.379 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (rising edge triggered by clock S_clk) + Slack (recovery check): 5.904 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 3.515ns (logic 0.756ns, net 2.759ns, 21% logic) - Logic Levels: 2 ( LUT3=1 LUT2=1 ) + Data Path Delay: 2.990ns (logic 0.756ns, net 2.234ns, 25% logic) + Logic Levels: 2 ( LUT2=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -2902,23 +2998,23 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_ u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.492 r 3.048 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0] cell (LUT2) 0.262 r 3.310 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net (fanout = 28) 1.256 r 4.566 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.262 r 4.828 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.011 r 5.839 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 path2reg 0.086 5.925 - Arrival time 5.925 (2 lvl) + eot_reg_syn_5.q[0] clk2q 0.146 r 2.556 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.588 r 3.144 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[1] cell (LUT2) 0.262 r 3.406 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net (fanout = 17) 0.572 r 3.978 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.262 r 4.240 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.314 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 path2reg 0.086 5.400 + Arrival time 5.400 (2 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -2926,17 +3022,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_ clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 5.379ns + Slack 5.904ns --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 6.058 ns + Slack (recovery check): 6.005 ns Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.836ns (logic 0.580ns, net 2.256ns, 20% logic) - Logic Levels: 1 ( LUT3=1 ) + Data Path Delay: 2.889ns (logic 0.580ns, net 2.309ns, 20% logic) + Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -2948,17 +3044,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_ launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.245 r 3.801 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.348 r 4.149 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.011 r 5.160 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 path2reg 0.086 5.246 - Arrival time 5.246 (1 lvl) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.235 r 3.791 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.348 r 4.139 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.213 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 path2reg 0.086 5.299 + Arrival time 5.299 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -2966,19 +3062,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_ clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 6.058ns + Slack 6.005ns --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 (2 paths) +Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 5.379 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (rising edge triggered by clock S_clk) + Slack (recovery check): 5.904 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 3.515ns (logic 0.756ns, net 2.759ns, 21% logic) - Logic Levels: 2 ( LUT3=1 LUT2=1 ) + Data Path Delay: 2.990ns (logic 0.756ns, net 2.234ns, 25% logic) + Logic Levels: 2 ( LUT2=2 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -2986,23 +3082,23 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_ u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.492 r 3.048 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0] cell (LUT2) 0.262 r 3.310 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net (fanout = 28) 1.256 r 4.566 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.262 r 4.828 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.011 r 5.839 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 path2reg 0.086 5.925 - Arrival time 5.925 (2 lvl) + eot_reg_syn_5.q[0] clk2q 0.146 r 2.556 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.588 r 3.144 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.f[1] cell (LUT2) 0.262 r 3.406 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net (fanout = 17) 0.572 r 3.978 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.262 r 4.240 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.314 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 path2reg 0.086 5.400 + Arrival time 5.400 (2 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -3010,17 +3106,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_ clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 5.379ns + Slack 5.904ns --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 6.058 ns + Slack (recovery check): 6.005 ns Start Point: adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Slow - Data Path Delay: 2.836ns (logic 0.580ns, net 2.256ns, 20% logic) - Logic Levels: 1 ( LUT3=1 ) + Data Path Delay: 2.889ns (logic 0.580ns, net 2.309ns, 20% logic) + Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -3032,17 +3128,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_ launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- adj_vsynco_reg_syn_5.q[1] clk2q 0.146 r 2.556 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.245 r 3.801 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1] cell (LUT3) 0.348 r 4.149 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net (fanout = 20) 1.011 r 5.160 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 path2reg 0.086 5.246 - Arrival time 5.246 (1 lvl) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net (fanout = 8) 1.235 r 3.791 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.f[1] cell (LUT2) 0.348 r 4.139 + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net (fanout = 20) 1.074 r 5.213 ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 path2reg 0.086 5.299 + Arrival time 5.299 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 9.258 11.424 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 11.124 @@ -3050,20 +3146,20 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_ clock recovergence pessimism 0.180 11.304 Required time 11.304 --------------------------------------------------------------------------------------------------------- - Slack 6.058ns + Slack 6.005ns --------------------------------------------------------------------------------------------------------- Removal checks: --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 (1 paths) +Paths for end point U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 0.697 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr (rising edge triggered by clock S_clk) + Slack (removal check): 0.823 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast - Data Path Delay: 0.995ns (logic 0.375ns, net 0.620ns, 37% logic) + Data Path Delay: 1.105ns (logic 0.375ns, net 0.730ns, 33% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3072,40 +3168,40 @@ Paths for end point U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138 - U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.232 r 2.370 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/reg16_syn_103_syn_2.f[0] cell (LUT2) 0.179 r 2.549 - U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net (fanout = 27) 0.388 r 2.937 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 path2reg 0.087 3.024 - Arrival time 3.024 (1 lvl) + eot_reg_syn_5.q[0] clk2q 0.109 r 2.138 + U_rgb_to_csi_pakage/reg16_syn_107_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.516 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/reg16_syn_107_syn_2.f[0] cell (LUT2) 0.179 r 2.695 + U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 23) 0.352 r 3.047 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2 path2reg 0.087 3.134 + Arrival time 3.134 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.483 clock uncertainty 0.000 2.483 - clock recovergence pessimism -0.156 2.327 - Required time 2.327 + clock recovergence pessimism -0.172 2.311 + Required time 2.311 --------------------------------------------------------------------------------------------------------- - Slack 0.697ns + Slack 0.823ns --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/reg2_syn_151_syn_2 (1 paths) +Paths for end point U_rgb_to_csi_pakage/reg7_syn_139_syn_2 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 0.727 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr (rising edge triggered by clock S_clk) + Slack (removal check): 0.823 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/reg7_syn_139_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast - Data Path Delay: 1.025ns (logic 0.375ns, net 0.650ns, 36% logic) + Data Path Delay: 1.121ns (logic 0.375ns, net 0.746ns, 33% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3114,21 +3210,21 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_151_syn_2 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138 - U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.232 r 2.370 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/reg16_syn_103_syn_2.f[1] cell (LUT2) 0.179 r 2.549 - U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_3) net (fanout = 14) 0.418 r 2.967 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/reg2_syn_151_syn_2 path2reg 0.087 3.054 - Arrival time 3.054 (1 lvl) + eot_reg_syn_5.q[0] clk2q 0.109 r 2.138 + U_rgb_to_csi_pakage/S_frame_end_delay_en_n_syn_135_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.364 r 2.502 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/S_frame_end_delay_en_n_syn_135_syn_2.f[0] cell (LUT2) 0.179 r 2.681 + U_rgb_to_csi_pakage/reg7_syn_139_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_4) net (fanout = 9) 0.382 r 3.063 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/reg7_syn_139_syn_2 path2reg 0.087 3.150 + Arrival time 3.150 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/reg2_syn_151_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/reg7_syn_139_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.483 @@ -3136,18 +3232,18 @@ Paths for end point U_rgb_to_csi_pakage/reg2_syn_151_syn_2 (1 paths) clock recovergence pessimism -0.156 2.327 Required time 2.327 --------------------------------------------------------------------------------------------------------- - Slack 0.727ns + Slack 0.823ns --------------------------------------------------------------------------------------------------------- -Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths) +Paths for end point U_rgb_to_csi_pakage/reg7_syn_175_syn_2 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 0.767 ns - Start Point: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk) - End Point: U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (rising edge triggered by clock S_clk) + Slack (removal check): 0.835 ns + Start Point: eot_reg_syn_5.clk (rising edge triggered by clock S_clk) + End Point: U_rgb_to_csi_pakage/reg7_syn_175_syn_2.sr (rising edge triggered by clock S_clk) Clock group: clock_source Process: Fast - Data Path Delay: 1.065ns (logic 0.375ns, net 0.690ns, 35% logic) + Data Path Delay: 1.133ns (logic 0.375ns, net 0.758ns, 33% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3156,21 +3252,21 @@ Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + eot_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0] clk2q 0.109 r 2.138 - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 6) 0.339 r 2.477 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) - U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0] cell (LUT2) 0.179 r 2.656 - U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_1) net (fanout = 28) 0.351 r 3.007 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) - U_rgb_to_csi_pakage/reg12_syn_73_syn_2 path2reg 0.087 3.094 - Arrival time 3.094 (1 lvl) + eot_reg_syn_5.q[0] clk2q 0.109 r 2.138 + U_rgb_to_csi_pakage/reg16_syn_107_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net (fanout = 7) 0.378 r 2.516 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101) + U_rgb_to_csi_pakage/reg16_syn_107_syn_2.f[0] cell (LUT2) 0.179 r 2.695 + U_rgb_to_csi_pakage/reg7_syn_175_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net (fanout = 23) 0.380 r 3.075 ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102) + U_rgb_to_csi_pakage/reg7_syn_175_syn_2 path2reg 0.087 3.162 + Arrival time 3.162 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - U_rgb_to_csi_pakage/reg12_syn_73_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + U_rgb_to_csi_pakage/reg7_syn_175_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.483 @@ -3178,7 +3274,7 @@ Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths) clock recovergence pessimism -0.156 2.327 Required time 2.327 --------------------------------------------------------------------------------------------------------- - Slack 0.767ns + Slack 0.835ns --------------------------------------------------------------------------------------------------------- @@ -3239,19 +3335,19 @@ Period checks: Timing constraint: clock: clk_adc Clock = clk_adc, period 166.664ns, rising at 0ns, falling at 83.332ns -5330 endpoints analyzed totally, and 46330 paths analyzed +4390 endpoints analyzed totally, and 44500 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 159.25ns +Minimum period is 159.224ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_bus_top/reg12_syn_135 (1 paths) +Paths for end point u_bus_top/reg6_syn_120 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 7.414 ns - Start Point: reg26_syn_196.clk (rising edge triggered by clock S_clk) - End Point: u_bus_top/reg12_syn_135.mi[1] (rising edge triggered by clock clk_adc) + Slack (setup check): 7.440 ns + Start Point: reg24_syn_78.clk (rising edge triggered by clock S_clk) + End Point: u_bus_top/reg6_syn_120.mi[0] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Slow - Data Path Delay: 1.363ns (logic 0.289ns, net 1.074ns, 21% logic) + Data Path Delay: 1.337ns (logic 0.289ns, net 1.048ns, 21% logic) Logic Levels: 0 Point Type Incr Path Info @@ -3260,17 +3356,17 @@ Paths for end point u_bus_top/reg12_syn_135 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - reg26_syn_196.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + reg24_syn_78.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - reg26_syn_196.q[0] clk2q 0.146 r 2.556 - u_bus_top/reg12_syn_135.mi[1] (lv_cnt_a[0]) net (fanout = 4) 1.074 r 3.630 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1093) - u_bus_top/reg12_syn_135 path2reg1 0.143 3.773 - Arrival time 3.773 (0 lvl) + reg24_syn_78.q[0] clk2q 0.146 r 2.556 + u_bus_top/reg6_syn_120.mi[0] (frame_cnt[12]) net (fanout = 3) 1.048 r 3.604 ../../../../hg_mp/drx_top/huagao_mipi_top.v(249) + u_bus_top/reg6_syn_120 path2reg0 0.143 3.747 + Arrival time 3.747 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/reg12_syn_135.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/reg6_syn_120.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 9.258 11.303 --------------------------------------------------------------------------------------------------------- cell setup -0.116 11.187 @@ -3278,18 +3374,18 @@ Paths for end point u_bus_top/reg12_syn_135 (1 paths) clock recovergence pessimism 0.000 11.187 Required time 11.187 --------------------------------------------------------------------------------------------------------- - Slack 7.414ns + Slack 7.440ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_bus_top/reg6_syn_118 (1 paths) +Paths for end point u_bus_top/reg15_syn_164 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 7.493 ns - Start Point: reg24_syn_80.clk (rising edge triggered by clock S_clk) - End Point: u_bus_top/reg6_syn_118.mi[0] (rising edge triggered by clock clk_adc) + Slack (setup check): 7.555 ns + Start Point: reg27_syn_235.clk (rising edge triggered by clock S_clk) + End Point: u_bus_top/reg15_syn_164.mi[1] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Slow - Data Path Delay: 1.284ns (logic 0.289ns, net 0.995ns, 22% logic) + Data Path Delay: 1.222ns (logic 0.289ns, net 0.933ns, 23% logic) Logic Levels: 0 Point Type Incr Path Info @@ -3298,17 +3394,17 @@ Paths for end point u_bus_top/reg6_syn_118 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - reg24_syn_80.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + reg27_syn_235.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - reg24_syn_80.q[0] clk2q 0.146 r 2.556 - u_bus_top/reg6_syn_118.mi[0] (frame_cnt[10]) net (fanout = 3) 0.995 r 3.551 ../../../../hg_mp/drx_top/huagao_mipi_top.v(249) - u_bus_top/reg6_syn_118 path2reg0 0.143 3.694 - Arrival time 3.694 (0 lvl) + reg27_syn_235.q[1] clk2q 0.146 r 2.556 + u_bus_top/reg15_syn_164.mi[1] (lv_cnt_b[21]) net (fanout = 4) 0.933 r 3.489 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1105) + u_bus_top/reg15_syn_164 path2reg1 0.143 3.632 + Arrival time 3.632 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/reg6_syn_118.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/reg15_syn_164.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 9.258 11.303 --------------------------------------------------------------------------------------------------------- cell setup -0.116 11.187 @@ -3316,18 +3412,18 @@ Paths for end point u_bus_top/reg6_syn_118 (1 paths) clock recovergence pessimism 0.000 11.187 Required time 11.187 --------------------------------------------------------------------------------------------------------- - Slack 7.493ns + Slack 7.555ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_bus_top/reg0_syn_143_syn_2 (1 paths) +Paths for end point u_bus_top/reg0_syn_180 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 7.607 ns - Start Point: reg1_syn_154.clk (rising edge triggered by clock S_clk) - End Point: u_bus_top/reg0_syn_143_syn_2.mi[1] (rising edge triggered by clock clk_adc) + Slack (setup check): 7.628 ns + Start Point: reg1_syn_147.clk (rising edge triggered by clock S_clk) + End Point: u_bus_top/reg0_syn_180.mi[0] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Slow - Data Path Delay: 1.170ns (logic 0.289ns, net 0.881ns, 24% logic) + Data Path Delay: 1.149ns (logic 0.289ns, net 0.860ns, 25% logic) Logic Levels: 0 Point Type Incr Path Info @@ -3336,17 +3432,17 @@ Paths for end point u_bus_top/reg0_syn_143_syn_2 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - reg1_syn_154.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + reg1_syn_147.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - reg1_syn_154.q[0] clk2q 0.146 r 2.556 - u_bus_top/reg0_syn_143_syn_2.mi[1] (S_hs_data_reg[11]) net (fanout = 1) 0.881 r 3.437 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1296) - u_bus_top/reg0_syn_143_syn_2 path2reg1 0.143 3.580 - Arrival time 3.580 (0 lvl) + reg1_syn_147.q[0] clk2q 0.146 r 2.556 + u_bus_top/reg0_syn_180.mi[0] (S_hs_data_reg[2]) net (fanout = 1) 0.860 r 3.416 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1307) + u_bus_top/reg0_syn_180 path2reg0 0.143 3.559 + Arrival time 3.559 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/reg0_syn_143_syn_2.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/reg0_syn_180.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 9.258 11.303 --------------------------------------------------------------------------------------------------------- cell setup -0.116 11.187 @@ -3354,17 +3450,17 @@ Paths for end point u_bus_top/reg0_syn_143_syn_2 (1 paths) clock recovergence pessimism 0.000 11.187 Required time 11.187 --------------------------------------------------------------------------------------------------------- - Slack 7.607ns + Slack 7.628ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point add9_syn_98 (1 paths) +Paths for end point add7_syn_140 (1 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.258 ns - Start Point: reg24_syn_89.clk (rising edge triggered by clock S_clk) - End Point: add9_syn_98.mi[0] (rising edge triggered by clock clk_adc) + Start Point: reg25_syn_123.clk (rising edge triggered by clock S_clk) + End Point: add7_syn_140.mi[0] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) @@ -3376,17 +3472,17 @@ Paths for end point add9_syn_98 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - reg24_syn_89.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + reg25_syn_123.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - reg24_syn_89.q[0] clk2q 0.109 r 2.138 - add9_syn_98.mi[0] (frame_cnt[2]) net (fanout = 3) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(249) - add9_syn_98 path2reg0 0.095 2.449 + reg25_syn_123.q[1] clk2q 0.109 r 2.138 + add7_syn_140.mi[0] (lv_cnt2bus[5]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1306) + add7_syn_140 path2reg0 0.095 2.449 Arrival time 2.449 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - add9_syn_98.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + add7_syn_140.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.191 @@ -3398,11 +3494,11 @@ Paths for end point add9_syn_98 (1 paths) --------------------------------------------------------------------------------------------------------- -Paths for end point u_bus_top/reg0_syn_151_syn_2 (1 paths) +Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80 (1 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.258 ns - Start Point: reg1_syn_142.clk (rising edge triggered by clock S_clk) - End Point: u_bus_top/reg0_syn_151_syn_2.mi[0] (rising edge triggered by clock clk_adc) + Start Point: reg1_syn_162.clk (rising edge triggered by clock S_clk) + End Point: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80.mi[0] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) @@ -3414,17 +3510,17 @@ Paths for end point u_bus_top/reg0_syn_151_syn_2 (1 paths) u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - reg1_syn_142.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + reg1_syn_162.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - reg1_syn_142.q[0] clk2q 0.109 r 2.138 - u_bus_top/reg0_syn_151_syn_2.mi[0] (S_hs_data_reg[14]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1296) - u_bus_top/reg0_syn_151_syn_2 path2reg0 0.095 2.449 + reg1_syn_162.q[0] clk2q 0.109 r 2.138 + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80.mi[0] (S_hs_data_reg[13]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1307) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80 path2reg0 0.095 2.449 Arrival time 2.449 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - u_bus_top/reg0_syn_151_syn_2.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.191 @@ -3436,90 +3532,54 @@ Paths for end point u_bus_top/reg0_syn_151_syn_2 (1 paths) --------------------------------------------------------------------------------------------------------- -Paths for end point exdev_ctl_b/reg2_syn_213 (1 paths) +Paths for end point u_bus_top/reg9_syn_152 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.260 ns - Start Point: exdev_ctl_b/reg1_syn_176.clk (rising edge triggered by clock clk_adc) - End Point: exdev_ctl_b/reg2_syn_213.mi[0] (rising edge triggered by clock clk_adc) + Slack (hold check): 0.258 ns + Start Point: reg25_syn_126.clk (rising edge triggered by clock S_clk) + End Point: u_bus_top/reg9_syn_152.mi[1] (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast - Data Path Delay: 0.429ns (logic 0.204ns, net 0.225ns, 47% logic) + Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - exdev_ctl_b/reg1_syn_176.clk (exdev_ctl_a/clk_adc) net 1.938 1.938 ../../../../hg_mp/fe/exdev_ctl.v(4) - launch clock edge 0.000 1.938 + u_pll/pll_inst.clkc[0] 0.000 0.000 + u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) + u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 + reg25_syn_126.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - exdev_ctl_b/reg1_syn_176.q[1] clk2q 0.109 r 2.047 - exdev_ctl_b/reg2_syn_213.mi[0] (exdev_ctl_b/adc_cfg_dat_d1[27]) net (fanout = 2) 0.225 r 2.272 ../../../../hg_mp/fe/exdev_ctl.v(72) - exdev_ctl_b/reg2_syn_213 path2reg0 0.095 2.367 - Arrival time 2.367 (0 lvl) + reg25_syn_126.q[1] clk2q 0.109 r 2.138 + u_bus_top/reg9_syn_152.mi[1] (lv_cnt2bus[10]) net (fanout = 1) 0.216 r 2.354 ../../../../hg_mp/drx_top/huagao_mipi_top.v(1306) + u_bus_top/reg9_syn_152 path2reg1 0.095 2.449 + Arrival time 2.449 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - exdev_ctl_b/reg2_syn_213.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + u_bus_top/reg9_syn_152.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.191 clock uncertainty 0.000 2.191 - clock recovergence pessimism -0.084 2.107 - Required time 2.107 + clock recovergence pessimism 0.000 2.191 + Required time 2.191 --------------------------------------------------------------------------------------------------------- - Slack 0.260ns + Slack 0.258ns --------------------------------------------------------------------------------------------------------- Recovery checks: --------------------------------------------------------------------------------------------------------- -Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths) ---------------------------------------------------------------------------------------------------------- - Slack (recovery check): 163.478 ns - Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) - End Point: scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc) - Clock group: clock_source - Process: Slow - Data Path Delay: 2.822ns (logic 0.494ns, net 2.328ns, 17% logic) - Logic Levels: 1 ( LUT2=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4) - launch clock edge 0.000 2.276 ---------------------------------------------------------------------------------------------------------- - clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 1.416 r 3.838 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.043 - scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.912 r 4.955 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/a_ex_frame_en_reg_syn_5 path2reg 0.143 5.098 - Arrival time 5.098 (1 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[4] 0.000 0.000 - scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) - capture clock edge 166.664 168.709 ---------------------------------------------------------------------------------------------------------- - cell recovery -0.300 168.409 - clock uncertainty -0.000 168.409 - clock recovergence pessimism 0.167 168.576 - Required time 168.576 ---------------------------------------------------------------------------------------------------------- - Slack 163.478ns - ---------------------------------------------------------------------------------------------------------- - Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 163.665 ns + Slack (recovery check): 162.162 ns Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) End Point: scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Slow - Data Path Delay: 2.635ns (logic 0.494ns, net 2.141ns, 18% logic) + Data Path Delay: 4.066ns (logic 0.551ns, net 3.515ns, 13% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3530,11 +3590,11 @@ Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 1.416 r 3.838 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.043 - scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.725 r 4.768 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/a_ex_frame_reg_syn_5 path2reg 0.143 4.911 - Arrival time 4.911 (1 lvl) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.560 r 4.982 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.f[0] cell (LUT2) 0.262 r 5.244 + scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_3) net (fanout = 21) 0.955 r 6.199 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/a_ex_frame_reg_syn_5 path2reg 0.143 6.342 + Arrival time 6.342 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 @@ -3543,21 +3603,21 @@ Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths) --------------------------------------------------------------------------------------------------------- cell recovery -0.300 168.409 clock uncertainty -0.000 168.409 - clock recovergence pessimism 0.167 168.576 - Required time 168.576 + clock recovergence pessimism 0.095 168.504 + Required time 168.504 --------------------------------------------------------------------------------------------------------- - Slack 163.665ns + Slack 162.162ns --------------------------------------------------------------------------------------------------------- -Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths) +Paths for end point scan_start_diff/reg1_syn_21 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (recovery check): 163.676 ns + Slack (recovery check): 162.190 ns Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) - End Point: scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc) + End Point: scan_start_diff/reg1_syn_21.sr (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Slow - Data Path Delay: 2.624ns (logic 0.494ns, net 2.130ns, 18% logic) + Data Path Delay: 4.038ns (logic 0.551ns, net 3.487ns, 13% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3568,36 +3628,74 @@ Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths) launch clock edge 0.000 2.276 --------------------------------------------------------------------------------------------------------- clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 1.416 r 3.838 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.205 r 4.043 - scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.714 r 4.757 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/enable_from_arm_rog_reg_syn_5 path2reg 0.143 4.900 - Arrival time 4.900 (1 lvl) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.560 r 4.982 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.f[0] cell (LUT2) 0.262 r 5.244 + scan_start_diff/reg1_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_3) net (fanout = 21) 0.927 r 6.171 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/reg1_syn_21 path2reg 0.143 6.314 + Arrival time 6.314 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - scan_start_diff/enable_from_arm_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) + scan_start_diff/reg1_syn_21.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 166.664 168.709 --------------------------------------------------------------------------------------------------------- cell recovery -0.300 168.409 clock uncertainty -0.000 168.409 - clock recovergence pessimism 0.167 168.576 - Required time 168.576 + clock recovergence pessimism 0.095 168.504 + Required time 168.504 --------------------------------------------------------------------------------------------------------- - Slack 163.676ns + Slack 162.190ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point scan_start_diff/reg1_syn_18 (1 paths) +--------------------------------------------------------------------------------------------------------- + Slack (recovery check): 162.190 ns + Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) + End Point: scan_start_diff/reg1_syn_18.sr (rising edge triggered by clock clk_adc) + Clock group: clock_source + Process: Slow + Data Path Delay: 4.038ns (logic 0.551ns, net 3.487ns, 13% logic) + Logic Levels: 1 ( LUT2=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[4] 0.000 0.000 + clkubus_rstn_reg_syn_8.clk (exdev_ctl_a/clk_adc) net 2.276 2.276 ../../../../hg_mp/fe/exdev_ctl.v(4) + launch clock edge 0.000 2.276 +--------------------------------------------------------------------------------------------------------- + clkubus_rstn_reg_syn_8.q[0] clk2q 0.146 r 2.422 + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 2.560 r 4.982 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.f[0] cell (LUT2) 0.262 r 5.244 + scan_start_diff/reg1_syn_18.sr (BUSY_MIPI_sync_d0_i_syn_3) net (fanout = 21) 0.927 r 6.171 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/reg1_syn_18 path2reg 0.143 6.314 + Arrival time 6.314 (1 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[4] 0.000 0.000 + scan_start_diff/reg1_syn_18.clk (exdev_ctl_a/clk_adc) net 2.045 2.045 ../../../../hg_mp/fe/exdev_ctl.v(4) + capture clock edge 166.664 168.709 +--------------------------------------------------------------------------------------------------------- + cell recovery -0.300 168.409 + clock uncertainty -0.000 168.409 + clock recovergence pessimism 0.095 168.504 + Required time 168.504 +--------------------------------------------------------------------------------------------------------- + Slack 162.190ns --------------------------------------------------------------------------------------------------------- Removal checks: --------------------------------------------------------------------------------------------------------- -Paths for end point scan_start_diff/reg2_syn_20 (1 paths) +Paths for end point scan_start_diff/reg2_syn_21 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 1.366 ns + Slack (removal check): 2.267 ns Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) - End Point: scan_start_diff/reg2_syn_20.sr (rising edge triggered by clock clk_adc) + End Point: scan_start_diff/reg2_syn_21.sr (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast - Data Path Delay: 1.664ns (logic 0.322ns, net 1.342ns, 19% logic) + Data Path Delay: 2.628ns (logic 0.375ns, net 2.253ns, 14% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3608,34 +3706,34 @@ Paths for end point scan_start_diff/reg2_syn_20 (1 paths) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 0.991 r 3.038 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.164 - scan_start_diff/reg2_syn_20.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.351 r 3.515 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/reg2_syn_20 path2reg 0.087 3.602 - Arrival time 3.602 (1 lvl) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 1.828 r 3.875 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.f[0] cell (LUT2) 0.179 r 4.054 + scan_start_diff/reg2_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_3) net (fanout = 21) 0.425 r 4.479 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/reg2_syn_21 path2reg 0.087 4.566 + Arrival time 4.566 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - scan_start_diff/reg2_syn_20.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + scan_start_diff/reg2_syn_21.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.383 clock uncertainty 0.000 2.383 - clock recovergence pessimism -0.147 2.236 - Required time 2.236 + clock recovergence pessimism -0.084 2.299 + Required time 2.299 --------------------------------------------------------------------------------------------------------- - Slack 1.366ns + Slack 2.267ns --------------------------------------------------------------------------------------------------------- -Paths for end point scan_start_diff/a_frame_pad_rog_reg_syn_5 (1 paths) +Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_4 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 1.410 ns + Slack (removal check): 2.267 ns Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) - End Point: scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc) + End Point: scan_start_diff/enable_from_arm_rog_reg_syn_4.sr (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast - Data Path Delay: 1.708ns (logic 0.322ns, net 1.386ns, 18% logic) + Data Path Delay: 2.628ns (logic 0.375ns, net 2.253ns, 14% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3646,34 +3744,34 @@ Paths for end point scan_start_diff/a_frame_pad_rog_reg_syn_5 (1 paths) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 0.991 r 3.038 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.164 - scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.395 r 3.559 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/a_frame_pad_rog_reg_syn_5 path2reg 0.087 3.646 - Arrival time 3.646 (1 lvl) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 1.828 r 3.875 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_bus_top/u_local_bus_slve_cis/reg57_syn_44.f[0] cell (LUT2) 0.179 r 4.054 + scan_start_diff/enable_from_arm_rog_reg_syn_4.sr (BUSY_MIPI_sync_d0_i_syn_3) net (fanout = 21) 0.425 r 4.479 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/enable_from_arm_rog_reg_syn_4 path2reg 0.087 4.566 + Arrival time 4.566 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - scan_start_diff/a_frame_pad_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + scan_start_diff/enable_from_arm_rog_reg_syn_4.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.383 clock uncertainty 0.000 2.383 - clock recovergence pessimism -0.147 2.236 - Required time 2.236 + clock recovergence pessimism -0.084 2.299 + Required time 2.299 --------------------------------------------------------------------------------------------------------- - Slack 1.410ns + Slack 2.267ns --------------------------------------------------------------------------------------------------------- -Paths for end point scan_start_diff/reg2_syn_22 (1 paths) +Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_4 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (removal check): 1.433 ns + Slack (removal check): 2.284 ns Start Point: clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc) - End Point: scan_start_diff/reg2_syn_22.sr (rising edge triggered by clock clk_adc) + End Point: scan_start_diff/a_ex_frame_en_reg_syn_4.sr (rising edge triggered by clock clk_adc) Clock group: clock_source Process: Fast - Data Path Delay: 1.731ns (logic 0.322ns, net 1.409ns, 18% logic) + Data Path Delay: 2.645ns (logic 0.375ns, net 2.270ns, 14% logic) Logic Levels: 1 ( LUT2=1 ) Point Type Incr Path Info @@ -3684,23 +3782,23 @@ Paths for end point scan_start_diff/reg2_syn_22 (1 paths) launch clock edge 0.000 1.938 --------------------------------------------------------------------------------------------------------- clkubus_rstn_reg_syn_8.q[0] clk2q 0.109 r 2.047 - scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 16) 0.991 r 3.038 ../../../../hg_mp/cdc/cdc_sync.v(9) - scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0] cell (LUT2) 0.126 r 3.164 - scan_start_diff/reg2_syn_22.sr (BUSY_MIPI_sync_d0_i_syn_9) net (fanout = 11) 0.418 r 3.582 ../../../../hg_mp/drx_top/huagao_mipi_top.v(570) - scan_start_diff/reg2_syn_22 path2reg 0.087 3.669 - Arrival time 3.669 (1 lvl) + u_pixel_cdc/u_clka_cis_total_num/reg1_syn_400.d[0] (u_softrst_fan_ctrl/signal_from[0]) net (fanout = 14) 1.573 r 3.620 ../../../../hg_mp/cdc/cdc_sync.v(9) + u_pixel_cdc/u_clka_cis_total_num/reg1_syn_400.f[0] cell (LUT2) 0.179 r 3.799 + scan_start_diff/a_ex_frame_en_reg_syn_4.sr (BUSY_MIPI_sync_d0_i_syn_8) net (fanout = 29) 0.697 r 4.496 ../../../../hg_mp/drx_top/huagao_mipi_top.v(581) + scan_start_diff/a_ex_frame_en_reg_syn_4 path2reg 0.087 4.583 + Arrival time 4.583 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[4] 0.000 0.000 - scan_start_diff/reg2_syn_22.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) + scan_start_diff/a_ex_frame_en_reg_syn_4.clk (exdev_ctl_a/clk_adc) net 2.130 2.130 ../../../../hg_mp/fe/exdev_ctl.v(4) capture clock edge 0.000 2.130 --------------------------------------------------------------------------------------------------------- cell removal 0.253 2.383 clock uncertainty 0.000 2.383 - clock recovergence pessimism -0.147 2.236 - Required time 2.236 + clock recovergence pessimism -0.084 2.299 + Required time 2.299 --------------------------------------------------------------------------------------------------------- - Slack 1.433ns + Slack 2.284ns --------------------------------------------------------------------------------------------------------- @@ -3711,17 +3809,55 @@ Clock = S_clk_x2, period 4.629ns, rising at 0ns, falling at 2.314ns 86 endpoints analyzed totally, and 152 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 2.21ns +Minimum period is 2.026ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths) +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 2.419 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (rising edge triggered by clock S_clk_x2) + Slack (setup check): 2.603 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk (rising edge triggered by clock S_clk_x2) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9.mi[0] (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Slow - Data Path Delay: 1.850ns (logic 0.597ns, net 1.253ns, 32% logic) + Data Path Delay: 1.846ns (logic 0.494ns, net 1.352ns, 26% logic) + Logic Levels: 1 ( LUT1=1 ) + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.q[0] clk2q 0.146 r 2.556 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_dup_1) net (fanout = 11) 0.590 r 3.146 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.f[0] cell (LUT1) 0.205 r 3.351 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_n1) net (fanout = 2) 0.762 r 4.113 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9 path2reg0 0.143 4.256 + Arrival time 4.256 (1 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + capture clock edge 4.629 6.795 +--------------------------------------------------------------------------------------------------------- + cell setup -0.116 6.679 + clock uncertainty -0.000 6.679 + clock recovergence pessimism 0.180 6.859 + Required time 6.859 +--------------------------------------------------------------------------------------------------------- + Slack 2.603ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 (2 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 2.632 ns + Start Point: add8_syn_104.clk (rising edge triggered by clock S_clk) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[0] (rising edge triggered by clock S_clk_x2) + Clock group: clock_source + Process: Slow + Data Path Delay: 1.637ns (logic 0.597ns, net 1.040ns, 36% logic) Logic Levels: 1 ( LUT3=1 ) Point Type Incr Path Info @@ -3730,17 +3866,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + add8_syn_104.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.q[1] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net (fanout = 1) 1.253 r 3.809 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3) 0.451 4.260 - Arrival time 4.260 (1 lvl) + add8_syn_104.q[0] clk2q 0.146 r 2.556 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net (fanout = 1) 1.040 r 3.596 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg0 (LUT3) 0.451 4.047 + Arrival time 4.047 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 4.629 6.795 --------------------------------------------------------------------------------------------------------- cell setup -0.116 6.679 @@ -3748,16 +3884,16 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp clock recovergence pessimism 0.000 6.679 Required time 6.679 --------------------------------------------------------------------------------------------------------- - Slack 2.419ns + Slack 2.632ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 2.942 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (rising edge triggered by clock S_clk_x2) + Slack (setup check): 2.998 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (rising edge triggered by clock S_clk) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[0] (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Slow - Data Path Delay: 1.327ns (logic 0.506ns, net 0.821ns, 38% logic) + Data Path Delay: 1.271ns (logic 0.506ns, net 0.765ns, 39% logic) Logic Levels: 1 ( LUT3=1 ) Point Type Incr Path Info @@ -3766,17 +3902,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[0] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net (fanout = 1) 0.821 r 3.377 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3) 0.360 3.737 - Arrival time 3.737 (1 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.q[1] clk2q 0.146 r 2.556 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net (fanout = 1) 0.765 r 3.321 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 path2reg0 (LUT3) 0.360 3.681 + Arrival time 3.681 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 4.629 6.795 --------------------------------------------------------------------------------------------------------- cell setup -0.116 6.679 @@ -3784,168 +3920,58 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp clock recovergence pessimism 0.000 6.679 Required time 6.679 --------------------------------------------------------------------------------------------------------- - Slack 2.942ns + Slack 2.998ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths) +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 2.457 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2) + Slack (setup check): 2.903 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk (rising edge triggered by clock S_clk_x2) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.mi[0] (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Slow - Data Path Delay: 1.812ns (logic 0.612ns, net 1.200ns, 33% logic) - Logic Levels: 1 ( LUT3=1 ) + Data Path Delay: 1.610ns (logic 0.494ns, net 1.116ns, 30% logic) + Logic Levels: 1 ( LUT1=1 ) Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 - u_pll/pll_inst.clkc[0] 0.000 0.000 - u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) - u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.q[1] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net (fanout = 1) 1.200 r 3.756 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.466 4.222 - Arrival time 4.222 (1 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.q[0] clk2q 0.146 r 2.556 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_dup_1) net (fanout = 11) 0.590 r 3.146 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.f[0] cell (LUT1) 0.205 r 3.351 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_n1) net (fanout = 2) 0.526 r 3.877 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13 path2reg0 0.143 4.020 + Arrival time 4.020 (1 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 4.629 6.795 --------------------------------------------------------------------------------------------------------- cell setup -0.116 6.679 clock uncertainty -0.000 6.679 - clock recovergence pessimism 0.000 6.679 - Required time 6.679 + clock recovergence pessimism 0.244 6.923 + Required time 6.923 --------------------------------------------------------------------------------------------------------- - Slack 2.457ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 3.101 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2) - Clock group: clock_source - Process: Slow - Data Path Delay: 1.168ns (logic 0.695ns, net 0.473ns, 59% logic) - Logic Levels: 1 ( LUT3=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[0] 0.000 0.000 - u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) - u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.q[0] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net (fanout = 1) 0.473 r 3.029 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3) 0.549 3.578 - Arrival time 3.578 (1 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - capture clock edge 4.629 6.795 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 6.679 - clock uncertainty -0.000 6.679 - clock recovergence pessimism 0.000 6.679 - Required time 6.679 ---------------------------------------------------------------------------------------------------------- - Slack 3.101ns - ---------------------------------------------------------------------------------------------------------- - -Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 2.507 ns - Start Point: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (rising edge triggered by clock S_clk_x2) - Clock group: clock_source - Process: Slow - Data Path Delay: 1.762ns (logic 0.597ns, net 1.165ns, 33% logic) - Logic Levels: 1 ( LUT3=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[0] 0.000 0.000 - u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) - u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.q[0] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net (fanout = 1) 1.165 r 3.721 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3) 0.451 4.172 - Arrival time 4.172 (1 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - capture clock edge 4.629 6.795 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 6.679 - clock uncertainty -0.000 6.679 - clock recovergence pessimism 0.000 6.679 - Required time 6.679 ---------------------------------------------------------------------------------------------------------- - Slack 2.507ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 2.831 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (rising edge triggered by clock S_clk_x2) - Clock group: clock_source - Process: Slow - Data Path Delay: 1.438ns (logic 0.506ns, net 0.932ns, 35% logic) - Logic Levels: 1 ( LUT3=1 ) - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[0] 0.000 0.000 - u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) - u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[1] clk2q 0.146 r 2.556 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net (fanout = 1) 0.932 r 3.488 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3) 0.360 3.848 - Arrival time 3.848 (1 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.166 2.166 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - capture clock edge 4.629 6.795 ---------------------------------------------------------------------------------------------------------- - cell setup -0.116 6.679 - clock uncertainty -0.000 6.679 - clock recovergence pessimism 0.000 6.679 - Required time 6.679 ---------------------------------------------------------------------------------------------------------- - Slack 2.831ns + Slack 2.903ns --------------------------------------------------------------------------------------------------------- Hold checks: --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 (1 paths) +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.167 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0] (rising edge triggered by clock S_clk_x2) + Slack (hold check): 0.158 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_13_syn_2_dup_1.clk (rising edge triggered by clock S_clk) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Fast - Data Path Delay: 0.429ns (logic 0.204ns, net 0.225ns, 47% logic) + Data Path Delay: 0.420ns (logic 0.204ns, net 0.216ns, 48% logic) Logic Levels: 0 Point Type Incr Path Info @@ -3954,17 +3980,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_13_syn_2_dup_1.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.225 r 2.363 encrypted_text(0) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 path2reg0 0.095 2.458 - Arrival time 2.458 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_13_syn_2_dup_1.q[1] clk2q 0.109 r 2.138 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_dup_42) net (fanout = 1) 0.216 r 2.354 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 path2reg0 0.095 2.449 + Arrival time 2.449 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.291 @@ -3972,18 +3998,18 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1 clock recovergence pessimism 0.000 2.291 Required time 2.291 --------------------------------------------------------------------------------------------------------- - Slack 0.167ns + Slack 0.158ns --------------------------------------------------------------------------------------------------------- -Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 (1 paths) +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.190 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk) - End Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0] (rising edge triggered by clock S_clk_x2) + Slack (hold check): 0.212 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_17.clk (rising edge triggered by clock S_clk) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.sr (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Fast - Data Path Delay: 0.452ns (logic 0.204ns, net 0.248ns, 45% logic) + Data Path Delay: 0.421ns (logic 0.196ns, net 0.225ns, 46% logic) Logic Levels: 0 Point Type Incr Path Info @@ -3992,37 +4018,37 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1 u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_17.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.q[0] clk2q 0.109 r 2.138 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d) net (fanout = 5) 0.248 r 2.386 encrypted_text(0) - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 path2reg0 0.095 2.481 - Arrival time 2.481 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_17.q[0] clk2q 0.109 r 2.138 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.sr (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_dup_41) net (fanout = 2) 0.225 r 2.363 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg 0.087 2.450 + Arrival time 2.450 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- - cell hold 0.061 2.291 - clock uncertainty 0.000 2.291 - clock recovergence pessimism 0.000 2.291 - Required time 2.291 + cell hold 0.008 2.238 + clock uncertainty 0.000 2.238 + clock recovergence pessimism 0.000 2.238 + Required time 2.238 --------------------------------------------------------------------------------------------------------- - Slack 0.190ns + Slack 0.212ns --------------------------------------------------------------------------------------------------------- -Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 (2 paths) +Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 (1 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.341 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1] (rising edge triggered by clock S_clk_x2) + Slack (hold check): 0.264 ns + Start Point: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_18.clk (rising edge triggered by clock S_clk) + End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2) Clock group: clock_source Process: Fast - Data Path Delay: 0.603ns (logic 0.378ns, net 0.225ns, 62% logic) - Logic Levels: 1 + Data Path Delay: 0.526ns (logic 0.204ns, net 0.322ns, 38% logic) + Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- @@ -4030,17 +4056,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_ u_pll/pll_inst.clkc[0] 0.000 0.000 u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_18.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.q[0] clk2q 0.109 r 2.138 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en) net (fanout = 2) 0.225 r 2.363 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 path2reg1 0.269 2.632 - Arrival time 2.632 (1 lvl) + sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_18.q[0] clk2q 0.109 r 2.138 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net (fanout = 1) 0.322 r 2.460 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 path2reg0 0.095 2.555 + Arrival time 2.555 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) capture clock edge 0.000 2.230 --------------------------------------------------------------------------------------------------------- cell hold 0.061 2.291 @@ -4048,43 +4074,7 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_ clock recovergence pessimism 0.000 2.291 Required time 2.291 --------------------------------------------------------------------------------------------------------- - Slack 0.341ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.490 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (rising edge triggered by clock S_clk) - End Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1] (rising edge triggered by clock S_clk_x2) - Clock group: clock_source - Process: Fast - Data Path Delay: 0.752ns (logic 0.430ns, net 0.322ns, 57% logic) - Logic Levels: 1 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[0] 0.000 0.000 - u_pll/bufg_feedback.clki (u_pll/clk0_buf) net 0.000 0.000 ../../../../hg_mp/anlogic_ip/pll/pll.v(46) - u_pll/bufg_feedback.clko cell (GCLK) 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21) - launch clock edge 0.000 2.029 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.q[1] clk2q 0.109 r 2.138 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data[0]) net (fanout = 1) 0.322 r 2.460 encrypted_text(0) - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 path2reg1 0.321 2.781 - Arrival time 2.781 (1 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.230 2.230 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - capture clock edge 0.000 2.230 ---------------------------------------------------------------------------------------------------------- - cell hold 0.061 2.291 - clock uncertainty 0.000 2.291 - clock recovergence pessimism 0.000 2.291 - Required time 2.291 ---------------------------------------------------------------------------------------------------------- - Slack 0.490ns + Slack 0.264ns --------------------------------------------------------------------------------------------------------- @@ -4095,17 +4085,17 @@ Clock = S_clk_x4, period 2.314ns, rising at 0ns, falling at 1.157ns 8 endpoints analyzed totally, and 32 paths analyzed 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000) -Minimum period is 1.435ns +Minimum period is 1.399ns --------------------------------------------------------------------------------------------------------- Paths for end point O_data_hs_p[1]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.879 ns + Slack (setup check): 0.915 ns Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow - Data Path Delay: 0.821ns (logic 0.146ns, net 0.675ns, 17% logic) + Data Path Delay: 0.785ns (logic 0.146ns, net 0.639ns, 18% logic) Logic Levels: 0 Point Type Incr Path Info @@ -4116,9 +4106,9 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556 - O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.675 r 3.231 encrypted_text(0) - O_data_hs_p[1]_syn_2 path2reg 0.000 3.231 - Arrival time 3.231 (0 lvl) + O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.639 r 3.195 encrypted_text(0) + O_data_hs_p[1]_syn_2 path2reg 0.000 3.195 + Arrival time 3.195 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 @@ -4130,50 +4120,16 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) clock recovergence pessimism 0.000 4.110 Required time 4.110 --------------------------------------------------------------------------------------------------------- - Slack 0.879ns + Slack 0.915ns --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.879 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2) + Slack (setup check): 0.915 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow - Data Path Delay: 0.821ns (logic 0.146ns, net 0.675ns, 17% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.146 r 2.556 - O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.675 r 3.231 encrypted_text(0) - O_data_hs_p[1]_syn_2 path2reg 0.000 3.231 - Arrival time 3.231 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) - capture clock edge 2.314 4.171 ---------------------------------------------------------------------------------------------------------- - cell setup -0.061 4.110 - clock uncertainty -0.000 4.110 - clock recovergence pessimism 0.000 4.110 - Required time 4.110 ---------------------------------------------------------------------------------------------------------- - Slack 0.879ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 0.923 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) - Clock group: clock_source - Process: Slow - Data Path Delay: 0.777ns (logic 0.146ns, net 0.631ns, 18% logic) + Data Path Delay: 0.785ns (logic 0.146ns, net 0.639ns, 18% logic) Logic Levels: 0 Point Type Incr Path Info @@ -4184,9 +4140,9 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556 - O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.631 r 3.187 encrypted_text(0) - O_data_hs_p[1]_syn_2 path2reg 0.000 3.187 - Arrival time 3.187 (0 lvl) + O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.639 r 3.195 encrypted_text(0) + O_data_hs_p[1]_syn_2 path2reg 0.000 3.195 + Arrival time 3.195 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 @@ -4198,35 +4154,33 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) clock recovergence pessimism 0.000 4.110 Required time 4.110 --------------------------------------------------------------------------------------------------------- - Slack 0.923ns + Slack 0.915ns --------------------------------------------------------------------------------------------------------- -Paths for end point O_data_hs_p[2]_syn_2 (4 paths) ---------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.923 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[2]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) + Slack (setup check): 1.078 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow - Data Path Delay: 0.777ns (logic 0.146ns, net 0.631ns, 18% logic) + Data Path Delay: 0.622ns (logic 0.146ns, net 0.476ns, 23% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556 - O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.631 r 3.187 encrypted_text(0) - O_data_hs_p[2]_syn_2 path2reg 0.000 3.187 - Arrival time 3.187 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556 + O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.476 r 3.032 encrypted_text(0) + O_data_hs_p[1]_syn_2 path2reg 0.000 3.032 + Arrival time 3.032 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) capture clock edge 2.314 4.171 --------------------------------------------------------------------------------------------------------- cell setup -0.061 4.110 @@ -4234,82 +4188,14 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) clock recovergence pessimism 0.000 4.110 Required time 4.110 --------------------------------------------------------------------------------------------------------- - Slack 0.923ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 0.925 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) - Clock group: clock_source - Process: Slow - Data Path Delay: 0.775ns (logic 0.146ns, net 0.629ns, 18% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556 - O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.629 r 3.185 encrypted_text(0) - O_data_hs_p[2]_syn_2 path2reg 0.000 3.185 - Arrival time 3.185 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) - capture clock edge 2.314 4.171 ---------------------------------------------------------------------------------------------------------- - cell setup -0.061 4.110 - clock uncertainty -0.000 4.110 - clock recovergence pessimism 0.000 4.110 - Required time 4.110 ---------------------------------------------------------------------------------------------------------- - Slack 0.925ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): 1.224 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) - Clock group: clock_source - Process: Slow - Data Path Delay: 0.476ns (logic 0.146ns, net 0.330ns, 30% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556 - O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.330 r 2.886 encrypted_text(0) - O_data_hs_p[2]_syn_2 path2reg 0.000 2.886 - Arrival time 2.886 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) - capture clock edge 2.314 4.171 ---------------------------------------------------------------------------------------------------------- - cell setup -0.061 4.110 - clock uncertainty -0.000 4.110 - clock recovergence pessimism 0.000 4.110 - Required time 4.110 ---------------------------------------------------------------------------------------------------------- - Slack 1.224ns + Slack 1.078ns --------------------------------------------------------------------------------------------------------- Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack (setup check): 0.928 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow @@ -4320,10 +4206,10 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.146 r 2.556 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556 O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.626 r 3.182 encrypted_text(0) O_data_hs_p[3]_syn_2 path2reg 0.000 3.182 Arrival time 3.182 (0 lvl) @@ -4342,25 +4228,25 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): 0.929 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) + Slack (setup check): 1.035 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow - Data Path Delay: 0.771ns (logic 0.146ns, net 0.625ns, 18% logic) + Data Path Delay: 0.665ns (logic 0.146ns, net 0.519ns, 21% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556 - O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.625 r 3.181 encrypted_text(0) - O_data_hs_p[3]_syn_2 path2reg 0.000 3.181 - Arrival time 3.181 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.146 r 2.556 + O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.519 r 3.075 encrypted_text(0) + O_data_hs_p[3]_syn_2 path2reg 0.000 3.075 + Arrival time 3.075 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 @@ -4372,13 +4258,83 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) clock recovergence pessimism 0.000 4.110 Required time 4.110 --------------------------------------------------------------------------------------------------------- - Slack 0.929ns + Slack 1.035ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 1.078 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) + Clock group: clock_source + Process: Slow + Data Path Delay: 0.622ns (logic 0.146ns, net 0.476ns, 23% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556 + O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.476 r 3.032 encrypted_text(0) + O_data_hs_p[3]_syn_2 path2reg 0.000 3.032 + Arrival time 3.032 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[2] 0.000 0.000 + O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + capture clock edge 2.314 4.171 +--------------------------------------------------------------------------------------------------------- + cell setup -0.061 4.110 + clock uncertainty -0.000 4.110 + clock recovergence pessimism 0.000 4.110 + Required time 4.110 +--------------------------------------------------------------------------------------------------------- + Slack 1.078ns + +--------------------------------------------------------------------------------------------------------- + +Paths for end point O_data_hs_p[0]_syn_2 (4 paths) +--------------------------------------------------------------------------------------------------------- + Slack (setup check): 1.028 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) + Clock group: clock_source + Process: Slow + Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.146 r 2.556 + O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.526 r 3.082 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 3.082 + Arrival time 3.082 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[2] 0.000 0.000 + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + capture clock edge 2.314 4.171 +--------------------------------------------------------------------------------------------------------- + cell setup -0.061 4.110 + clock uncertainty -0.000 4.110 + clock recovergence pessimism 0.000 4.110 + Required time 4.110 +--------------------------------------------------------------------------------------------------------- + Slack 1.028ns --------------------------------------------------------------------------------------------------------- Slack (setup check): 1.075 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Slow Data Path Delay: 0.625ns (logic 0.146ns, net 0.479ns, 23% logic) @@ -4388,17 +4344,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q 0.146 r 2.556 - O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.479 r 3.035 encrypted_text(0) - O_data_hs_p[3]_syn_2 path2reg 0.000 3.035 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.146 r 2.556 + O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.479 r 3.035 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 3.035 Arrival time 3.035 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) capture clock edge 2.314 4.171 --------------------------------------------------------------------------------------------------------- cell setup -0.061 4.110 @@ -4408,6 +4364,40 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack 1.075ns +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): 1.078 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) + Clock group: clock_source + Process: Slow + Data Path Delay: 0.622ns (logic 0.146ns, net 0.476ns, 23% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.146 r 2.556 + O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.476 r 3.032 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 3.032 + Arrival time 3.032 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[2] 0.000 0.000 + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + capture clock edge 2.314 4.171 +--------------------------------------------------------------------------------------------------------- + cell setup -0.061 4.110 + clock uncertainty -0.000 4.110 + clock recovergence pessimism 0.000 4.110 + Required time 4.110 +--------------------------------------------------------------------------------------------------------- + Slack 1.078ns + --------------------------------------------------------------------------------------------------------- Hold checks: @@ -4415,8 +4405,8 @@ Hold checks: Paths for end point O_data_hs_p[2]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.401 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[2]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic) @@ -4426,11 +4416,11 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138 - O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138 + O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0) O_data_hs_p[2]_syn_2 path2reg 0.000 2.363 Arrival time 2.363 (0 lvl) @@ -4449,7 +4439,7 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.401 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (rising edge triggered by clock S_clk_x2) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_data_hs_p[2]_syn_2.do[0] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast @@ -4460,10 +4450,10 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.q[0] clk2q 0.109 r 2.138 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138 O_data_hs_p[2]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.225 r 2.363 encrypted_text(0) O_data_hs_p[2]_syn_2 path2reg 0.000 2.363 Arrival time 2.363 (0 lvl) @@ -4482,25 +4472,25 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.623 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) + Slack (hold check): 0.517 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast - Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic) + Data Path Delay: 0.450ns (logic 0.109ns, net 0.341ns, 24% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138 - O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.447 r 2.585 encrypted_text(0) - O_data_hs_p[2]_syn_2 path2reg 0.000 2.585 - Arrival time 2.585 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138 + O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.341 r 2.479 encrypted_text(0) + O_data_hs_p[2]_syn_2 path2reg 0.000 2.479 + Arrival time 2.479 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 @@ -4512,15 +4502,15 @@ Paths for end point O_data_hs_p[2]_syn_2 (4 paths) clock recovergence pessimism 0.000 1.962 Required time 1.962 --------------------------------------------------------------------------------------------------------- - Slack 0.623ns + Slack 0.517ns --------------------------------------------------------------------------------------------------------- -Paths for end point O_data_hs_p[3]_syn_2 (4 paths) +Paths for end point O_data_hs_p[0]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.498 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[3]_syn_2.do[0] (rising edge triggered by clock S_clk_x4) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic) @@ -4530,17 +4520,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q 0.109 r 2.138 - O_data_hs_p[3]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.322 r 2.460 encrypted_text(0) - O_data_hs_p[3]_syn_2 path2reg 0.000 2.460 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138 + O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.322 r 2.460 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 2.460 Arrival time 2.460 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) capture clock edge 0.000 1.965 --------------------------------------------------------------------------------------------------------- cell hold -0.003 1.962 @@ -4550,11 +4540,45 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- Slack 0.498ns +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 0.507 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) + Clock group: clock_source + Process: Fast + Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.029 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138 + O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 2.469 + Arrival time 2.469 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[2] 0.000 0.000 + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + capture clock edge 0.000 1.965 +--------------------------------------------------------------------------------------------------------- + cell hold -0.003 1.962 + clock uncertainty 0.000 1.962 + clock recovergence pessimism 0.000 1.962 + Required time 1.962 +--------------------------------------------------------------------------------------------------------- + Slack 0.507ns + --------------------------------------------------------------------------------------------------------- Slack (hold check): 0.508 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast Data Path Delay: 0.441ns (logic 0.109ns, net 0.332ns, 24% logic) @@ -4564,17 +4588,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q 0.109 r 2.138 - O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0) - O_data_hs_p[3]_syn_2 path2reg 0.000 2.470 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138 + O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net (fanout = 1) 0.332 r 2.470 encrypted_text(0) + O_data_hs_p[0]_syn_2 path2reg 0.000 2.470 Arrival time 2.470 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) capture clock edge 0.000 1.965 --------------------------------------------------------------------------------------------------------- cell hold -0.003 1.962 @@ -4586,29 +4610,31 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.614 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) +Paths for end point O_data_hs_p[1]_syn_2 (4 paths) +--------------------------------------------------------------------------------------------------------- + Slack (hold check): 0.498 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast - Data Path Delay: 0.547ns (logic 0.109ns, net 0.438ns, 19% logic) + Data Path Delay: 0.431ns (logic 0.109ns, net 0.322ns, 25% logic) Logic Levels: 0 Point Type Incr Path Info --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138 - O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.438 r 2.576 encrypted_text(0) - O_data_hs_p[3]_syn_2 path2reg 0.000 2.576 - Arrival time 2.576 (0 lvl) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q 0.109 r 2.138 + O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.322 r 2.460 encrypted_text(0) + O_data_hs_p[1]_syn_2 path2reg 0.000 2.460 + Arrival time 2.460 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) + O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) capture clock edge 0.000 1.965 --------------------------------------------------------------------------------------------------------- cell hold -0.003 1.962 @@ -4616,15 +4642,13 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths) clock recovergence pessimism 0.000 1.962 Required time 1.962 --------------------------------------------------------------------------------------------------------- - Slack 0.614ns + Slack 0.498ns --------------------------------------------------------------------------------------------------------- -Paths for end point O_data_hs_p[1]_syn_2 (4 paths) ---------------------------------------------------------------------------------------------------------- Slack (hold check): 0.507 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4) + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast Data Path Delay: 0.440ns (logic 0.109ns, net 0.331ns, 24% logic) @@ -4634,11 +4658,11 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- source latency 0.000 0.000 u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.q[1] clk2q 0.109 r 2.138 - O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0) + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q 0.109 r 2.138 + O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.331 r 2.469 encrypted_text(0) O_data_hs_p[1]_syn_2 path2reg 0.000 2.469 Arrival time 2.469 (0 lvl) @@ -4656,46 +4680,12 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 0.624 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4) - Clock group: clock_source - Process: Fast - Data Path Delay: 0.557ns (logic 0.109ns, net 0.448ns, 19% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.029 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q 0.109 r 2.138 - O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net (fanout = 1) 0.448 r 2.586 encrypted_text(0) - O_data_hs_p[1]_syn_2 path2reg 0.000 2.586 - Arrival time 2.586 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[2] 0.000 0.000 - O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17) - capture clock edge 0.000 1.965 ---------------------------------------------------------------------------------------------------------- - cell hold -0.003 1.962 - clock uncertainty 0.000 1.962 - clock recovergence pessimism 0.000 1.962 - Required time 1.962 ---------------------------------------------------------------------------------------------------------- - Slack 0.624ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 0.653 ns + Slack (hold check): 0.629 ns Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4) Clock group: clock_source Process: Fast - Data Path Delay: 0.586ns (logic 0.109ns, net 0.477ns, 18% logic) + Data Path Delay: 0.562ns (logic 0.109ns, net 0.453ns, 19% logic) Logic Levels: 0 Point Type Incr Path Info @@ -4706,9 +4696,9 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q 0.109 r 2.138 - O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.477 r 2.615 encrypted_text(0) - O_data_hs_p[1]_syn_2 path2reg 0.000 2.615 - Arrival time 2.615 (0 lvl) + O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net (fanout = 1) 0.453 r 2.591 encrypted_text(0) + O_data_hs_p[1]_syn_2 path2reg 0.000 2.591 + Arrival time 2.591 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[2] 0.000 0.000 @@ -4720,7 +4710,7 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths) clock recovergence pessimism 0.000 1.962 Required time 1.962 --------------------------------------------------------------------------------------------------------- - Slack 0.653ns + Slack 0.629ns --------------------------------------------------------------------------------------------------------- @@ -4730,52 +4720,18 @@ Timing constraint: clock: S_clk_x4_90d Clock = S_clk_x4_90d, period 2.314ns, rising at 0.578ns, falling at 1.735ns 2 endpoints analyzed totally, and 4 paths analyzed -2 errors detected : 2 setup errors (TNS = -0.811), 0 hold errors (TNS = 0.000) -Minimum period is 3.125ns +2 errors detected : 2 setup errors (TNS = -0.512), 0 hold errors (TNS = 0.000) +Minimum period is 2.826ns --------------------------------------------------------------------------------------------------------- Paths for end point O_clk_hs_p_syn_2 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (setup check): -0.811 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d) - Clock group: clock_source - Process: Slow - Data Path Delay: 0.775ns (logic 0.146ns, net 0.629ns, 18% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.410 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556 - O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.629 r 3.185 encrypted_text(0) - O_clk_hs_p_syn_2 path2reg 0.000 3.185 - Arrival time 3.185 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[3] 0.000 0.000 - O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20) - capture clock edge 0.578 2.435 ---------------------------------------------------------------------------------------------------------- - cell setup -0.061 2.374 - clock uncertainty -0.000 2.374 - clock recovergence pessimism 0.000 2.374 - Required time 2.374 ---------------------------------------------------------------------------------------------------------- - Slack -0.811ns - ---------------------------------------------------------------------------------------------------------- - - Slack (setup check): -0.708 ns + Slack (setup check): -0.512 ns Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d) Clock group: clock_source Process: Slow - Data Path Delay: 0.672ns (logic 0.146ns, net 0.526ns, 21% logic) + Data Path Delay: 0.476ns (logic 0.146ns, net 0.330ns, 30% logic) Logic Levels: 0 Point Type Incr Path Info @@ -4786,9 +4742,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths) launch clock edge 0.000 2.410 --------------------------------------------------------------------------------------------------------- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556 - O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.526 r 3.082 encrypted_text(0) - O_clk_hs_p_syn_2 path2reg 0.000 3.082 - Arrival time 3.082 (0 lvl) + O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.330 r 2.886 encrypted_text(0) + O_clk_hs_p_syn_2 path2reg 0.000 2.886 + Arrival time 2.886 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[3] 0.000 0.000 @@ -4800,7 +4756,41 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths) clock recovergence pessimism 0.000 2.374 Required time 2.374 --------------------------------------------------------------------------------------------------------- - Slack -0.708ns + Slack -0.512ns + +--------------------------------------------------------------------------------------------------------- + + Slack (setup check): -0.508 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d) + Clock group: clock_source + Process: Slow + Data Path Delay: 0.472ns (logic 0.146ns, net 0.326ns, 30% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.410 2.410 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.410 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.146 r 2.556 + O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.326 r 2.882 encrypted_text(0) + O_clk_hs_p_syn_2 path2reg 0.000 2.882 + Arrival time 2.882 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[3] 0.000 0.000 + O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.857 1.857 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20) + capture clock edge 0.578 2.435 +--------------------------------------------------------------------------------------------------------- + cell setup -0.061 2.374 + clock uncertainty -0.000 2.374 + clock recovergence pessimism 0.000 2.374 + Required time 2.374 +--------------------------------------------------------------------------------------------------------- + Slack -0.508ns --------------------------------------------------------------------------------------------------------- @@ -4808,46 +4798,12 @@ Hold checks: --------------------------------------------------------------------------------------------------------- Paths for end point O_clk_hs_p_syn_2 (2 paths) --------------------------------------------------------------------------------------------------------- - Slack (hold check): 2.282 ns - Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) - End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d) - Clock group: clock_source - Process: Fast - Data Path Delay: 0.479ns (logic 0.109ns, net 0.370ns, 22% logic) - Logic Levels: 0 - - Point Type Incr Path Info ---------------------------------------------------------------------------------------------------------- - source latency 0.000 0.000 - u_pll/pll_inst.clkc[1] 0.000 0.000 - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) - launch clock edge 0.000 2.029 ---------------------------------------------------------------------------------------------------------- - u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138 - O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.370 r 2.508 encrypted_text(0) - O_clk_hs_p_syn_2 path2reg 0.000 2.508 - Arrival time 2.508 (0 lvl) - - source latency 0.000 0.000 - u_pll/pll_inst.clkc[3] 0.000 0.000 - O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20) - capture clock edge -1.736 0.229 ---------------------------------------------------------------------------------------------------------- - cell hold -0.003 0.226 - clock uncertainty 0.000 0.226 - clock recovergence pessimism 0.000 0.226 - Required time 0.226 ---------------------------------------------------------------------------------------------------------- - Slack 2.282ns - ---------------------------------------------------------------------------------------------------------- - - Slack (hold check): 2.359 ns + Slack (hold check): 2.128 ns Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) End Point: O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d) Clock group: clock_source Process: Fast - Data Path Delay: 0.556ns (logic 0.109ns, net 0.447ns, 19% logic) + Data Path Delay: 0.325ns (logic 0.109ns, net 0.216ns, 33% logic) Logic Levels: 0 Point Type Incr Path Info @@ -4858,9 +4814,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths) launch clock edge 0.000 2.029 --------------------------------------------------------------------------------------------------------- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138 - O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.447 r 2.585 encrypted_text(0) - O_clk_hs_p_syn_2 path2reg 0.000 2.585 - Arrival time 2.585 (0 lvl) + O_clk_hs_p_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.216 r 2.354 encrypted_text(0) + O_clk_hs_p_syn_2 path2reg 0.000 2.354 + Arrival time 2.354 (0 lvl) source latency 0.000 0.000 u_pll/pll_inst.clkc[3] 0.000 0.000 @@ -4872,7 +4828,41 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths) clock recovergence pessimism 0.000 0.226 Required time 0.226 --------------------------------------------------------------------------------------------------------- - Slack 2.359ns + Slack 2.128ns + +--------------------------------------------------------------------------------------------------------- + + Slack (hold check): 2.137 ns + Start Point: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2) + End Point: O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d) + Clock group: clock_source + Process: Fast + Data Path Delay: 0.334ns (logic 0.109ns, net 0.225ns, 32% logic) + Logic Levels: 0 + + Point Type Incr Path Info +--------------------------------------------------------------------------------------------------------- + source latency 0.000 0.000 + u_pll/pll_inst.clkc[1] 0.000 0.000 + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net 2.029 2.029 ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16) + launch clock edge 0.000 2.029 +--------------------------------------------------------------------------------------------------------- + u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q 0.109 r 2.138 + O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net (fanout = 2) 0.225 r 2.363 encrypted_text(0) + O_clk_hs_p_syn_2 path2reg 0.000 2.363 + Arrival time 2.363 (0 lvl) + + source latency 0.000 0.000 + u_pll/pll_inst.clkc[3] 0.000 0.000 + O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net 1.965 1.965 ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20) + capture clock edge -1.736 0.229 +--------------------------------------------------------------------------------------------------------- + cell hold -0.003 0.226 + clock uncertainty 0.000 0.226 + clock recovergence pessimism 0.000 0.226 + Required time 0.226 +--------------------------------------------------------------------------------------------------------- + Slack 2.137ns --------------------------------------------------------------------------------------------------------- @@ -4880,22 +4870,22 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths) ========================================================================================================= Timing summary: --------------------------------------------------------------------------------------------------------- -Constraint path number: 364350 (STA coverage = 91.56%) +Constraint path number: 361754 (STA coverage = 91.81%) Timing violations: 2 setup errors, and 0 hold errors. -Minimal setup slack: -0.811, minimal hold slack: 0.067 +Minimal setup slack: -0.512, minimal hold slack: 0.067 Timing group statistics: Clock constraints: Clock Name Min Period Max Freq Skew Fanout TNS - S_clk (108.0MHz) 9.231ns 108.331MHz 0.326ns 1825 0.000ns - a_pclk (48.0MHz) 12.828ns 77.954MHz 0.326ns 1432 0.000ns - b_pclk (48.0MHz) 10.513ns 95.120MHz 0.326ns 1342 0.000ns - clk_adc (6.0MHz) 159.250ns 6.279MHz 0.326ns 1235 0.000ns - a_sclk (168.0MHz) 1.906ns 524.659MHz 0.254ns 71 0.000ns - b_sclk (168.0MHz) 2.080ns 480.769MHz 0.326ns 70 0.000ns - S_clk_x2 (216.0MHz) 2.210ns 452.489MHz 0.480ns 22 0.000ns - S_clk_x4 (432.0MHz) 1.435ns 696.864MHz 0.018ns 4 0.000ns - S_clk_x4_90d (432.0MHz) 3.125ns 320.000MHz 0.000ns 1 -0.811ns + S_clk (108.0MHz) 9.216ns 108.507MHz 0.326ns 1798 0.000ns + a_pclk (48.0MHz) 12.866ns 77.724MHz 0.326ns 1415 0.000ns + b_pclk (48.0MHz) 9.922ns 100.786MHz 0.326ns 1345 0.000ns + clk_adc (6.0MHz) 159.224ns 6.280MHz 0.326ns 989 0.000ns + b_sclk (168.0MHz) 2.151ns 464.900MHz 0.326ns 72 0.000ns + a_sclk (168.0MHz) 1.860ns 537.634MHz 0.326ns 70 0.000ns + S_clk_x2 (216.0MHz) 2.026ns 493.583MHz 0.480ns 22 0.000ns + S_clk_x4 (432.0MHz) 1.399ns 714.796MHz 0.018ns 4 0.000ns + S_clk_x4_90d (432.0MHz) 2.826ns 353.857MHz 0.000ns 1 -0.512ns Minimum input arrival time before clock: no constraint path Maximum output required time after clock: no constraint path Maximum combinational path delay: no constraint path @@ -4910,34 +4900,12 @@ Warning: No clock constraint on 3 clock net(s): Check Type: MAX ---------------------------------------------------------------------------------------------------- Path Num Constraint - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ] - 0 set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[3]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d} ] - 0 set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[1]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2} ] - 1 set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 1 set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ] 2 set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ] Check Type: MIN ---------------------------------------------------------------------------------------------------- Path Num Constraint - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ] - 1 set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 1 set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ] 2 set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ] diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm index d454a1f..4430589 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm @@ -1,1299 +1,1299 @@ eagle_s20 -13 4881 4737 2689 26496 364350 2 0 --0.811 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 54 12 +13 4871 4727 2781 25764 361754 2 0 +-0.512 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 32 12 clock: a_lvds_clk_p 15 0 0 0 clock: a_pclk -23 105576 6154 2 +23 104162 6178 2 Setup check 33 3 -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -33 8.005000 691 3 -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk -sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -35 8.005000 22.929000 14.924000 7 7 +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +33 7.967000 659 3 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +35 7.967000 22.929000 14.962000 7 10 sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk -sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -85 8.005000 22.929000 14.924000 7 7 -sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk -sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 -135 8.005000 22.929000 14.924000 7 9 -sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] - - -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -189 8.153000 659 3 -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -191 8.153000 22.929000 14.776000 7 7 -sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -241 8.153000 22.929000 14.776000 7 7 -sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 -291 8.153000 22.929000 14.776000 7 9 -sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] +91 7.967000 22.929000 14.962000 7 10 +sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] + +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 +147 7.967000 22.929000 14.962000 7 10 +sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -345 12.557000 12 3 -Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -347 12.557000 22.762000 10.205000 6 6 -u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 reg14_syn_50.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5086 ua_lvds_rx/reg8_syn_184.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_10 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.c[1] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_12 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[50]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1] +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +203 7.968000 691 3 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +205 7.968000 22.929000 14.961000 7 10 +sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] -Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -393 13.869000 22.762000 8.893000 5 5 -u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 reg14_syn_50.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3436 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.a[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +261 7.968000 22.929000 14.961000 7 10 +sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] -Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 -437 14.080000 22.762000 8.682000 5 5 -u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.a[1] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4536 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.b[0] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_49.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 +317 7.968000 22.929000 14.961000 7 10 +sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] u_bus_top/reg0_syn_156.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1233 u_bus_top/reg0_syn_158.a[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg6_syn_35_syn_2.b[0] +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] + + +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +373 11.979000 85 3 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +375 11.979000 22.929000 10.950000 6 6 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0] U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[4]_syn_19_syn_2.d[0] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_34 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.b[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] + +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +423 12.328000 22.929000 10.601000 6 6 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.b[0] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_35 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] + +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +sampling_fe_a/u_sort/u_data_prebuffer/reg0_syn_28.clk +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720 +471 12.623000 22.929000 10.306000 6 6 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0] U_rgb_to_csi_pakage/U_crc16_24b/O_crc_b[3]_syn_5_syn_2.d[0] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_35 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_80.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5471 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_20.c[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[57]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_16.a[1] +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_6 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_720.c[1] Hold check -481 3 -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -483 0.080000 8 3 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -485 0.080000 2.183000 2.263000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_data[71] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7] +519 3 +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +521 0.080000 10 3 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_627.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_627.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +523 0.080000 2.183000 2.263000 1 1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[55] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[8] -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -523 0.251000 2.183000 2.434000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_data[67] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3] +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +561 0.195000 2.183000 2.378000 1 1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[51] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[4] -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 -561 0.336000 2.183000 2.519000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_data[68] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4] +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_676.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1 +599 0.205000 2.183000 2.388000 1 1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[53] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.addra[6] -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -599 0.089000 10 3 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -601 0.089000 2.183000 2.272000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[18] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11] - -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +637 0.130000 10 3 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 639 0.130000 2.183000 2.313000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[14] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7] +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[13] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[6] -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk -sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 -677 0.234000 2.183000 2.417000 1 1 -sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12] +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_data_tmp[7]_syn_8.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_data_tmp[7]_syn_8.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +677 0.246000 2.183000 2.429000 1 1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[15] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[8] + +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_639.clk +sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1 +715 0.336000 2.183000 2.519000 1 1 +sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[11] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.addra[4] -Endpoint: u0_test_en/reg0_syn_26 -715 0.167000 1 1 -Timing path: u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk->u0_test_en/reg0_syn_26 -u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk -u0_test_en/reg0_syn_26 -717 0.167000 2.191000 2.358000 0 1 -u0_test_en/signal_from[0] u0_test_en/reg0_syn_26.mi[0] +Endpoint: u0_test_en/reg0_syn_16 +753 0.167000 1 1 +Timing path: u_bus_top/u_local_bus_slve_cis/reg46_syn_230.clk->u0_test_en/reg0_syn_16 +u_bus_top/u_local_bus_slve_cis/reg46_syn_230.clk +u0_test_en/reg0_syn_16 +755 0.167000 2.191000 2.358000 0 1 +u0_test_en/signal_from[0] u0_test_en/reg0_syn_16.mi[0] clock: a_sclk -753 698 282 2 +791 706 282 2 Setup check -763 3 +801 3 Endpoint: ua_lvds_rx/rx_clk_sync_reg_syn_5 -763 4.046000 7 3 -Timing path: ua_lvds_rx/reg7_syn_33.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 -ua_lvds_rx/reg7_syn_33.clk +801 4.092000 7 3 +Timing path: ua_lvds_rx/reg7_syn_36.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 +ua_lvds_rx/reg7_syn_36.clk ua_lvds_rx/rx_clk_sync_reg_syn_5 -765 4.046000 8.182000 4.136000 2 2 +803 4.092000 8.210000 4.118000 2 2 ua_lvds_rx/rx_clk_sft[1] ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0] ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] -Timing path: ua_lvds_rx/reg7_syn_24.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 -ua_lvds_rx/reg7_syn_24.clk +Timing path: ua_lvds_rx/reg7_syn_39.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 +ua_lvds_rx/reg7_syn_39.clk ua_lvds_rx/rx_clk_sync_reg_syn_5 -801 4.086000 8.182000 4.096000 2 2 -ua_lvds_rx/rx_clk_sft[3] ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] -ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] - -Timing path: ua_lvds_rx/reg7_syn_30.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 -ua_lvds_rx/reg7_syn_30.clk -ua_lvds_rx/rx_clk_sync_reg_syn_5 -837 4.194000 8.182000 3.988000 2 2 +839 4.099000 8.210000 4.111000 2 2 ua_lvds_rx/rx_clk_sft[0] ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] - -Endpoint: ua_lvds_rx/ramread0_syn_88 -873 4.116000 2 2 -Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_88 -ua_lvds_rx/reg16_syn_31.clk -ua_lvds_rx/ramread0_syn_88 -875 4.116000 8.189000 4.073000 1 1 -ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_88.c[0] - -Timing path: ua_lvds_rx/reg8_syn_157.clk->ua_lvds_rx/ramread0_syn_88 -ua_lvds_rx/reg8_syn_157.clk -ua_lvds_rx/ramread0_syn_88 -909 5.160000 8.189000 3.029000 1 1 -ua_lvds_rx/para_data[22] ua_lvds_rx/ramread0_syn_88.c[1] +Timing path: ua_lvds_rx/reg7_syn_39.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5 +ua_lvds_rx/reg7_syn_39.clk +ua_lvds_rx/rx_clk_sync_reg_syn_5 +875 4.261000 8.210000 3.949000 2 2 +ua_lvds_rx/rx_clk_sft[3] ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] +ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] -Endpoint: ua_lvds_rx/ramread0_syn_46 -943 4.116000 2 2 -Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_46 -ua_lvds_rx/reg16_syn_31.clk -ua_lvds_rx/ramread0_syn_46 -945 4.116000 8.189000 4.073000 1 1 -ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_46.c[0] +Endpoint: ua_lvds_rx/reg8_syn_174 +911 4.121000 9 3 +Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_174 +ua_lvds_rx/sync0_reg_syn_4.clk +ua_lvds_rx/reg8_syn_174 +913 4.121000 8.182000 4.061000 1 1 +ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_174.d[1] -Timing path: ua_lvds_rx/reg8_syn_153.clk->ua_lvds_rx/ramread0_syn_46 -ua_lvds_rx/reg8_syn_153.clk -ua_lvds_rx/ramread0_syn_46 -979 4.574000 8.189000 3.615000 1 1 -ua_lvds_rx/para_data[10] ua_lvds_rx/ramread0_syn_46.c[1] +Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_174 +ua_lvds_rx/sync0_reg_syn_4.clk +ua_lvds_rx/reg8_syn_174 +947 4.121000 8.182000 4.061000 1 1 +ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_174.d[0] + +Timing path: ua_lvds_rx/reg8_syn_174.clk->ua_lvds_rx/reg8_syn_174 +ua_lvds_rx/reg8_syn_174.clk +ua_lvds_rx/reg8_syn_174 +981 4.198000 8.182000 3.984000 1 1 +ua_lvds_rx/para_data[20] ua_lvds_rx/reg8_syn_174.a[1] + + +Endpoint: ua_lvds_rx/reg8_syn_160 +1015 4.121000 9 3 +Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_160 +ua_lvds_rx/sync0_reg_syn_4.clk +ua_lvds_rx/reg8_syn_160 +1017 4.121000 8.182000 4.061000 1 1 +ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_160.d[1] + +Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_160 +ua_lvds_rx/sync0_reg_syn_4.clk +ua_lvds_rx/reg8_syn_160 +1051 4.121000 8.182000 4.061000 1 1 +ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_160.d[0] + +Timing path: ua_lvds_rx/reg8_syn_160.clk->ua_lvds_rx/reg8_syn_160 +ua_lvds_rx/reg8_syn_160.clk +ua_lvds_rx/reg8_syn_160 +1085 4.198000 8.182000 3.984000 1 1 +ua_lvds_rx/para_data[11] ua_lvds_rx/reg8_syn_160.a[1] Hold check -1013 3 -Endpoint: ua_lvds_rx/ramread0_syn_102 -1015 0.092000 2 2 -Timing path: ua_lvds_rx/reg3_syn_184.clk->ua_lvds_rx/ramread0_syn_102 -ua_lvds_rx/reg3_syn_184.clk -ua_lvds_rx/ramread0_syn_102 -1017 0.092000 2.157000 2.249000 1 1 -ua_lvds_rx/para_data[26] ua_lvds_rx/ramread0_syn_102.c[1] +1119 3 +Endpoint: ua_lvds_rx/ramread0_syn_18 +1121 0.092000 2 2 +Timing path: ua_lvds_rx/reg3_syn_163.clk->ua_lvds_rx/ramread0_syn_18 +ua_lvds_rx/reg3_syn_163.clk +ua_lvds_rx/ramread0_syn_18 +1123 0.092000 2.157000 2.249000 1 1 +ua_lvds_rx/para_data[2] ua_lvds_rx/ramread0_syn_18.c[1] -Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102 +Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_18 ua_lvds_rx/reg16_syn_31.clk -ua_lvds_rx/ramread0_syn_102 -1051 0.700000 2.157000 2.857000 1 1 -ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_102.c[0] +ua_lvds_rx/ramread0_syn_18 +1157 0.316000 2.157000 2.473000 1 1 +ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_18.c[0] -Endpoint: ua_lvds_rx/ramread0_syn_102 -1085 0.092000 2 2 -Timing path: ua_lvds_rx/reg3_syn_184.clk->ua_lvds_rx/ramread0_syn_102 -ua_lvds_rx/reg3_syn_184.clk -ua_lvds_rx/ramread0_syn_102 -1087 0.092000 2.157000 2.249000 1 1 -ua_lvds_rx/para_data[25] ua_lvds_rx/ramread0_syn_102.b[1] +Endpoint: ua_lvds_rx/ramread0_syn_18 +1191 0.092000 2 2 +Timing path: ua_lvds_rx/reg3_syn_163.clk->ua_lvds_rx/ramread0_syn_18 +ua_lvds_rx/reg3_syn_163.clk +ua_lvds_rx/ramread0_syn_18 +1193 0.092000 2.157000 2.249000 1 1 +ua_lvds_rx/para_data[1] ua_lvds_rx/ramread0_syn_18.b[1] -Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_102 -ua_lvds_rx/reg16_syn_33.clk -ua_lvds_rx/ramread0_syn_102 -1121 0.403000 2.157000 2.560000 1 1 -ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_102.b[0] - - -Endpoint: ua_lvds_rx/ramread0_syn_102 -1155 0.167000 2 2 -Timing path: ua_lvds_rx/reg3_syn_181.clk->ua_lvds_rx/ramread0_syn_102 -ua_lvds_rx/reg3_syn_181.clk -ua_lvds_rx/ramread0_syn_102 -1157 0.167000 2.187000 2.354000 1 1 -ua_lvds_rx/para_data[24] ua_lvds_rx/ramread0_syn_102.a[1] - -Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102 +Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_18 ua_lvds_rx/reg16_syn_31.clk -ua_lvds_rx/ramread0_syn_102 -1191 0.412000 2.187000 2.599000 1 1 -ua_lvds_rx/wcnt[0] ua_lvds_rx/ramread0_syn_102.a[0] +ua_lvds_rx/ramread0_syn_18 +1227 0.517000 2.157000 2.674000 1 1 +ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_18.b[0] + + +Endpoint: ua_lvds_rx/ramread0_syn_46 +1261 0.092000 2 2 +Timing path: ua_lvds_rx/reg3_syn_168.clk->ua_lvds_rx/ramread0_syn_46 +ua_lvds_rx/reg3_syn_168.clk +ua_lvds_rx/ramread0_syn_46 +1263 0.092000 2.157000 2.249000 1 1 +ua_lvds_rx/para_data[10] ua_lvds_rx/ramread0_syn_46.c[1] + +Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_46 +ua_lvds_rx/reg16_syn_31.clk +ua_lvds_rx/ramread0_syn_46 +1297 0.191000 2.157000 2.348000 1 1 +ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_46.c[0] clock: b_lvds_clk_p -1227 0 0 0 +1333 0 0 0 clock: b_pclk -1235 101792 5792 2 +1341 105460 5884 2 Setup check -1245 3 -Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -1245 10.320000 139 3 -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -1247 10.320000 22.857000 12.537000 6 8 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -1299 10.320000 22.857000 12.537000 6 8 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 -1351 10.553000 22.857000 12.304000 6 7 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] - - +1351 3 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 -1401 10.320000 171 3 +1351 10.911000 171 3 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 -1403 10.320000 22.857000 12.537000 6 8 +1353 10.911000 22.857000 11.946000 6 8 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 -1455 10.320000 22.857000 12.537000 6 8 +1405 10.911000 22.857000 11.946000 6 8 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 -1507 10.553000 22.857000 12.304000 6 7 -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] +1457 10.917000 22.857000 11.940000 6 9 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1] -sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] -Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_89 -1557 12.376000 214 3 -Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_73.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89 -exdev_ctl_b/u_gen_sp/reg9_syn_73.clk -exdev_ctl_b/u_gen_sp/reg0_syn_89 -1559 12.376000 22.858000 10.482000 8 11 -exdev_ctl_b/u_gen_sp/sp_t_d1[0] exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] -exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci -exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci -exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci -exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] -exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +1511 10.979000 139 3 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +1513 10.979000 22.857000 11.878000 6 8 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] -Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_77.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89 -exdev_ctl_b/u_gen_sp/reg9_syn_77.clk -exdev_ctl_b/u_gen_sp/reg0_syn_89 -1617 12.465000 22.858000 10.393000 8 11 -exdev_ctl_b/u_gen_sp/sp_t_d1[1] exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] -exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci -exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci -exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci -exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] -exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +1565 10.979000 22.857000 11.878000 6 8 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] -Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_97.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89 -exdev_ctl_b/u_gen_sp/reg9_syn_97.clk -exdev_ctl_b/u_gen_sp/reg0_syn_89 -1675 12.546000 22.858000 10.312000 8 10 -exdev_ctl_b/u_gen_sp/sp_t_d1[3] exdev_ctl_b/u_gen_sp/sub1_syn_103.a[0] -exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci -exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci -exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] -exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0] -exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] -exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 +1617 10.985000 22.857000 11.872000 6 9 +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_pic_cnt/reg1_syn_406.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 reg36_syn_108.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1262.b[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] + + +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +1671 11.503000 21 3 +Timing path: ub_lvds_rx/reg4_syn_22.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +ub_lvds_rx/reg4_syn_22.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +1673 11.503000 22.857000 11.354000 5 5 +ub_lvds_rx/rcnt[0] ub_lvds_rx/ramread0_syn_73.a[1] +ub_lvds_rx/rdata[19] u_pixel_cdc/reg2_syn_106.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229 sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] + +Timing path: ub_lvds_rx/reg4_syn_22.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +ub_lvds_rx/reg4_syn_22.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +1719 11.589000 22.857000 11.268000 5 5 +ub_lvds_rx/rcnt[0] ub_lvds_rx/ramread0_syn_73.a[0] +ub_lvds_rx/rdata[18] u_pixel_cdc/reg2_syn_106.c[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229 sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] + +Timing path: ub_lvds_rx/reg4_syn_22.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +ub_lvds_rx/reg4_syn_22.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51 +1765 11.795000 22.857000 11.062000 5 5 +ub_lvds_rx/rcnt[0] ub_lvds_rx/ramread0_syn_86.a[0] +ub_lvds_rx/rdata[20] u_pixel_cdc/reg2_syn_106.d[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1227 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_452.a[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1229 sampling_fe_b/u_sort/u_transfer_300_to_200/data_e_b5[5]_syn_5.d[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[2]_syn_4 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg2_syn_51.d[0] Hold check -1731 3 -Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -1733 0.130000 10 3 -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -1735 0.130000 2.183000 2.313000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[28] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11] +1811 3 +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +1813 0.089000 10 3 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_743.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg6_syn_743.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +1815 0.089000 2.183000 2.272000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[56] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[9] -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[17]_syn_17.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_addr_tmp[17]_syn_17.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +1853 0.271000 2.183000 2.454000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[59] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[12] + +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_728.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_728.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1 +1891 0.311000 2.183000 2.494000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[51] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.addra[4] + + +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +1929 0.089000 10 3 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +1931 0.089000 2.183000 2.272000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] + +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_682.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_682.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +1969 0.171000 2.183000 2.354000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[35] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[8] + +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_622.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 +2007 0.196000 2.183000 2.379000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[31] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[4] + + +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +2045 0.114000 10 3 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_704.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_704.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +2047 0.114000 2.183000 2.297000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[109] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[12] + +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_707.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_707.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +2085 0.292000 2.183000 2.475000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[106] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[9] + +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -1773 0.195000 2.183000 2.378000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[20] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 -1811 0.248000 2.183000 2.431000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] - - -Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -1849 0.130000 8 3 -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -1851 0.130000 2.183000 2.313000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[19] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -1889 0.232000 2.183000 2.415000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[20] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4] - -Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk -sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 -1927 0.236000 2.183000 2.419000 1 1 -sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[21] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5] - - -Endpoint: exdev_ctl_b/reg3_syn_190 -1965 0.167000 1 1 -Timing path: u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk->exdev_ctl_b/reg3_syn_190 -u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk -exdev_ctl_b/reg3_syn_190 -1967 0.167000 2.191000 2.358000 0 1 -u_bus_top/u_local_bus_slve_cis/reg21[2] exdev_ctl_b/reg3_syn_190.mi[1] +sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1 +2123 0.312000 2.183000 2.495000 1 1 +sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[105] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.addra[8] clock: b_sclk -2003 714 282 2 +2161 706 282 2 Setup check -2013 3 -Endpoint: ub_lvds_rx/reg3_syn_179 -2013 3.872000 5 3 -Timing path: ub_lvds_rx/reg8_syn_219.clk->ub_lvds_rx/reg3_syn_179 -ub_lvds_rx/reg8_syn_219.clk -ub_lvds_rx/reg3_syn_179 -2015 3.872000 8.048000 4.176000 1 1 -ub_lvds_rx/rx_data[26] ub_lvds_rx/reg3_syn_179.b[0] - -Timing path: ub_lvds_rx/reg8_syn_163.clk->ub_lvds_rx/reg3_syn_179 -ub_lvds_rx/reg8_syn_163.clk -ub_lvds_rx/reg3_syn_179 -2049 4.385000 8.048000 3.663000 1 1 -ub_lvds_rx/rx_data[27] ub_lvds_rx/reg3_syn_179.c[0] - -Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_179 -ub_lvds_rx/reg8_syn_197.clk -ub_lvds_rx/reg3_syn_179 -2083 4.636000 8.048000 3.412000 1 1 -ub_lvds_rx/sync0 ub_lvds_rx/reg3_syn_179.d[0] - - -Endpoint: ub_lvds_rx/reg3_syn_195 -2117 4.034000 5 3 -Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_195 -ub_lvds_rx/reg8_syn_197.clk -ub_lvds_rx/reg3_syn_195 -2119 4.034000 8.048000 4.014000 1 1 -ub_lvds_rx/rx_data[24] ub_lvds_rx/reg3_syn_195.b[0] - -Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_195 -ub_lvds_rx/reg8_syn_197.clk -ub_lvds_rx/reg3_syn_195 -2153 4.636000 8.048000 3.412000 1 1 -ub_lvds_rx/sync0 ub_lvds_rx/reg3_syn_195.d[0] - -Timing path: ub_lvds_rx/reg8_syn_219.clk->ub_lvds_rx/reg3_syn_195 -ub_lvds_rx/reg8_syn_219.clk -ub_lvds_rx/reg3_syn_195 -2187 4.678000 8.048000 3.370000 1 1 -ub_lvds_rx/rx_data[25] ub_lvds_rx/reg3_syn_195.c[0] - - +2171 3 Endpoint: ub_lvds_rx/rx_clk_sync_reg_syn_5 -2221 4.071000 7 3 -Timing path: ub_lvds_rx/reg7_syn_34.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5 -ub_lvds_rx/reg7_syn_34.clk +2171 3.801000 7 3 +Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5 +ub_lvds_rx/reg7_syn_28.clk ub_lvds_rx/rx_clk_sync_reg_syn_5 -2223 4.071000 8.048000 3.977000 2 2 +2173 3.801000 8.076000 4.275000 2 2 ub_lvds_rx/rx_clk_sft[0] ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5 ub_lvds_rx/reg7_syn_28.clk ub_lvds_rx/rx_clk_sync_reg_syn_5 -2259 4.371000 8.048000 3.677000 1 1 -ub_lvds_rx/rx_clk_sft[5] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1] - -Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5 -ub_lvds_rx/reg7_syn_28.clk -ub_lvds_rx/rx_clk_sync_reg_syn_5 -2293 4.382000 8.048000 3.666000 2 2 -ub_lvds_rx/rx_clk_sft[4] ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0] +2209 3.963000 8.076000 4.113000 2 2 +ub_lvds_rx/rx_clk_sft[3] ub_lvds_rx/rx_clk_sync_reg_syn_5.d[0] ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] +Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5 +ub_lvds_rx/reg7_syn_25.clk +ub_lvds_rx/rx_clk_sync_reg_syn_5 +2245 4.018000 8.076000 4.058000 2 2 +ub_lvds_rx/rx_clk_sft[2] ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] +ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] + + +Endpoint: exdev_ctl_b/u_gen_sp/add2_syn_98 +2281 3.873000 1 1 +Timing path: ub_lvds_rx/reg8_syn_190.clk->exdev_ctl_b/u_gen_sp/add2_syn_98 +ub_lvds_rx/reg8_syn_190.clk +exdev_ctl_b/u_gen_sp/add2_syn_98 +2283 3.873000 7.976000 4.103000 0 1 +ub_lvds_rx/rx_data[32] exdev_ctl_b/u_gen_sp/add2_syn_98.mi[0] + + +Endpoint: ub_lvds_rx/reg8_syn_159 +2317 4.145000 9 3 +Timing path: ub_lvds_rx/reg8_syn_159.clk->ub_lvds_rx/reg8_syn_159 +ub_lvds_rx/reg8_syn_159.clk +ub_lvds_rx/reg8_syn_159 +2319 4.145000 8.112000 3.967000 1 1 +ub_lvds_rx/para_data[23] ub_lvds_rx/reg8_syn_159.a[1] + +Timing path: ub_lvds_rx/reg8_syn_159.clk->ub_lvds_rx/reg8_syn_159 +ub_lvds_rx/reg8_syn_159.clk +ub_lvds_rx/reg8_syn_159 +2353 4.544000 8.112000 3.568000 1 1 +ub_lvds_rx/rx_data[26] ub_lvds_rx/reg8_syn_159.b[1] + +Timing path: ub_lvds_rx/reg8_syn_159.clk->ub_lvds_rx/reg8_syn_159 +ub_lvds_rx/reg8_syn_159.clk +ub_lvds_rx/reg8_syn_159 +2387 4.544000 8.112000 3.568000 1 1 +ub_lvds_rx/rx_data[26] ub_lvds_rx/reg8_syn_159.b[0] + Hold check -2329 3 +2421 3 +Endpoint: ub_lvds_rx/ramread0_syn_32 +2423 0.167000 2 2 +Timing path: ub_lvds_rx/reg3_syn_168.clk->ub_lvds_rx/ramread0_syn_32 +ub_lvds_rx/reg3_syn_168.clk +ub_lvds_rx/ramread0_syn_32 +2425 0.167000 2.096000 2.263000 1 1 +ub_lvds_rx/para_data[4] ub_lvds_rx/ramread0_syn_32.a[1] + +Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/ramread0_syn_32 +ub_lvds_rx/reg16_syn_33.clk +ub_lvds_rx/ramread0_syn_32 +2459 0.315000 2.096000 2.411000 1 1 +ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_32.a[0] + + Endpoint: ub_lvds_rx/ramread0_syn_102 -2331 0.167000 2 2 -Timing path: ub_lvds_rx/reg3_syn_182.clk->ub_lvds_rx/ramread0_syn_102 -ub_lvds_rx/reg3_syn_182.clk +2493 0.167000 2 2 +Timing path: ub_lvds_rx/reg3_syn_185.clk->ub_lvds_rx/ramread0_syn_102 +ub_lvds_rx/reg3_syn_185.clk ub_lvds_rx/ramread0_syn_102 -2333 0.167000 2.096000 2.263000 1 1 +2495 0.167000 2.096000 2.263000 1 1 ub_lvds_rx/para_data[26] ub_lvds_rx/ramread0_syn_102.c[1] Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_102 ub_lvds_rx/reg16_syn_31.clk ub_lvds_rx/ramread0_syn_102 -2367 0.548000 2.096000 2.644000 1 1 +2529 0.393000 2.096000 2.489000 1 1 ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_102.c[0] Endpoint: ub_lvds_rx/ramread0_syn_74 -2401 0.167000 2 2 -Timing path: ub_lvds_rx/reg3_syn_174.clk->ub_lvds_rx/ramread0_syn_74 -ub_lvds_rx/reg3_syn_174.clk +2563 0.167000 2 2 +Timing path: ub_lvds_rx/para_en_reg_syn_5.clk->ub_lvds_rx/ramread0_syn_74 +ub_lvds_rx/para_en_reg_syn_5.clk ub_lvds_rx/ramread0_syn_74 -2403 0.167000 2.096000 2.263000 1 1 +2565 0.167000 2.096000 2.263000 1 1 ub_lvds_rx/para_data[16] ub_lvds_rx/ramread0_syn_74.a[1] -Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_74 -ub_lvds_rx/reg16_syn_31.clk +Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/ramread0_syn_74 +ub_lvds_rx/reg16_syn_33.clk ub_lvds_rx/ramread0_syn_74 -2437 0.207000 2.096000 2.303000 1 1 +2599 0.215000 2.096000 2.311000 1 1 ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_74.a[0] -Endpoint: ub_lvds_rx/ramread0_syn_60 -2471 0.167000 2 2 -Timing path: ub_lvds_rx/reg3_syn_190.clk->ub_lvds_rx/ramread0_syn_60 -ub_lvds_rx/reg3_syn_190.clk -ub_lvds_rx/ramread0_syn_60 -2473 0.167000 2.096000 2.263000 1 1 -ub_lvds_rx/para_data[12] ub_lvds_rx/ramread0_syn_60.a[1] - -Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_60 -ub_lvds_rx/reg16_syn_31.clk -ub_lvds_rx/ramread0_syn_60 -2507 0.324000 2.096000 2.420000 1 1 -ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_60.a[0] - - clock: clock_source -2543 0 0 0 +2635 0 0 0 clock: S_clk -2551 109052 8560 5 +2643 106032 8652 5 Setup check -2561 3 -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 -2561 0.027000 1 1 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 -sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk -sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 -2563 0.027000 4.317000 4.290000 1 2 -sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] -sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0] +2653 3 +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74 +2653 0.042000 1 1 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74 +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74 +2655 0.042000 4.317000 4.275000 1 2 +sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13 sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_74.mi[0] -Endpoint: U_rgb_to_csi_pakage/reg14_syn_101_syn_2 -2603 0.027000 1 1 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->U_rgb_to_csi_pakage/reg14_syn_101_syn_2 -sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk -U_rgb_to_csi_pakage/reg14_syn_101_syn_2 -2605 0.027000 4.317000 4.290000 1 2 -sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] -sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0] +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79 +2695 0.162000 1 1 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79 +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79 +2697 0.162000 4.317000 4.155000 1 2 +sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13 sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/reg5_syn_79.mi[0] -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 -2645 0.027000 1 1 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 -sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk -sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 -2647 0.027000 4.317000 4.290000 1 2 -sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] -sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0] +Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72 +2737 0.165000 1 1 +Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72 +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72 +2739 0.165000 4.317000 4.152000 1 2 +sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_59.b[0] +sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13 sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_72.mi[0] Hold check -2687 3 -Endpoint: u_pic_cnt/reg1_syn_385 -2689 0.067000 1 1 -Timing path: reg36_syn_108.clk->u_pic_cnt/reg1_syn_385 -reg36_syn_108.clk -u_pic_cnt/reg1_syn_385 -2691 0.067000 2.291000 2.358000 0 1 -u_pic_cnt/signal_from[5] u_pic_cnt/reg1_syn_385.mi[0] +2779 3 +Endpoint: u_mipi_eot_min/reg1_syn_266 +2781 0.067000 1 1 +Timing path: u_bus_top/reg18_syn_64.clk->u_mipi_eot_min/reg1_syn_266 +u_bus_top/reg18_syn_64.clk +u_mipi_eot_min/reg1_syn_266 +2783 0.067000 2.291000 2.358000 0 1 +u_mipi_eot_min/signal_from[0] u_mipi_eot_min/reg1_syn_266.mi[0] -Endpoint: u_mipi_eot_min/reg1_syn_289 -2727 0.067000 1 1 -Timing path: u_bus_top/reg18_syn_66.clk->u_mipi_eot_min/reg1_syn_289 -u_bus_top/reg18_syn_66.clk -u_mipi_eot_min/reg1_syn_289 -2729 0.067000 2.291000 2.358000 0 1 -u_mipi_eot_min/signal_from[0] u_mipi_eot_min/reg1_syn_289.mi[1] +Endpoint: sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20 +2819 0.075000 1 1 +Timing path: u_b_pclk/signal_to_reg[0]_reg_syn_5.clk->sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20 +u_b_pclk/signal_to_reg[0]_reg_syn_5.clk +sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20 +2821 0.075000 2.291000 2.366000 0 1 +u_b_pclk/signal_to[0] sampling_fe_b/u_sort/u0_rdsoft_n/reg0_syn_20.mi[0] -Endpoint: u_pic_cnt/reg1_syn_436 -2765 0.067000 1 1 -Timing path: reg36_syn_111.clk->u_pic_cnt/reg1_syn_436 -reg36_syn_111.clk -u_pic_cnt/reg1_syn_436 -2767 0.067000 2.291000 2.358000 0 1 -u_pic_cnt/signal_from[19] u_pic_cnt/reg1_syn_436.mi[1] +Endpoint: sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27 +2859 0.075000 1 1 +Timing path: u_b_pclk/signal_to_reg[0]_reg_syn_6.clk->sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27 +u_b_pclk/signal_to_reg[0]_reg_syn_6.clk +sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27 +2861 0.075000 2.291000 2.366000 0 1 +u_b_pclk/signal_to[0]_syn_11 sampling_fe_b/u_sort/rddpram_ctl/u0_rdsoft_n/reg0_syn_27.mi[0] Recovery check -2803 3 -Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 -2805 5.372000 2 2 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 -2807 5.372000 11.304000 5.932000 2 3 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] -U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr +2899 3 +Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 +2901 5.904000 2 2 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 +2903 5.904000 11.304000 5.400000 2 3 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] +U_rgb_to_csi_pakage/S_rst_n_dup_5 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr -Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 +Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 adj_vsynco_reg_syn_5.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 -2849 6.051000 11.304000 5.253000 1 2 -U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277 +2945 6.005000 11.304000 5.299000 1 2 +U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1277.sr -Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 -2889 5.379000 2 2 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 -2891 5.379000 11.304000 5.925000 2 3 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] -U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr +Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 +2985 5.904000 2 2 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 +2987 5.904000 11.304000 5.400000 2 3 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] +U_rgb_to_csi_pakage/S_rst_n_dup_5 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr -Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 +Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 adj_vsynco_reg_syn_5.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 -2933 6.058000 11.304000 5.246000 1 2 -U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2 +3029 6.005000 11.304000 5.299000 1 2 +U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1250_syn_2.sr -Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 -2973 5.379000 2 2 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 -2975 5.379000 11.304000 5.925000 2 3 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] -U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr +Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 +3069 5.904000 2 2 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 +3071 5.904000 11.304000 5.400000 2 3 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_36_syn_2.d[1] +U_rgb_to_csi_pakage/S_rst_n_dup_5 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.d[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr -Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 +Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 adj_vsynco_reg_syn_5.clk -U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 -3017 6.058000 11.304000 5.246000 1 2 -U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] -U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr +U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2 +3113 6.005000 11.304000 5.299000 1 2 +U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_40_syn_2.c[1] +U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1244_syn_2.sr Removal check -3057 3 -Endpoint: U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 -3059 0.697000 1 1 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 -3061 0.697000 2.327000 3.024000 1 2 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[0] -U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr +3153 3 +Endpoint: U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2 +3155 0.823000 1 1 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2 +3157 0.823000 2.311000 3.134000 1 2 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_107_syn_2.d[0] +U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_39_syn_2.sr -Endpoint: U_rgb_to_csi_pakage/reg2_syn_151_syn_2 -3101 0.727000 1 1 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg2_syn_151_syn_2 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/reg2_syn_151_syn_2 -3103 0.727000 2.327000 3.054000 1 2 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[1] -U_rgb_to_csi_pakage/S_rst_n_dup_3 U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr +Endpoint: U_rgb_to_csi_pakage/reg7_syn_139_syn_2 +3197 0.823000 1 1 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/reg7_syn_139_syn_2 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/reg7_syn_139_syn_2 +3199 0.823000 2.327000 3.150000 1 2 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_frame_end_delay_en_n_syn_135_syn_2.d[0] +U_rgb_to_csi_pakage/S_rst_n_dup_4 U_rgb_to_csi_pakage/reg7_syn_139_syn_2.sr -Endpoint: U_rgb_to_csi_pakage/reg12_syn_73_syn_2 -3143 0.767000 1 1 -Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg12_syn_73_syn_2 -U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk -U_rgb_to_csi_pakage/reg12_syn_73_syn_2 -3145 0.767000 2.327000 3.094000 1 2 -U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] -U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr +Endpoint: U_rgb_to_csi_pakage/reg7_syn_175_syn_2 +3239 0.835000 1 1 +Timing path: eot_reg_syn_5.clk->U_rgb_to_csi_pakage/reg7_syn_175_syn_2 +eot_reg_syn_5.clk +U_rgb_to_csi_pakage/reg7_syn_175_syn_2 +3241 0.835000 2.327000 3.162000 1 2 +U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_107_syn_2.d[0] +U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg7_syn_175_syn_2.sr Period check -3185 48 +3281 48 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb -3189 5.858000 1 0 +3285 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb -3190 5.858000 1 0 +3286 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb -3191 5.858000 1 0 +3287 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb -3192 5.858000 1 0 +3288 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb -3193 5.858000 1 0 +3289 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb -3194 5.858000 1 0 +3290 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb -3195 5.858000 1 0 +3291 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb -3196 5.858000 1 0 +3292 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb -3197 5.858000 1 0 +3293 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb -3198 5.858000 1 0 +3294 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb -3199 5.858000 1 0 +3295 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb -3200 5.858000 1 0 +3296 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb -3201 5.858000 1 0 +3297 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb -3202 5.858000 1 0 +3298 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb -3203 5.858000 1 0 +3299 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb -3204 5.858000 1 0 +3300 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb -3205 5.858000 1 0 +3301 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb -3206 5.858000 1 0 +3302 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb -3207 5.858000 1 0 +3303 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb -3208 5.858000 1 0 +3304 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb -3209 5.858000 1 0 +3305 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb -3210 5.858000 1 0 +3306 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb -3211 5.858000 1 0 +3307 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb -3212 5.858000 1 0 +3308 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb -3213 5.858000 1 0 +3309 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb -3214 5.858000 1 0 +3310 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb -3215 5.858000 1 0 +3311 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb -3216 5.858000 1 0 +3312 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb -3217 5.858000 1 0 +3313 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb -3218 5.858000 1 0 +3314 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb -3219 5.858000 1 0 +3315 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb -3220 5.858000 1 0 +3316 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb -3221 5.858000 1 0 +3317 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb -3222 5.858000 1 0 +3318 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb -3223 5.858000 1 0 +3319 5.858000 1 0 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb -3224 5.858000 1 0 +3320 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb -3225 5.858000 1 0 +3321 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb -3226 5.858000 1 0 +3322 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb -3227 5.858000 1 0 +3323 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb -3228 5.858000 1 0 +3324 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb -3229 5.858000 1 0 +3325 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb -3230 5.858000 1 0 +3326 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb -3231 5.858000 1 0 +3327 5.858000 1 0 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb -3232 5.858000 1 0 +3328 5.858000 1 0 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw -3233 5.958000 1 0 +3329 5.958000 1 0 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw -3234 5.958000 1 0 +3330 5.958000 1 0 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw -3235 5.958000 1 0 +3331 5.958000 1 0 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw -3236 5.958000 1 0 +3332 5.958000 1 0 clock: clk_adc -3237 46330 5330 4 +3333 44500 4390 4 Setup check -3247 3 -Endpoint: u_bus_top/reg12_syn_135 -3247 7.414000 1 1 -Timing path: reg26_syn_196.clk->u_bus_top/reg12_syn_135 -reg26_syn_196.clk -u_bus_top/reg12_syn_135 -3249 7.414000 11.187000 3.773000 0 1 -lv_cnt_a[0] u_bus_top/reg12_syn_135.mi[1] +3343 3 +Endpoint: u_bus_top/reg6_syn_120 +3343 7.440000 1 1 +Timing path: reg24_syn_78.clk->u_bus_top/reg6_syn_120 +reg24_syn_78.clk +u_bus_top/reg6_syn_120 +3345 7.440000 11.187000 3.747000 0 1 +frame_cnt[12] u_bus_top/reg6_syn_120.mi[0] -Endpoint: u_bus_top/reg6_syn_118 -3285 7.493000 1 1 -Timing path: reg24_syn_80.clk->u_bus_top/reg6_syn_118 -reg24_syn_80.clk -u_bus_top/reg6_syn_118 -3287 7.493000 11.187000 3.694000 0 1 -frame_cnt[10] u_bus_top/reg6_syn_118.mi[0] +Endpoint: u_bus_top/reg15_syn_164 +3381 7.555000 1 1 +Timing path: reg27_syn_235.clk->u_bus_top/reg15_syn_164 +reg27_syn_235.clk +u_bus_top/reg15_syn_164 +3383 7.555000 11.187000 3.632000 0 1 +lv_cnt_b[21] u_bus_top/reg15_syn_164.mi[1] -Endpoint: u_bus_top/reg0_syn_143_syn_2 -3323 7.607000 1 1 -Timing path: reg1_syn_154.clk->u_bus_top/reg0_syn_143_syn_2 -reg1_syn_154.clk -u_bus_top/reg0_syn_143_syn_2 -3325 7.607000 11.187000 3.580000 0 1 -S_hs_data_reg[11] u_bus_top/reg0_syn_143_syn_2.mi[1] +Endpoint: u_bus_top/reg0_syn_180 +3419 7.628000 1 1 +Timing path: reg1_syn_147.clk->u_bus_top/reg0_syn_180 +reg1_syn_147.clk +u_bus_top/reg0_syn_180 +3421 7.628000 11.187000 3.559000 0 1 +S_hs_data_reg[2] u_bus_top/reg0_syn_180.mi[0] Hold check -3361 3 -Endpoint: add9_syn_98 -3363 0.258000 1 1 -Timing path: reg24_syn_89.clk->add9_syn_98 -reg24_syn_89.clk -add9_syn_98 -3365 0.258000 2.191000 2.449000 0 1 -frame_cnt[2] add9_syn_98.mi[0] +3457 3 +Endpoint: add7_syn_140 +3459 0.258000 1 1 +Timing path: reg25_syn_123.clk->add7_syn_140 +reg25_syn_123.clk +add7_syn_140 +3461 0.258000 2.191000 2.449000 0 1 +lv_cnt2bus[5] add7_syn_140.mi[0] -Endpoint: u_bus_top/reg0_syn_151_syn_2 -3401 0.258000 1 1 -Timing path: reg1_syn_142.clk->u_bus_top/reg0_syn_151_syn_2 -reg1_syn_142.clk -u_bus_top/reg0_syn_151_syn_2 -3403 0.258000 2.191000 2.449000 0 1 -S_hs_data_reg[14] u_bus_top/reg0_syn_151_syn_2.mi[0] +Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80 +3497 0.258000 1 1 +Timing path: reg1_syn_162.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80 +reg1_syn_162.clk +sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80 +3499 0.258000 2.191000 2.449000 0 1 +S_hs_data_reg[13] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/add0_syn_80.mi[0] -Endpoint: exdev_ctl_b/reg2_syn_213 -3439 0.260000 1 1 -Timing path: exdev_ctl_b/reg1_syn_176.clk->exdev_ctl_b/reg2_syn_213 -exdev_ctl_b/reg1_syn_176.clk -exdev_ctl_b/reg2_syn_213 -3441 0.260000 2.107000 2.367000 0 1 -exdev_ctl_b/adc_cfg_dat_d1[27] exdev_ctl_b/reg2_syn_213.mi[0] +Endpoint: u_bus_top/reg9_syn_152 +3535 0.258000 1 1 +Timing path: reg25_syn_126.clk->u_bus_top/reg9_syn_152 +reg25_syn_126.clk +u_bus_top/reg9_syn_152 +3537 0.258000 2.191000 2.449000 0 1 +lv_cnt2bus[10] u_bus_top/reg9_syn_152.mi[1] Recovery check -3475 3 -Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_5 -3477 163.478000 1 1 -Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_5 -clkubus_rstn_reg_syn_8.clk -scan_start_diff/a_ex_frame_en_reg_syn_5 -3479 163.478000 168.576000 5.098000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_en_reg_syn_5.sr - - +3573 3 Endpoint: scan_start_diff/a_ex_frame_reg_syn_5 -3515 163.665000 1 1 +3575 162.162000 1 1 Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5 clkubus_rstn_reg_syn_8.clk scan_start_diff/a_ex_frame_reg_syn_5 -3517 163.665000 168.576000 4.911000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_reg_syn_5.sr +3577 162.162000 168.504000 6.342000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] +BUSY_MIPI_sync_d0_i_syn_3 scan_start_diff/a_ex_frame_reg_syn_5.sr -Endpoint: scan_start_diff/enable_from_arm_rog_reg_syn_5 -3553 163.676000 1 1 -Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/enable_from_arm_rog_reg_syn_5 +Endpoint: scan_start_diff/reg1_syn_21 +3613 162.190000 1 1 +Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_21 clkubus_rstn_reg_syn_8.clk -scan_start_diff/enable_from_arm_rog_reg_syn_5 -3555 163.676000 168.576000 4.900000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/enable_from_arm_rog_reg_syn_5.sr +scan_start_diff/reg1_syn_21 +3615 162.190000 168.504000 6.314000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] +BUSY_MIPI_sync_d0_i_syn_3 scan_start_diff/reg1_syn_21.sr + + +Endpoint: scan_start_diff/reg1_syn_18 +3651 162.190000 1 1 +Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg1_syn_18 +clkubus_rstn_reg_syn_8.clk +scan_start_diff/reg1_syn_18 +3653 162.190000 168.504000 6.314000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] +BUSY_MIPI_sync_d0_i_syn_3 scan_start_diff/reg1_syn_18.sr Removal check -3591 3 -Endpoint: scan_start_diff/reg2_syn_20 -3593 1.366000 1 1 -Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_20 +3689 3 +Endpoint: scan_start_diff/reg2_syn_21 +3691 2.267000 1 1 +Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_21 clkubus_rstn_reg_syn_8.clk -scan_start_diff/reg2_syn_20 -3595 1.366000 2.236000 3.602000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_20.sr +scan_start_diff/reg2_syn_21 +3693 2.267000 2.299000 4.566000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] +BUSY_MIPI_sync_d0_i_syn_3 scan_start_diff/reg2_syn_21.sr -Endpoint: scan_start_diff/a_frame_pad_rog_reg_syn_5 -3631 1.410000 1 1 -Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_frame_pad_rog_reg_syn_5 +Endpoint: scan_start_diff/enable_from_arm_rog_reg_syn_4 +3729 2.267000 1 1 +Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/enable_from_arm_rog_reg_syn_4 clkubus_rstn_reg_syn_8.clk -scan_start_diff/a_frame_pad_rog_reg_syn_5 -3633 1.410000 2.236000 3.646000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_frame_pad_rog_reg_syn_5.sr +scan_start_diff/enable_from_arm_rog_reg_syn_4 +3731 2.267000 2.299000 4.566000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_bus_top/u_local_bus_slve_cis/reg57_syn_44.d[0] +BUSY_MIPI_sync_d0_i_syn_3 scan_start_diff/enable_from_arm_rog_reg_syn_4.sr -Endpoint: scan_start_diff/reg2_syn_22 -3669 1.433000 1 1 -Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_22 +Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_4 +3767 2.284000 1 1 +Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_4 clkubus_rstn_reg_syn_8.clk -scan_start_diff/reg2_syn_22 -3671 1.433000 2.236000 3.669000 1 2 -u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] -BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_22.sr +scan_start_diff/a_ex_frame_en_reg_syn_4 +3769 2.284000 2.299000 4.583000 1 2 +u_softrst_fan_ctrl/signal_from[0] u_pixel_cdc/u_clka_cis_total_num/reg1_syn_400.d[0] +BUSY_MIPI_sync_d0_i_syn_8 scan_start_diff/a_ex_frame_en_reg_syn_4.sr clock: S_clk_x2 -3707 152 86 2 +3805 152 86 2 Setup check -3717 3 -Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3717 2.419000 2 2 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3719 2.419000 6.679000 4.260000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3755 2.942000 6.679000 3.737000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] +3815 3 +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9 +3815 2.603000 1 1 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9 +3817 2.603000 6.859000 4.256000 1 2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_dup_1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.d[0] +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_n1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_9.mi[0] -Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 -3791 2.457000 2 2 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 -3793 2.457000 6.679000 4.222000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 +3853 2.632000 2 2 +Timing path: add8_syn_104.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 +add8_syn_104.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 +3855 2.632000 6.679000 4.047000 1 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.b[0] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 -3829 3.101000 6.679000 3.578000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2 +3891 2.998000 6.679000 3.681000 1 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.c[0] -Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3865 2.507000 2 2 -Timing path: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3867 2.507000 6.679000 4.172000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 -3903 2.831000 6.679000 3.848000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13 +3927 2.903000 1 1 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13 +3929 2.903000 6.923000 4.020000 1 2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_dup_1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_11.d[0] +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_n1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_odd_even_reg_syn_13.mi[0] Hold check -3939 3 -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 -3941 0.167000 1 1 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 -3943 0.167000 2.291000 2.458000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0] +3965 3 +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 +3967 0.158000 1 1 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_13_syn_2_dup_1.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_13_syn_2_dup_1.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 +3969 0.158000 2.291000 2.449000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_dup_42 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] -Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 -3979 0.190000 1 1 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk -sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 -3981 0.190000 2.291000 2.481000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0] +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 +4005 0.212000 1 1 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_17.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_17.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 +4007 0.212000 2.238000 2.450000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_dup_41 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.sr -Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 -4017 0.341000 2 2 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 -4019 0.341000 2.291000 2.632000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 -4055 0.490000 2.291000 2.781000 1 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1] +Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 +4043 0.264000 1 1 +Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_18.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 +sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[97]_syn_18.clk +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5 +4045 0.264000 2.291000 2.555000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.mi[0] clock: S_clk_x4 -4091 32 8 2 +4081 32 8 2 Setup check -4101 3 +4091 3 Endpoint: O_data_hs_p[1]_syn_2 -4101 0.879000 4 3 +4091 0.915000 4 3 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk O_data_hs_p[1]_syn_2 -4103 0.879000 4.110000 3.231000 0 1 +4093 0.915000 4.110000 3.195000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk -O_data_hs_p[1]_syn_2 -4137 0.879000 4.110000 3.231000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1] - Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk O_data_hs_p[1]_syn_2 -4171 0.923000 4.110000 3.187000 0 1 +4127 0.915000 4.110000 3.195000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1] + +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk +O_data_hs_p[1]_syn_2 +4161 1.078000 4.110000 3.032000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2] +Endpoint: O_data_hs_p[3]_syn_2 +4195 0.928000 4 3 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk +O_data_hs_p[3]_syn_2 +4197 0.928000 4.110000 3.182000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2] + +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk +O_data_hs_p[3]_syn_2 +4231 1.035000 4.110000 3.075000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1] + +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +O_data_hs_p[3]_syn_2 +4265 1.078000 4.110000 3.032000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3] + + +Endpoint: O_data_hs_p[0]_syn_2 +4299 1.028000 4 3 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk +O_data_hs_p[0]_syn_2 +4301 1.028000 4.110000 3.082000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2] + +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk +O_data_hs_p[0]_syn_2 +4335 1.075000 4.110000 3.035000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1] + +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +O_data_hs_p[0]_syn_2 +4369 1.078000 4.110000 3.032000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3] + + + +Hold check +4403 3 Endpoint: O_data_hs_p[2]_syn_2 -4205 0.923000 4 3 +4405 0.401000 4 3 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk O_data_hs_p[2]_syn_2 -4207 0.923000 4.110000 3.187000 0 1 +4407 0.401000 1.962000 2.363000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[2]_syn_2.do[3] Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk O_data_hs_p[2]_syn_2 -4241 0.925000 4.110000 3.185000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk -O_data_hs_p[2]_syn_2 -4275 1.224000 4.110000 2.886000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2] - - -Endpoint: O_data_hs_p[3]_syn_2 -4309 0.928000 4 3 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk -O_data_hs_p[3]_syn_2 -4311 0.928000 4.110000 3.182000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk -O_data_hs_p[3]_syn_2 -4345 0.929000 4.110000 3.181000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk -O_data_hs_p[3]_syn_2 -4379 1.075000 4.110000 3.035000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1] - - - -Hold check -4413 3 -Endpoint: O_data_hs_p[2]_syn_2 -4415 0.401000 4 3 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk -O_data_hs_p[2]_syn_2 -4417 0.401000 1.962000 2.363000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2] - -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk->O_data_hs_p[2]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk -O_data_hs_p[2]_syn_2 -4451 0.401000 1.962000 2.363000 0 1 +4441 0.401000 1.962000 2.363000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[2]_syn_2.do[0] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk O_data_hs_p[2]_syn_2 -4485 0.623000 1.962000 2.585000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1] +4475 0.517000 1.962000 2.479000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2] -Endpoint: O_data_hs_p[3]_syn_2 -4519 0.498000 4 3 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk -O_data_hs_p[3]_syn_2 -4521 0.498000 1.962000 2.460000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[3]_syn_2.do[0] +Endpoint: O_data_hs_p[0]_syn_2 +4509 0.498000 4 3 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +O_data_hs_p[0]_syn_2 +4511 0.498000 1.962000 2.460000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk -O_data_hs_p[3]_syn_2 -4555 0.508000 1.962000 2.470000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1] +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +O_data_hs_p[0]_syn_2 +4545 0.507000 1.962000 2.469000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk -O_data_hs_p[3]_syn_2 -4589 0.614000 1.962000 2.576000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3] +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk +O_data_hs_p[0]_syn_2 +4579 0.508000 1.962000 2.470000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1] Endpoint: O_data_hs_p[1]_syn_2 -4623 0.507000 4 3 -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk->O_data_hs_p[1]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk +4613 0.498000 4 3 +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk O_data_hs_p[1]_syn_2 -4625 0.507000 1.962000 2.469000 0 1 +4615 0.498000 1.962000 2.460000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0] -Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk +Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[1]_syn_2 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk O_data_hs_p[1]_syn_2 -4659 0.624000 1.962000 2.586000 0 1 +4649 0.507000 1.962000 2.469000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2] Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk O_data_hs_p[1]_syn_2 -4693 0.653000 1.962000 2.615000 0 1 +4683 0.629000 1.962000 2.591000 0 1 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3] clock: S_clk_x4_90d -4727 4 2 2 +4717 4 2 2 Setup check -4737 1 +4727 1 Endpoint: O_clk_hs_p_syn_2 -4737 -0.811000 2 2 +4727 -0.512000 2 2 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk O_clk_hs_p_syn_2 -4739 -0.811000 2.374000 3.185000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2] +4729 -0.512000 2.374000 2.886000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0] Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk O_clk_hs_p_syn_2 -4773 -0.708000 2.374000 3.082000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0] +4763 -0.508000 2.374000 2.882000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2] Hold check -4807 1 +4797 1 Endpoint: O_clk_hs_p_syn_2 -4809 2.282000 2 2 +4799 2.128000 2 2 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk O_clk_hs_p_syn_2 -4811 2.282000 0.226000 2.508000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0] +4801 2.128000 0.226000 2.354000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2] Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk O_clk_hs_p_syn_2 -4845 2.359000 0.226000 2.585000 0 1 -u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2] +4835 2.137000 0.226000 2.363000 0 1 +u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0] @@ -1302,15 +1302,15 @@ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_cl Timing group statistics: Clock constraints: Clock Name Min Period Max Freq Skew Fanout TNS - S_clk (108.0MHz) 9.231ns 108.331MHz 0.326ns 1825 0.000ns - a_pclk (48.0MHz) 12.828ns 77.954MHz 0.326ns 1432 0.000ns - b_pclk (48.0MHz) 10.513ns 95.120MHz 0.326ns 1342 0.000ns - clk_adc (6.0MHz) 159.250ns 6.279MHz 0.326ns 1235 0.000ns - a_sclk (168.0MHz) 1.906ns 524.659MHz 0.254ns 71 0.000ns - b_sclk (168.0MHz) 2.080ns 480.769MHz 0.326ns 70 0.000ns - S_clk_x2 (216.0MHz) 2.210ns 452.489MHz 0.480ns 22 0.000ns - S_clk_x4 (432.0MHz) 1.435ns 696.864MHz 0.018ns 4 0.000ns - S_clk_x4_90d (432.0MHz) 3.125ns 320.000MHz 0.000ns 1 -0.811ns + S_clk (108.0MHz) 9.216ns 108.507MHz 0.326ns 1798 0.000ns + a_pclk (48.0MHz) 12.866ns 77.724MHz 0.326ns 1415 0.000ns + b_pclk (48.0MHz) 9.922ns 100.786MHz 0.326ns 1345 0.000ns + clk_adc (6.0MHz) 159.224ns 6.280MHz 0.326ns 989 0.000ns + b_sclk (168.0MHz) 2.151ns 464.900MHz 0.326ns 72 0.000ns + a_sclk (168.0MHz) 1.860ns 537.634MHz 0.326ns 70 0.000ns + S_clk_x2 (216.0MHz) 2.026ns 493.583MHz 0.480ns 22 0.000ns + S_clk_x4 (432.0MHz) 1.399ns 714.796MHz 0.018ns 4 0.000ns + S_clk_x4_90d (432.0MHz) 2.826ns 353.857MHz 0.000ns 1 -0.512ns Minimum input arrival time before clock: no constraint path Maximum output required time after clock: no constraint path Maximum combinational path delay: no constraint path @@ -1323,34 +1323,12 @@ Warning: No clock constraint on 3 clock net(s): Check Type: MAX ---------------------------------------------------------------------------------------------------- Path Num Constraint - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ] - 0 set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[3]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d} ] - 0 set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[1]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2} ] - 1 set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 1 set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ] 2 set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ] Check Type: MIN ---------------------------------------------------------------------------------------------------- Path Num Constraint - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ] - 22 set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ] - 16 set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ] - 1 set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] - 0 set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 1 set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ] 2 set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ] diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db index c9cfcd8..2700de5 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db index 5b3cdd8..a4b0ac6 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db differ diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log index bdcf7f6..0a1773c 100644 --- a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log +++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log @@ -4,7 +4,7 @@ Executable = D:/Anlogic/TD5.6.2/bin/td.exe Built at = 20:34:38 Mar 21 2023 Run by = holdtecs - Run Date = Tue Mar 12 14:52:10 2024 + Run Date = Tue Mar 12 16:40:01 2024 Run on = DESKTOP-5MQL5VE ============================================================ @@ -97,19 +97,19 @@ HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in . HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) -HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) -HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) -HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) -HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) -HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) -HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) -HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) -HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) -HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) -HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) -HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) -HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) -HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v @@ -203,9 +203,9 @@ RUN-1001 : Import timing constraints RUN-1001 : Import IO constraints RUN-1001 : Import Inst constraints RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 -RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.470817s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (99.9%) +RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.195129s wall, 2.125000s user + 0.078125s system = 2.203125s CPU (100.4%) -RUN-1004 : used memory is 354 MB, reserved memory is 324 MB, peak memory is 358 MB +RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 350 MB RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" RUN-1002 : start command "get_ports clock_source" RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " @@ -243,42 +243,6 @@ RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_c RUN-1002 : start command "get_ports clock_source" RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" -RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" -RUN-1002 : start command "set_false_path -setup -from -to " -RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" -RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" -RUN-1002 : start command "set_false_path -setup -from -to " -RUN-1002 : start command "get_regs BUSY_MIPI" -RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_regs clkubus_rstn" -RUN-1002 : start command "get_nets a_pclk_rstn" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_regs clkubus_rstn" -RUN-1002 : start command "get_nets b_pclk_rstn" -RUN-1002 : start command "set_false_path -from -to " RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" RUN-1002 : start command "set_false_path -from -to " @@ -329,7 +293,7 @@ SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be m SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27] SYN-5055 Similar messages will be suppressed. RUN-1002 : start command "phys_opt -simplify_lut" -SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins). +SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins). SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins). SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins). SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst. @@ -367,15 +331,15 @@ SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins. SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins. PHY-1001 : Populate physical database on model huagao_mipi_top. -RUN-1001 : There are total 18313 instances -RUN-0007 : 7475 luts, 9615 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps -RUN-1001 : There are total 20891 nets +RUN-1001 : There are total 17682 instances +RUN-0007 : 7357 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 20260 nets RUN-6004 WARNING: There are 20 nets with only 1 pin. -RUN-1001 : 13879 nets have 2 pins -RUN-1001 : 5557 nets have [3 - 5] pins -RUN-1001 : 1043 nets have [6 - 10] pins +RUN-1001 : 13191 nets have 2 pins +RUN-1001 : 5790 nets have [3 - 5] pins +RUN-1001 : 865 nets have [6 - 10] pins RUN-1001 : 158 nets have [11 - 20] pins -RUN-1001 : 180 nets have [21 - 99] pins +RUN-1001 : 182 nets have [21 - 99] pins RUN-1001 : 54 nets have 100+ pins PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint. RUN-1001 : Report Control nets information: @@ -384,7 +348,7 @@ RUN-1001 : ---------------------------------- RUN-1001 : CE | SSR | ASR | DFF Count RUN-1001 : ---------------------------------- RUN-1001 : No | No | No | 793 -RUN-1001 : No | No | Yes | 2540 +RUN-1001 : No | No | Yes | 2027 RUN-1001 : No | Yes | No | 3473 RUN-1001 : Yes | No | No | 64 RUN-1001 : Yes | No | Yes | 72 @@ -398,1211 +362,1057 @@ RUN-0007 : 12 | 76 | 57 RUN-0007 : --------------------------- RUN-0007 : Control Set = 142 PHY-3001 : Initial placement ... -PHY-3001 : design contains 18311 instances, 7475 luts, 9615 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 6469 pins -PHY-0007 : Cell area utilization is 49% +PHY-3001 : design contains 17680 instances, 7357 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins +PHY-0007 : Cell area utilization is 48% PHY-3001 : Start timing update ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.206386s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.7%) +RUN-1003 : finish command "start_timer -report" in 1.169949s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (100.2%) -RUN-1004 : used memory is 552 MB, reserved memory is 529 MB, peak memory is 552 MB +RUN-1004 : used memory is 538 MB, reserved memory is 514 MB, peak memory is 538 MB TMR-2503 : Start to update net delay, extr mode = 2. -TMR-2504 : Update delay of 20713 nets completely. +TMR-2504 : Update delay of 20082 nets completely. TMR-2502 : Annotate delay completely, extr mode = 2. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 2.026228s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (100.2%) +PHY-3001 : End timing update; 1.973139s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (100.6%) -PHY-3001 : Found 1222 cells with 2 region constraints. +PHY-3001 : Found 1234 cells with 2 region constraints. PHY-3001 : Global placement ... -PHY-3001 : Initial: Len = 4.00806e+06 +PHY-3001 : Initial: Len = 4.1219e+06 PHY-3001 : Clustering ... -PHY-3001 : Level 0 #clusters 18311. -PHY-3001 : Level 1 #clusters 2004. -PHY-3001 : End clustering; 0.130135s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (144.1%) +PHY-3001 : Level 0 #clusters 17680. +PHY-3001 : Level 1 #clusters 1973. +PHY-3001 : End clustering; 0.128462s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.3%) PHY-3001 : Run with size of 4 -PHY-3001 : Cell area utilization is 49% +PHY-3001 : Cell area utilization is 48% PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 -PHY-3002 : Step(1): len = 1.25808e+06, overlap = 537.594 -PHY-3002 : Step(2): len = 1.17948e+06, overlap = 555.469 -PHY-3002 : Step(3): len = 805880, overlap = 617.25 -PHY-3002 : Step(4): len = 747389, overlap = 670.188 -PHY-3002 : Step(5): len = 580252, overlap = 828.438 -PHY-3002 : Step(6): len = 506405, overlap = 888.562 -PHY-3002 : Step(7): len = 438740, overlap = 953.062 -PHY-3002 : Step(8): len = 405793, overlap = 990.031 -PHY-3002 : Step(9): len = 368140, overlap = 999.406 -PHY-3002 : Step(10): len = 335219, overlap = 1063.25 -PHY-3002 : Step(11): len = 304746, overlap = 1095.97 -PHY-3002 : Step(12): len = 274497, overlap = 1117.5 -PHY-3002 : Step(13): len = 258167, overlap = 1150.56 -PHY-3002 : Step(14): len = 234928, overlap = 1220.59 -PHY-3002 : Step(15): len = 218432, overlap = 1280.91 -PHY-3002 : Step(16): len = 199574, overlap = 1330.09 -PHY-3002 : Step(17): len = 179244, overlap = 1360.41 -PHY-3002 : Step(18): len = 168619, overlap = 1364.97 -PHY-3002 : Step(19): len = 153530, overlap = 1394.62 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37726e-06 -PHY-3002 : Step(20): len = 156286, overlap = 1372.84 -PHY-3002 : Step(21): len = 190148, overlap = 1281.91 -PHY-3002 : Step(22): len = 194863, overlap = 1229.56 -PHY-3002 : Step(23): len = 199569, overlap = 1171.84 -PHY-3002 : Step(24): len = 197760, overlap = 1203.22 -PHY-3002 : Step(25): len = 197337, overlap = 1227.56 -PHY-3002 : Step(26): len = 194838, overlap = 1227.19 -PHY-3002 : Step(27): len = 192802, overlap = 1221.19 -PHY-3002 : Step(28): len = 190823, overlap = 1218.09 -PHY-3002 : Step(29): len = 189585, overlap = 1208.81 -PHY-3002 : Step(30): len = 187401, overlap = 1200.69 -PHY-3002 : Step(31): len = 186285, overlap = 1197.38 -PHY-3002 : Step(32): len = 186493, overlap = 1166.91 -PHY-3002 : Step(33): len = 185759, overlap = 1155.12 -PHY-3002 : Step(34): len = 185102, overlap = 1127.38 -PHY-3002 : Step(35): len = 183975, overlap = 1115.5 -PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.75453e-06 -PHY-3002 : Step(36): len = 187471, overlap = 1107.03 -PHY-3002 : Step(37): len = 198764, overlap = 1090.66 -PHY-3002 : Step(38): len = 202928, overlap = 1067.75 -PHY-3002 : Step(39): len = 207381, overlap = 1034.38 -PHY-3002 : Step(40): len = 210559, overlap = 1015.44 -PHY-3002 : Step(41): len = 213446, overlap = 990 -PHY-3002 : Step(42): len = 212214, overlap = 968.312 -PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.50906e-06 -PHY-3002 : Step(43): len = 221098, overlap = 913.219 -PHY-3002 : Step(44): len = 242358, overlap = 819.594 -PHY-3002 : Step(45): len = 255165, overlap = 778.438 -PHY-3002 : Step(46): len = 267478, overlap = 731 -PHY-3002 : Step(47): len = 271662, overlap = 720.438 -PHY-3002 : Step(48): len = 271709, overlap = 706.906 -PHY-3002 : Step(49): len = 270113, overlap = 680 -PHY-3002 : Step(50): len = 269630, overlap = 679.875 -PHY-3002 : Step(51): len = 267425, overlap = 688.156 -PHY-3002 : Step(52): len = 265303, overlap = 695.812 -PHY-3002 : Step(53): len = 262713, overlap = 706.719 -PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.10181e-05 -PHY-3002 : Step(54): len = 281886, overlap = 673.031 -PHY-3002 : Step(55): len = 297627, overlap = 598.438 -PHY-3002 : Step(56): len = 304406, overlap = 543.031 -PHY-3002 : Step(57): len = 308710, overlap = 545.219 -PHY-3002 : Step(58): len = 307694, overlap = 551.438 -PHY-3002 : Step(59): len = 307802, overlap = 554.938 -PHY-3002 : Step(60): len = 304819, overlap = 550.656 -PHY-3002 : Step(61): len = 305086, overlap = 548.125 -PHY-3002 : Step(62): len = 303942, overlap = 549.188 -PHY-3002 : Step(63): len = 304623, overlap = 548.75 -PHY-3002 : Step(64): len = 301771, overlap = 538.562 -PHY-3002 : Step(65): len = 301740, overlap = 527.969 -PHY-3002 : Step(66): len = 301591, overlap = 528.219 -PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.20362e-05 -PHY-3002 : Step(67): len = 316913, overlap = 533.75 -PHY-3002 : Step(68): len = 328114, overlap = 511.719 -PHY-3002 : Step(69): len = 332758, overlap = 471.406 -PHY-3002 : Step(70): len = 335310, overlap = 472.625 -PHY-3002 : Step(71): len = 334783, overlap = 483.938 -PHY-3002 : Step(72): len = 337780, overlap = 470.219 -PHY-3002 : Step(73): len = 338712, overlap = 458.938 -PHY-3002 : Step(74): len = 340455, overlap = 459.062 -PHY-3002 : Step(75): len = 339404, overlap = 467.625 -PHY-3002 : Step(76): len = 340251, overlap = 463.375 -PHY-3002 : Step(77): len = 339541, overlap = 456.281 -PHY-3002 : Step(78): len = 340666, overlap = 462.219 -PHY-3002 : Step(79): len = 339598, overlap = 465.75 -PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.40725e-05 -PHY-3002 : Step(80): len = 358475, overlap = 417.094 -PHY-3002 : Step(81): len = 371673, overlap = 392.438 -PHY-3002 : Step(82): len = 371429, overlap = 384 -PHY-3002 : Step(83): len = 373076, overlap = 377.188 -PHY-3002 : Step(84): len = 375376, overlap = 382.594 -PHY-3002 : Step(85): len = 379126, overlap = 374.875 -PHY-3002 : Step(86): len = 376946, overlap = 358.219 -PHY-3002 : Step(87): len = 380036, overlap = 349.438 -PHY-3002 : Step(88): len = 381497, overlap = 324.781 -PHY-3002 : Step(89): len = 383751, overlap = 328.844 -PHY-3002 : Step(90): len = 378101, overlap = 320.062 -PHY-3002 : Step(91): len = 377588, overlap = 307.562 -PHY-3002 : Step(92): len = 380210, overlap = 315.656 -PHY-3002 : Step(93): len = 382216, overlap = 309.469 -PHY-3002 : Step(94): len = 377413, overlap = 316.156 -PHY-3002 : Step(95): len = 376819, overlap = 314.219 -PHY-3002 : Step(96): len = 378971, overlap = 320.594 -PHY-3002 : Step(97): len = 381832, overlap = 309.156 -PHY-3002 : Step(98): len = 378679, overlap = 322.562 -PHY-3002 : Step(99): len = 378909, overlap = 328.312 -PHY-3002 : Step(100): len = 381466, overlap = 320.75 -PHY-3002 : Step(101): len = 383108, overlap = 322.375 -PHY-3002 : Step(102): len = 379254, overlap = 323.375 -PHY-3002 : Step(103): len = 378855, overlap = 336.344 -PHY-3002 : Step(104): len = 382473, overlap = 334.438 -PHY-3002 : Step(105): len = 385118, overlap = 324.469 -PHY-3002 : Step(106): len = 379894, overlap = 330 -PHY-3002 : Step(107): len = 379380, overlap = 334 -PHY-3002 : Step(108): len = 381186, overlap = 337.844 -PHY-3002 : Step(109): len = 383820, overlap = 343.094 -PHY-3002 : Step(110): len = 380397, overlap = 343.188 -PHY-3002 : Step(111): len = 380110, overlap = 335.906 -PHY-3002 : Step(112): len = 381876, overlap = 333.656 -PHY-3002 : Step(113): len = 382988, overlap = 331.688 -PHY-3002 : Step(114): len = 379633, overlap = 340.5 -PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.69695e-05 -PHY-3002 : Step(115): len = 396380, overlap = 324.281 -PHY-3002 : Step(116): len = 404504, overlap = 316.625 -PHY-3002 : Step(117): len = 402189, overlap = 319.906 -PHY-3002 : Step(118): len = 402844, overlap = 307.562 -PHY-3002 : Step(119): len = 407559, overlap = 300.656 -PHY-3002 : Step(120): len = 410960, overlap = 293.938 -PHY-3002 : Step(121): len = 409023, overlap = 313.469 -PHY-3002 : Step(122): len = 410609, overlap = 307.719 -PHY-3002 : Step(123): len = 413005, overlap = 302.188 -PHY-3002 : Step(124): len = 415370, overlap = 304.281 -PHY-3002 : Step(125): len = 411929, overlap = 304.812 -PHY-3002 : Step(126): len = 411455, overlap = 301.156 -PHY-3002 : Step(127): len = 413253, overlap = 297.406 -PHY-3002 : Step(128): len = 415569, overlap = 296.688 -PHY-3002 : Step(129): len = 413280, overlap = 298.125 -PHY-3002 : Step(130): len = 414014, overlap = 299.562 -PHY-3002 : Step(131): len = 415804, overlap = 291.688 -PHY-3002 : Step(132): len = 416706, overlap = 287.562 -PHY-3002 : Step(133): len = 414488, overlap = 293.062 -PHY-3002 : Step(134): len = 414222, overlap = 296.188 -PHY-3002 : Step(135): len = 416186, overlap = 297.844 -PHY-3002 : Step(136): len = 418247, overlap = 297.594 -PHY-3002 : Step(137): len = 415157, overlap = 307.406 -PHY-3002 : Step(138): len = 414792, overlap = 302.969 -PHY-3002 : Step(139): len = 416141, overlap = 297.094 -PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000173939 -PHY-3002 : Step(140): len = 429093, overlap = 281.469 -PHY-3002 : Step(141): len = 436379, overlap = 267.344 -PHY-3002 : Step(142): len = 436546, overlap = 270.844 -PHY-3002 : Step(143): len = 437380, overlap = 260 -PHY-3002 : Step(144): len = 439507, overlap = 261.031 -PHY-3002 : Step(145): len = 442472, overlap = 260.094 -PHY-3002 : Step(146): len = 443304, overlap = 254.219 -PHY-3002 : Step(147): len = 444774, overlap = 251.031 -PHY-3002 : Step(148): len = 447138, overlap = 255.531 -PHY-3002 : Step(149): len = 448747, overlap = 255.688 -PHY-3002 : Step(150): len = 447451, overlap = 243.031 -PHY-3002 : Step(151): len = 447432, overlap = 241.656 -PHY-3002 : Step(152): len = 447994, overlap = 237.375 -PHY-3002 : Step(153): len = 448451, overlap = 237.281 -PHY-3002 : Step(154): len = 446798, overlap = 237.188 -PHY-3002 : Step(155): len = 446275, overlap = 236.5 -PHY-3002 : Step(156): len = 447543, overlap = 230.219 -PHY-3002 : Step(157): len = 449128, overlap = 220.375 -PHY-3002 : Step(158): len = 447139, overlap = 219.219 -PHY-3002 : Step(159): len = 446549, overlap = 211.5 -PHY-3002 : Step(160): len = 447169, overlap = 214.344 -PHY-3002 : Step(161): len = 447800, overlap = 215.125 -PHY-3002 : Step(162): len = 446898, overlap = 207.406 -PHY-3002 : Step(163): len = 446875, overlap = 201.406 -PHY-3002 : Step(164): len = 447304, overlap = 210.5 -PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000347504 -PHY-3002 : Step(165): len = 457687, overlap = 210.438 -PHY-3002 : Step(166): len = 465640, overlap = 207.938 -PHY-3002 : Step(167): len = 466285, overlap = 204.312 -PHY-3002 : Step(168): len = 467249, overlap = 195.25 -PHY-3002 : Step(169): len = 469554, overlap = 192.719 -PHY-3002 : Step(170): len = 471718, overlap = 200 -PHY-3002 : Step(171): len = 471191, overlap = 203.031 -PHY-3002 : Step(172): len = 471762, overlap = 203.625 -PHY-3002 : Step(173): len = 474201, overlap = 204.312 -PHY-3002 : Step(174): len = 475784, overlap = 201.562 -PHY-3002 : Step(175): len = 474873, overlap = 204.906 -PHY-3002 : Step(176): len = 474276, overlap = 202.906 -PHY-3002 : Step(177): len = 475208, overlap = 198.844 -PHY-3002 : Step(178): len = 478795, overlap = 189.438 -PHY-3002 : Step(179): len = 478779, overlap = 190.219 -PHY-3002 : Step(180): len = 479429, overlap = 196.031 -PHY-3002 : Step(181): len = 480439, overlap = 190.375 -PHY-3002 : Step(182): len = 481046, overlap = 190.844 -PHY-3002 : Step(183): len = 480074, overlap = 193.062 -PHY-3002 : Step(184): len = 479914, overlap = 196.062 -PHY-3002 : Step(185): len = 480011, overlap = 187.688 -PHY-3002 : Step(186): len = 480060, overlap = 186.594 -PHY-3002 : Step(187): len = 479977, overlap = 191.312 -PHY-3002 : Step(188): len = 480291, overlap = 189.219 -PHY-3002 : Step(189): len = 480033, overlap = 187.594 -PHY-3002 : Step(190): len = 480026, overlap = 184.906 -PHY-3002 : Step(191): len = 480182, overlap = 185.344 -PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000629862 -PHY-3002 : Step(192): len = 484636, overlap = 185 -PHY-3002 : Step(193): len = 491568, overlap = 188.906 -PHY-3002 : Step(194): len = 492459, overlap = 174.625 -PHY-3002 : Step(195): len = 493328, overlap = 178.156 -PHY-3002 : Step(196): len = 494684, overlap = 175.781 -PHY-3002 : Step(197): len = 495973, overlap = 182.688 -PHY-3002 : Step(198): len = 496068, overlap = 180.688 -PHY-3002 : Step(199): len = 496492, overlap = 179.375 -PHY-3002 : Step(200): len = 497525, overlap = 179.062 -PHY-3002 : Step(201): len = 497860, overlap = 178.938 -PHY-3002 : Step(202): len = 497995, overlap = 176.688 -PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106194 -PHY-3002 : Step(203): len = 501189, overlap = 172.438 -PHY-3002 : Step(204): len = 505162, overlap = 170.562 -PHY-3002 : Step(205): len = 505875, overlap = 159.469 -PHY-3002 : Step(206): len = 506812, overlap = 163.594 -PHY-3002 : Step(207): len = 509113, overlap = 160.812 -PHY-3002 : Step(208): len = 511531, overlap = 160.969 -PHY-3002 : Step(209): len = 512285, overlap = 163.625 -PHY-3002 : Step(210): len = 512751, overlap = 164.281 -PHY-3002 : Step(211): len = 513549, overlap = 160.531 -PHY-3002 : Step(212): len = 514423, overlap = 165.031 -PHY-3002 : Step(213): len = 514641, overlap = 168.281 -PHY-3002 : Step(214): len = 515054, overlap = 166.562 -PHY-3002 : Step(215): len = 515798, overlap = 163.719 -PHY-3002 : Step(216): len = 516032, overlap = 161.594 -PHY-3002 : Step(217): len = 516078, overlap = 162.438 -PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017657 -PHY-3002 : Step(218): len = 519424, overlap = 162.188 -PHY-3002 : Step(219): len = 528170, overlap = 161.281 -PHY-3002 : Step(220): len = 528993, overlap = 160.875 -PHY-3002 : Step(221): len = 529757, overlap = 166 -PHY-3002 : Step(222): len = 531547, overlap = 169.75 -PHY-3002 : Step(223): len = 532471, overlap = 171.062 -PHY-3002 : Step(224): len = 532202, overlap = 169.25 -PHY-3002 : Step(225): len = 532186, overlap = 160.906 -PHY-3002 : Step(226): len = 533182, overlap = 164.469 -PHY-3002 : Step(227): len = 534273, overlap = 161.219 -PHY-3002 : Step(228): len = 534293, overlap = 156.25 -PHY-3002 : Step(229): len = 534480, overlap = 155.875 -PHY-3002 : Step(230): len = 535266, overlap = 157.812 -PHY-3002 : Step(231): len = 535593, overlap = 158.156 -PHY-3002 : Step(232): len = 535598, overlap = 156.781 -PHY-3002 : Step(233): len = 535732, overlap = 156.344 -PHY-3002 : Step(234): len = 536545, overlap = 158.906 -PHY-3002 : Step(235): len = 537668, overlap = 158.875 -PHY-3002 : Step(236): len = 537696, overlap = 160.156 -PHY-3002 : Step(237): len = 537796, overlap = 157.844 -PHY-3002 : Step(238): len = 538367, overlap = 157.031 +PHY-3002 : Step(1): len = 1.28458e+06, overlap = 454.594 +PHY-3002 : Step(2): len = 1.19286e+06, overlap = 517.438 +PHY-3002 : Step(3): len = 834854, overlap = 592.562 +PHY-3002 : Step(4): len = 777443, overlap = 637.781 +PHY-3002 : Step(5): len = 600279, overlap = 721.844 +PHY-3002 : Step(6): len = 521980, overlap = 819.938 +PHY-3002 : Step(7): len = 451048, overlap = 893.281 +PHY-3002 : Step(8): len = 403911, overlap = 964.25 +PHY-3002 : Step(9): len = 368591, overlap = 1029.12 +PHY-3002 : Step(10): len = 338922, overlap = 1073.25 +PHY-3002 : Step(11): len = 304508, overlap = 1141.53 +PHY-3002 : Step(12): len = 279694, overlap = 1170.69 +PHY-3002 : Step(13): len = 252054, overlap = 1214.53 +PHY-3002 : Step(14): len = 238649, overlap = 1226.72 +PHY-3002 : Step(15): len = 215896, overlap = 1308.69 +PHY-3002 : Step(16): len = 208275, overlap = 1349.81 +PHY-3002 : Step(17): len = 186803, overlap = 1390.97 +PHY-3002 : Step(18): len = 181606, overlap = 1410.38 +PHY-3002 : Step(19): len = 161931, overlap = 1445.09 +PHY-3002 : Step(20): len = 158750, overlap = 1451.41 +PHY-3002 : Step(21): len = 144790, overlap = 1458.78 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.10227e-06 +PHY-3002 : Step(22): len = 145764, overlap = 1436.72 +PHY-3002 : Step(23): len = 171419, overlap = 1355.31 +PHY-3002 : Step(24): len = 181024, overlap = 1285.84 +PHY-3002 : Step(25): len = 190053, overlap = 1252.5 +PHY-3002 : Step(26): len = 189802, overlap = 1232.38 +PHY-3002 : Step(27): len = 188169, overlap = 1167.09 +PHY-3002 : Step(28): len = 186098, overlap = 1152.94 +PHY-3002 : Step(29): len = 184554, overlap = 1153.88 +PHY-3002 : Step(30): len = 182246, overlap = 1160.28 +PHY-3002 : Step(31): len = 180553, overlap = 1150.56 +PHY-3002 : Step(32): len = 178023, overlap = 1131 +PHY-3002 : Step(33): len = 175804, overlap = 1116.19 +PHY-3002 : Step(34): len = 172887, overlap = 1111.69 +PHY-3002 : Step(35): len = 172318, overlap = 1092.16 +PHY-3002 : Step(36): len = 170745, overlap = 1082.41 +PHY-3002 : Step(37): len = 170225, overlap = 1078.19 +PHY-3002 : Step(38): len = 168406, overlap = 1092.12 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.20454e-06 +PHY-3002 : Step(39): len = 173223, overlap = 1091 +PHY-3002 : Step(40): len = 183661, overlap = 1073.78 +PHY-3002 : Step(41): len = 187019, overlap = 1076.62 +PHY-3002 : Step(42): len = 191009, overlap = 1064.94 +PHY-3002 : Step(43): len = 192665, overlap = 1062.09 +PHY-3002 : Step(44): len = 195163, overlap = 1060.5 +PHY-3002 : Step(45): len = 192963, overlap = 1046.19 +PHY-3002 : Step(46): len = 193608, overlap = 1030.38 +PHY-3002 : Step(47): len = 192284, overlap = 1002.53 +PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.40908e-06 +PHY-3002 : Step(48): len = 200352, overlap = 983.75 +PHY-3002 : Step(49): len = 213737, overlap = 939.594 +PHY-3002 : Step(50): len = 219580, overlap = 886.688 +PHY-3002 : Step(51): len = 226210, overlap = 816.094 +PHY-3002 : Step(52): len = 229549, overlap = 804.75 +PHY-3002 : Step(53): len = 232138, overlap = 780.781 +PHY-3002 : Step(54): len = 233416, overlap = 765.125 +PHY-3002 : Step(55): len = 234157, overlap = 763 +PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.81817e-06 +PHY-3002 : Step(56): len = 245109, overlap = 742.219 +PHY-3002 : Step(57): len = 266212, overlap = 668.969 +PHY-3002 : Step(58): len = 277689, overlap = 618.844 +PHY-3002 : Step(59): len = 285405, overlap = 596.625 +PHY-3002 : Step(60): len = 288711, overlap = 579.406 +PHY-3002 : Step(61): len = 285269, overlap = 573.375 +PHY-3002 : Step(62): len = 282211, overlap = 567.625 +PHY-3002 : Step(63): len = 281487, overlap = 544.031 +PHY-3002 : Step(64): len = 281654, overlap = 536.062 +PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.76363e-05 +PHY-3002 : Step(65): len = 298684, overlap = 505.062 +PHY-3002 : Step(66): len = 312625, overlap = 481.625 +PHY-3002 : Step(67): len = 320174, overlap = 451.344 +PHY-3002 : Step(68): len = 324546, overlap = 454.938 +PHY-3002 : Step(69): len = 322533, overlap = 425.188 +PHY-3002 : Step(70): len = 326215, overlap = 428.062 +PHY-3002 : Step(71): len = 325562, overlap = 429.625 +PHY-3002 : Step(72): len = 328832, overlap = 411.375 +PHY-3002 : Step(73): len = 327893, overlap = 403.625 +PHY-3002 : Step(74): len = 328559, overlap = 392.656 +PHY-3002 : Step(75): len = 328014, overlap = 378.594 +PHY-3002 : Step(76): len = 327790, overlap = 361.219 +PHY-3002 : Step(77): len = 327386, overlap = 365.656 +PHY-3002 : Step(78): len = 327424, overlap = 361.812 +PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.52727e-05 +PHY-3002 : Step(79): len = 347844, overlap = 345 +PHY-3002 : Step(80): len = 360317, overlap = 330.156 +PHY-3002 : Step(81): len = 359507, overlap = 338.219 +PHY-3002 : Step(82): len = 360230, overlap = 363.219 +PHY-3002 : Step(83): len = 360958, overlap = 361.75 +PHY-3002 : Step(84): len = 363179, overlap = 337.781 +PHY-3002 : Step(85): len = 362174, overlap = 335.562 +PHY-3002 : Step(86): len = 365967, overlap = 331.625 +PHY-3002 : Step(87): len = 366931, overlap = 327.406 +PHY-3002 : Step(88): len = 369206, overlap = 313.719 +PHY-3002 : Step(89): len = 365751, overlap = 298.844 +PHY-3002 : Step(90): len = 366337, overlap = 287.688 +PHY-3002 : Step(91): len = 367062, overlap = 293.812 +PHY-3002 : Step(92): len = 368680, overlap = 292.719 +PHY-3002 : Step(93): len = 366044, overlap = 303.5 +PHY-3002 : Step(94): len = 365356, overlap = 315.25 +PHY-3002 : Step(95): len = 365794, overlap = 306.25 +PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.05453e-05 +PHY-3002 : Step(96): len = 383373, overlap = 294.125 +PHY-3002 : Step(97): len = 396682, overlap = 289.375 +PHY-3002 : Step(98): len = 396725, overlap = 271.656 +PHY-3002 : Step(99): len = 398660, overlap = 253.812 +PHY-3002 : Step(100): len = 402517, overlap = 254.156 +PHY-3002 : Step(101): len = 405673, overlap = 241.094 +PHY-3002 : Step(102): len = 403429, overlap = 252.25 +PHY-3002 : Step(103): len = 405140, overlap = 248.125 +PHY-3002 : Step(104): len = 407766, overlap = 237.375 +PHY-3002 : Step(105): len = 409418, overlap = 249.156 +PHY-3002 : Step(106): len = 405880, overlap = 239.969 +PHY-3002 : Step(107): len = 405662, overlap = 235.875 +PHY-3002 : Step(108): len = 406048, overlap = 232.312 +PHY-3002 : Step(109): len = 406902, overlap = 237.75 +PHY-3002 : Step(110): len = 404493, overlap = 248.5 +PHY-3002 : Step(111): len = 404712, overlap = 239.375 +PHY-3002 : Step(112): len = 406242, overlap = 226.094 +PHY-3002 : Step(113): len = 407166, overlap = 224.438 +PHY-3002 : Step(114): len = 404269, overlap = 228.969 +PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000136152 +PHY-3002 : Step(115): len = 418935, overlap = 227.062 +PHY-3002 : Step(116): len = 427384, overlap = 206.469 +PHY-3002 : Step(117): len = 425584, overlap = 205.844 +PHY-3002 : Step(118): len = 425470, overlap = 212.75 +PHY-3002 : Step(119): len = 428820, overlap = 206.594 +PHY-3002 : Step(120): len = 432309, overlap = 196.875 +PHY-3002 : Step(121): len = 430894, overlap = 197.094 +PHY-3002 : Step(122): len = 432789, overlap = 200.562 +PHY-3002 : Step(123): len = 436136, overlap = 200.344 +PHY-3002 : Step(124): len = 439101, overlap = 196.25 +PHY-3002 : Step(125): len = 436715, overlap = 199.156 +PHY-3002 : Step(126): len = 436613, overlap = 197.156 +PHY-3002 : Step(127): len = 439831, overlap = 196.281 +PHY-3002 : Step(128): len = 443685, overlap = 196.625 +PHY-3002 : Step(129): len = 441926, overlap = 189.938 +PHY-3002 : Step(130): len = 441301, overlap = 179.031 +PHY-3002 : Step(131): len = 442397, overlap = 184.125 +PHY-3002 : Step(132): len = 443133, overlap = 199.562 +PHY-3002 : Step(133): len = 441362, overlap = 195.719 +PHY-3002 : Step(134): len = 441255, overlap = 209.875 +PHY-3002 : Step(135): len = 442109, overlap = 207.469 +PHY-3002 : Step(136): len = 442607, overlap = 207.156 +PHY-3002 : Step(137): len = 441272, overlap = 203.031 +PHY-3002 : Step(138): len = 441832, overlap = 203.344 +PHY-3002 : Step(139): len = 443179, overlap = 212.375 +PHY-3002 : Step(140): len = 444519, overlap = 214.75 +PHY-3002 : Step(141): len = 442739, overlap = 209.094 +PHY-3002 : Step(142): len = 442473, overlap = 207.844 +PHY-3002 : Step(143): len = 443263, overlap = 205.531 +PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000272303 +PHY-3002 : Step(144): len = 455518, overlap = 195.062 +PHY-3002 : Step(145): len = 464702, overlap = 185.5 +PHY-3002 : Step(146): len = 464857, overlap = 180.531 +PHY-3002 : Step(147): len = 465637, overlap = 183.438 +PHY-3002 : Step(148): len = 468027, overlap = 192.156 +PHY-3002 : Step(149): len = 469099, overlap = 190.906 +PHY-3002 : Step(150): len = 467659, overlap = 192.344 +PHY-3002 : Step(151): len = 467713, overlap = 188.438 +PHY-3002 : Step(152): len = 470120, overlap = 192.5 +PHY-3002 : Step(153): len = 472631, overlap = 190.406 +PHY-3002 : Step(154): len = 472240, overlap = 188.5 +PHY-3002 : Step(155): len = 472491, overlap = 190.688 +PHY-3002 : Step(156): len = 473540, overlap = 190.875 +PHY-3002 : Step(157): len = 473764, overlap = 188.156 +PHY-3002 : Step(158): len = 472836, overlap = 191.719 +PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000517479 +PHY-3002 : Step(159): len = 481783, overlap = 185.75 +PHY-3002 : Step(160): len = 489324, overlap = 173.531 +PHY-3002 : Step(161): len = 490952, overlap = 175.844 +PHY-3002 : Step(162): len = 491576, overlap = 179.406 +PHY-3002 : Step(163): len = 493038, overlap = 172.75 +PHY-3002 : Step(164): len = 494288, overlap = 172.031 +PHY-3002 : Step(165): len = 494102, overlap = 170.969 +PHY-3002 : Step(166): len = 494482, overlap = 171.281 +PHY-3002 : Step(167): len = 495592, overlap = 167.562 +PHY-3002 : Step(168): len = 496404, overlap = 160.312 +PHY-3002 : Step(169): len = 496139, overlap = 161.219 +PHY-3002 : Step(170): len = 496343, overlap = 161.719 +PHY-3002 : Step(171): len = 497891, overlap = 156.531 +PHY-3002 : Step(172): len = 499031, overlap = 157.719 +PHY-3002 : Step(173): len = 498589, overlap = 156.281 +PHY-3002 : Step(174): len = 498494, overlap = 157.719 +PHY-3002 : Step(175): len = 498990, overlap = 159.594 +PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100707 +PHY-3002 : Step(176): len = 503830, overlap = 152.062 +PHY-3002 : Step(177): len = 509893, overlap = 150.5 +PHY-3002 : Step(178): len = 511435, overlap = 152.344 +PHY-3002 : Step(179): len = 512388, overlap = 133.812 +PHY-3002 : Step(180): len = 513505, overlap = 133.719 +PHY-3002 : Step(181): len = 514467, overlap = 129.719 +PHY-3002 : Step(182): len = 515230, overlap = 135.812 +PHY-3002 : Step(183): len = 516003, overlap = 136.906 +PHY-3002 : Step(184): len = 516865, overlap = 134.562 +PHY-3002 : Step(185): len = 517779, overlap = 130.688 +PHY-3002 : Step(186): len = 518736, overlap = 132.719 +PHY-3002 : Step(187): len = 519811, overlap = 126.688 +PHY-3002 : Step(188): len = 520285, overlap = 126.156 +PHY-3002 : Step(189): len = 520609, overlap = 125.312 +PHY-3002 : Step(190): len = 521783, overlap = 127.844 +PHY-3002 : Step(191): len = 524804, overlap = 133.906 +PHY-3002 : Step(192): len = 525311, overlap = 128.094 +PHY-3002 : Step(193): len = 525522, overlap = 127.75 +PHY-3002 : Step(194): len = 525992, overlap = 130.906 +PHY-3002 : Step(195): len = 526317, overlap = 127.812 +PHY-3002 : Step(196): len = 526461, overlap = 129.562 +PHY-3002 : Step(197): len = 526651, overlap = 128.719 +PHY-3002 : Step(198): len = 526598, overlap = 125.625 +PHY-3002 : Step(199): len = 526598, overlap = 125.625 +PHY-3002 : Step(200): len = 526552, overlap = 127.5 +PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00175132 +PHY-3002 : Step(201): len = 530576, overlap = 126.094 +PHY-3002 : Step(202): len = 538601, overlap = 110.594 +PHY-3002 : Step(203): len = 541750, overlap = 108.5 +PHY-3002 : Step(204): len = 544652, overlap = 105.531 +PHY-3002 : Step(205): len = 547197, overlap = 106.688 +PHY-3002 : Step(206): len = 548616, overlap = 102.438 +PHY-3002 : Step(207): len = 548103, overlap = 107.719 +PHY-3002 : Step(208): len = 547931, overlap = 106.031 +PHY-3002 : Step(209): len = 548688, overlap = 104.594 +PHY-3002 : Step(210): len = 548850, overlap = 104.406 +PHY-3002 : Step(211): len = 548658, overlap = 104.156 +PHY-3002 : Step(212): len = 548451, overlap = 102.812 +PHY-3002 : Step(213): len = 548705, overlap = 102.719 +PHY-3002 : Step(214): len = 549232, overlap = 110.531 +PHY-3002 : Step(215): len = 548966, overlap = 110.062 +PHY-3002 : Step(216): len = 548965, overlap = 106.812 +PHY-3002 : Step(217): len = 549793, overlap = 107.031 +PHY-3002 : Step(218): len = 550809, overlap = 106.312 +PHY-3002 : Step(219): len = 550869, overlap = 103.344 +PHY-3002 : Step(220): len = 550943, overlap = 103.188 +PHY-3002 : Step(221): len = 551329, overlap = 103.625 +PHY-3002 : Step(222): len = 551423, overlap = 103.688 +PHY-3002 : Step(223): len = 551233, overlap = 103.312 +PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00283364 +PHY-3002 : Step(224): len = 553382, overlap = 104.562 +PHY-3002 : Step(225): len = 556308, overlap = 104.5 +PHY-3002 : Step(226): len = 557092, overlap = 103.656 +PHY-3002 : Step(227): len = 557701, overlap = 103.594 +PHY-3002 : Step(228): len = 559575, overlap = 101.031 +PHY-3002 : Step(229): len = 561650, overlap = 102.812 +PHY-3002 : Step(230): len = 561954, overlap = 101.875 +PHY-3002 : Step(231): len = 562121, overlap = 101.688 +PHY-3002 : Step(232): len = 562575, overlap = 103.812 +PHY-3002 : Step(233): len = 563080, overlap = 103.562 +PHY-3002 : Step(234): len = 563399, overlap = 102.906 +PHY-3002 : Step(235): len = 563656, overlap = 109.125 +PHY-3002 : Step(236): len = 564193, overlap = 114.281 +PHY-3002 : Step(237): len = 564456, overlap = 114.406 +PHY-3002 : Step(238): len = 564464, overlap = 115.469 PHY-3001 : Legalization ... -PHY-3001 : End legalization; 0.014376s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (434.7%) +PHY-3001 : End legalization; 0.014158s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (110.4%) PHY-3001 : Run with size of 4 -PHY-3001 : Cell area utilization is 56% +PHY-3001 : Cell area utilization is 55% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... RUN-1001 : Building simple global routing graph ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 0/20891. +PHY-1001 : Reuse net number 0/20260. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 706104, over cnt = 1605(4%), over = 7585, worst = 45 -PHY-1001 : End global iterations; 0.688595s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (136.1%) +PHY-1002 : len = 742288, over cnt = 1602(4%), over = 6977, worst = 39 +PHY-1001 : End global iterations; 0.659622s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (139.8%) -PHY-1001 : Congestion index: top1 = 81.38, top5 = 61.13, top10 = 52.56, top15 = 47.12. -PHY-3001 : End congestion estimation; 0.911135s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (126.9%) +PHY-1001 : Congestion index: top1 = 77.52, top5 = 59.55, top10 = 51.12, top15 = 45.77. +PHY-3001 : End congestion estimation; 0.889029s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (128.3%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 20713 nets completely. +TMR-2504 : Update delay of 20082 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 0.876627s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.6%) +PHY-3001 : End timing update; 0.874409s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.1%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000147396 -PHY-3002 : Step(239): len = 641511, overlap = 105.406 -PHY-3002 : Step(240): len = 640037, overlap = 96.4375 -PHY-3002 : Step(241): len = 635785, overlap = 90.5938 -PHY-3002 : Step(242): len = 635141, overlap = 80.8438 -PHY-3002 : Step(243): len = 635198, overlap = 74.8125 -PHY-3002 : Step(244): len = 631981, overlap = 69.3125 -PHY-3002 : Step(245): len = 628790, overlap = 63.875 -PHY-3002 : Step(246): len = 627388, overlap = 61.75 -PHY-3002 : Step(247): len = 624297, overlap = 57.1875 -PHY-3002 : Step(248): len = 620643, overlap = 57.3125 -PHY-3002 : Step(249): len = 618809, overlap = 59.7188 -PHY-3002 : Step(250): len = 616473, overlap = 58.375 -PHY-3002 : Step(251): len = 614842, overlap = 52.0312 -PHY-3002 : Step(252): len = 614370, overlap = 51.6562 -PHY-3002 : Step(253): len = 613433, overlap = 50.5938 -PHY-3002 : Step(254): len = 612101, overlap = 51.4375 -PHY-3002 : Step(255): len = 611656, overlap = 55.5312 -PHY-3002 : Step(256): len = 609221, overlap = 55.7812 -PHY-3002 : Step(257): len = 607441, overlap = 55.875 -PHY-3002 : Step(258): len = 605551, overlap = 56.7812 -PHY-3002 : Step(259): len = 603713, overlap = 56.9375 -PHY-3002 : Step(260): len = 601945, overlap = 58.375 -PHY-3002 : Step(261): len = 600761, overlap = 58.9688 -PHY-3002 : Step(262): len = 599246, overlap = 57.5312 -PHY-3002 : Step(263): len = 598384, overlap = 54.0625 -PHY-3002 : Step(264): len = 597774, overlap = 54.0312 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000294791 -PHY-3002 : Step(265): len = 602124, overlap = 52.9062 -PHY-3002 : Step(266): len = 602124, overlap = 52.9062 -PHY-3002 : Step(267): len = 602455, overlap = 51.9375 +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000134098 +PHY-3002 : Step(239): len = 674162, overlap = 73.5 +PHY-3002 : Step(240): len = 670596, overlap = 61.3125 +PHY-3002 : Step(241): len = 668312, overlap = 59.5625 +PHY-3002 : Step(242): len = 662072, overlap = 55.0625 +PHY-3002 : Step(243): len = 659219, overlap = 46.6562 +PHY-3002 : Step(244): len = 654533, overlap = 41.7188 +PHY-3002 : Step(245): len = 653845, overlap = 38.3438 +PHY-3002 : Step(246): len = 652502, overlap = 32.7812 +PHY-3002 : Step(247): len = 651565, overlap = 29 +PHY-3002 : Step(248): len = 649002, overlap = 29.2812 +PHY-3002 : Step(249): len = 647118, overlap = 26.875 +PHY-3002 : Step(250): len = 645340, overlap = 23.5 +PHY-3002 : Step(251): len = 644071, overlap = 22.3125 +PHY-3002 : Step(252): len = 642522, overlap = 22.6562 +PHY-3002 : Step(253): len = 643069, overlap = 19.5 +PHY-3002 : Step(254): len = 642226, overlap = 19.8438 +PHY-3002 : Step(255): len = 641386, overlap = 18.8438 +PHY-3002 : Step(256): len = 640522, overlap = 20.3125 +PHY-3002 : Step(257): len = 641564, overlap = 18.2188 +PHY-3002 : Step(258): len = 641706, overlap = 18.5938 +PHY-3002 : Step(259): len = 640729, overlap = 18.1875 +PHY-3002 : Step(260): len = 639333, overlap = 17.6562 +PHY-3002 : Step(261): len = 637600, overlap = 21.125 +PHY-3002 : Step(262): len = 635940, overlap = 22.1875 +PHY-3002 : Step(263): len = 634881, overlap = 26.125 +PHY-3002 : Step(264): len = 633529, overlap = 27.4375 +PHY-3002 : Step(265): len = 632208, overlap = 30.0312 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000268196 +PHY-3002 : Step(266): len = 633978, overlap = 28.4688 +PHY-3002 : Step(267): len = 636544, overlap = 29.0625 PHY-3001 : Run with size of 2 -PHY-3001 : Cell area utilization is 56% +PHY-3001 : Cell area utilization is 55% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 102/20891. +PHY-1001 : Reuse net number 44/20260. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 684712, over cnt = 2538(7%), over = 10926, worst = 61 -PHY-1001 : End global iterations; 1.668208s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (128.3%) +PHY-1002 : len = 722688, over cnt = 2639(7%), over = 11351, worst = 45 +PHY-1001 : End global iterations; 1.654921s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (135.0%) -PHY-1001 : Congestion index: top1 = 79.40, top5 = 62.52, top10 = 54.61, top15 = 49.89. -PHY-3001 : End congestion estimation; 1.942959s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (123.8%) +PHY-1001 : Congestion index: top1 = 79.96, top5 = 64.73, top10 = 56.49, top15 = 51.40. +PHY-3001 : End congestion estimation; 1.929596s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (130.4%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 20713 nets completely. +TMR-2504 : Update delay of 20082 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 0.903062s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.4%) +PHY-3001 : End timing update; 0.882366s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.2%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.83893e-05 -PHY-3002 : Step(268): len = 602232, overlap = 264.625 -PHY-3002 : Step(269): len = 606216, overlap = 234.656 -PHY-3002 : Step(270): len = 600744, overlap = 225.219 -PHY-3002 : Step(271): len = 599256, overlap = 214.812 -PHY-3002 : Step(272): len = 596499, overlap = 207.125 -PHY-3002 : Step(273): len = 593592, overlap = 190.25 -PHY-3002 : Step(274): len = 593046, overlap = 180.375 -PHY-3002 : Step(275): len = 589416, overlap = 180.781 -PHY-3002 : Step(276): len = 587384, overlap = 179.938 -PHY-3002 : Step(277): len = 586438, overlap = 174.219 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000156779 -PHY-3002 : Step(278): len = 585723, overlap = 170.719 -PHY-3002 : Step(279): len = 588639, overlap = 164.906 -PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000298785 -PHY-3002 : Step(280): len = 597053, overlap = 150.094 -PHY-3002 : Step(281): len = 605801, overlap = 136.844 -PHY-3002 : Step(282): len = 609405, overlap = 129 -PHY-3002 : Step(283): len = 609633, overlap = 127.938 -PHY-3002 : Step(284): len = 609883, overlap = 125.094 -PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000597571 -PHY-3002 : Step(285): len = 612494, overlap = 118.562 -PHY-3002 : Step(286): len = 618492, overlap = 112.938 -PHY-3002 : Step(287): len = 622904, overlap = 102.719 +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.45711e-05 +PHY-3002 : Step(268): len = 634348, overlap = 279.812 +PHY-3002 : Step(269): len = 639507, overlap = 216.344 +PHY-3002 : Step(270): len = 638353, overlap = 198.625 +PHY-3002 : Step(271): len = 634382, overlap = 177.656 +PHY-3002 : Step(272): len = 632561, overlap = 168.781 +PHY-3002 : Step(273): len = 632299, overlap = 158.906 +PHY-3002 : Step(274): len = 629659, overlap = 151.312 +PHY-3002 : Step(275): len = 626125, overlap = 147.844 +PHY-3002 : Step(276): len = 625185, overlap = 141.875 +PHY-3002 : Step(277): len = 623351, overlap = 138.406 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000189142 +PHY-3002 : Step(278): len = 623152, overlap = 137.344 +PHY-3002 : Step(279): len = 625031, overlap = 133.312 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000341742 +PHY-3002 : Step(280): len = 627249, overlap = 124.875 +PHY-3002 : Step(281): len = 634382, overlap = 114.781 +PHY-3002 : Step(282): len = 641077, overlap = 110.656 +PHY-3002 : Step(283): len = 647090, overlap = 103.875 +PHY-3002 : Step(284): len = 649306, overlap = 99.7812 OPT-1001 : Start physical optimization ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84569, tnet num: 20082, tinst num: 17680, tnode num: 114836, tedge num: 135704. TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.460893s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.5%) +RUN-1003 : finish command "start_timer -report" in 1.464396s wall, 1.375000s user + 0.078125s system = 1.453125s CPU (99.2%) -RUN-1004 : used memory is 596 MB, reserved memory is 578 MB, peak memory is 734 MB -OPT-1001 : Total overflow 433.69 peak overflow 3.00 +RUN-1004 : used memory is 581 MB, reserved memory is 563 MB, peak memory is 716 MB +OPT-1001 : Total overflow 437.66 peak overflow 4.34 OPT-1001 : Start high-fanout net optimization ... OPT-1001 : Update timing in global mode PHY-1001 : Start incremental global routing, caller is place ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 1484/20891. +PHY-1001 : Reuse net number 1293/20260. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 721464, over cnt = 3027(8%), over = 11212, worst = 32 -PHY-1001 : End global iterations; 1.187443s wall, 1.734375s user + 0.046875s system = 1.781250s CPU (150.0%) +PHY-1002 : len = 750200, over cnt = 3025(8%), over = 11597, worst = 30 +PHY-1001 : End global iterations; 1.164716s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (143.5%) -PHY-1001 : Congestion index: top1 = 70.32, top5 = 57.04, top10 = 50.86, top15 = 47.22. -PHY-1001 : End incremental global routing; 1.526473s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (138.2%) +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.18, top10 = 52.60, top15 = 48.96. +PHY-1001 : End incremental global routing; 1.501090s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (133.2%) TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 20713 nets completely. +TMR-2504 : Update delay of 20082 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.952616s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.1%) +OPT-1001 : End timing update; 0.924389s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.4%) -OPT-1001 : 50 high-fanout net processed. +OPT-1001 : 51 high-fanout net processed. PHY-3001 : Start incremental placement ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 18176 has valid locations, 336 needs to be replaced -PHY-3001 : design contains 18597 instances, 7580 luts, 9796 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 6584 pins -PHY-3001 : Found 1231 cells with 2 region constraints. +PHY-3001 : eco cells: 17544 has valid locations, 333 needs to be replaced +PHY-3001 : design contains 17962 instances, 7448 luts, 9293 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 6083 pins +PHY-3001 : Found 1246 cells with 2 region constraints. PHY-3001 : Global placement ... -PHY-3001 : Initial: Len = 646398 +PHY-3001 : Initial: Len = 673789 PHY-3001 : Run with size of 4 -PHY-3001 : Cell area utilization is 57% +PHY-3001 : Cell area utilization is 56% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16965/21177. +PHY-1001 : Reuse net number 16643/20542. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 736936, over cnt = 3085(8%), over = 11319, worst = 32 -PHY-1001 : End global iterations; 0.236596s wall, 0.375000s user + 0.046875s system = 0.421875s CPU (178.3%) +PHY-1002 : len = 764288, over cnt = 3037(8%), over = 11623, worst = 30 +PHY-1001 : End global iterations; 0.245305s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (159.2%) -PHY-1001 : Congestion index: top1 = 70.15, top5 = 57.25, top10 = 51.37, top15 = 47.64. -PHY-3001 : End congestion estimation; 0.492914s wall, 0.609375s user + 0.046875s system = 0.656250s CPU (133.1%) +PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.30, top10 = 52.75, top15 = 49.18. +PHY-3001 : End congestion estimation; 0.512588s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (125.0%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88307, tnet num: 20999, tinst num: 18597, tnode num: 120641, tedge num: 141346. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85707, tnet num: 20364, tinst num: 17962, tnode num: 116573, tedge num: 137416. TMR-2508 : Levelizing timing graph completed, there are 25 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.476353s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.5%) +RUN-1003 : finish command "start_timer -report" in 1.467541s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (100.1%) -RUN-1004 : used memory is 642 MB, reserved memory is 641 MB, peak memory is 740 MB +RUN-1004 : used memory is 626 MB, reserved memory is 630 MB, peak memory is 720 MB TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 20999 nets completely. +TMR-2504 : Update delay of 20364 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 2.836114s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (100.3%) +PHY-3001 : End timing update; 2.432119s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (100.2%) PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 -PHY-3002 : Step(288): len = 645449, overlap = 0.28125 -PHY-3002 : Step(289): len = 645089, overlap = 0.1875 -PHY-3002 : Step(290): len = 644945, overlap = 0.125 -PHY-3002 : Step(291): len = 644686, overlap = 0.1875 +PHY-3002 : Step(285): len = 672646, overlap = 1.375 +PHY-3002 : Step(286): len = 672026, overlap = 1.375 +PHY-3002 : Step(287): len = 671652, overlap = 1.5 +PHY-3002 : Step(288): len = 671270, overlap = 1.5 PHY-3001 : Run with size of 2 -PHY-3001 : Cell area utilization is 57% +PHY-3001 : Cell area utilization is 56% PHY-3001 : Analyzing congestion ... PHY-1001 : Generate routing nets ... PHY-1001 : Incremental mode ON -PHY-1001 : Reuse net number 17109/21177. +PHY-1001 : Reuse net number 16759/20542. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 735064, over cnt = 3094(8%), over = 11333, worst = 32 -PHY-1001 : End global iterations; 0.184287s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (152.6%) +PHY-1002 : len = 761576, over cnt = 3040(8%), over = 11693, worst = 30 +PHY-1001 : End global iterations; 0.217945s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (121.9%) -PHY-1001 : Congestion index: top1 = 70.75, top5 = 57.57, top10 = 51.49, top15 = 47.80. -PHY-3001 : End congestion estimation; 0.439402s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.9%) +PHY-1001 : Congestion index: top1 = 69.40, top5 = 58.58, top10 = 52.80, top15 = 49.30. +PHY-3001 : End congestion estimation; 0.514184s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (109.4%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 20999 nets completely. +TMR-2504 : Update delay of 20364 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 1.327813s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.0%) +PHY-3001 : End timing update; 1.041445s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (100.5%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000425296 -PHY-3002 : Step(292): len = 644677, overlap = 104.375 -PHY-3002 : Step(293): len = 644738, overlap = 104.812 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000850593 -PHY-3002 : Step(294): len = 644784, overlap = 105.688 -PHY-3002 : Step(295): len = 645163, overlap = 106.156 -PHY-3001 : Final: Len = 645163, Over = 106.156 -PHY-3001 : End incremental placement; 5.757935s wall, 6.187500s user + 0.156250s system = 6.343750s CPU (110.2%) +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000435663 +PHY-3002 : Step(289): len = 671244, overlap = 101.719 +PHY-3002 : Step(290): len = 671463, overlap = 101.938 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000871325 +PHY-3002 : Step(291): len = 671601, overlap = 101.75 +PHY-3002 : Step(292): len = 671936, overlap = 102.031 +PHY-3001 : Final: Len = 671936, Over = 102.031 +PHY-3001 : End incremental placement; 5.176966s wall, 5.546875s user + 0.250000s system = 5.796875s CPU (112.0%) -OPT-1001 : Total overflow 440.84 peak overflow 3.00 -OPT-1001 : End high-fanout net optimization; 8.788392s wall, 9.781250s user + 0.218750s system = 10.000000s CPU (113.8%) +OPT-1001 : Total overflow 441.78 peak overflow 4.34 +OPT-1001 : End high-fanout net optimization; 8.148556s wall, 9.125000s user + 0.265625s system = 9.390625s CPU (115.2%) -OPT-1001 : Current memory(MB): used = 741, reserve = 729, peak = 759. +OPT-1001 : Current memory(MB): used = 723, reserve = 710, peak = 740. OPT-1001 : Start bottleneck based optimization ... OPT-1001 : Start congestion update ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 17031/21177. +PHY-1001 : Reuse net number 16686/20542. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 738344, over cnt = 3046(8%), over = 10371, worst = 32 -PHY-1002 : len = 787592, over cnt = 2141(6%), over = 5560, worst = 22 -PHY-1002 : len = 839104, over cnt = 840(2%), over = 1899, worst = 15 -PHY-1002 : len = 860952, over cnt = 225(0%), over = 430, worst = 11 -PHY-1002 : len = 868704, over cnt = 15(0%), over = 15, worst = 1 -PHY-1001 : End global iterations; 2.151436s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (132.9%) +PHY-1002 : len = 765152, over cnt = 3002(8%), over = 10538, worst = 30 +PHY-1002 : len = 812976, over cnt = 2132(6%), over = 5931, worst = 20 +PHY-1002 : len = 868056, over cnt = 761(2%), over = 1696, worst = 16 +PHY-1002 : len = 884888, over cnt = 289(0%), over = 690, worst = 16 +PHY-1002 : len = 896184, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.062124s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (132.6%) -PHY-1001 : Congestion index: top1 = 57.20, top5 = 50.49, top10 = 46.81, top15 = 44.58. -OPT-1001 : End congestion update; 2.414332s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (130.1%) +PHY-1001 : Congestion index: top1 = 58.60, top5 = 51.57, top10 = 47.85, top15 = 45.55. +OPT-1001 : End congestion update; 2.343490s wall, 3.000000s user + 0.015625s system = 3.015625s CPU (128.7%) OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 20999 nets completely. +TMR-2504 : Update delay of 20364 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.861345s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%) +OPT-1001 : End timing update; 0.987732s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (99.7%) OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0 -OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 17592 slack improved -OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 40 cells processed and 5550 slack improved -OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 350 slack improved -OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved -OPT-1001 : End bottleneck based optimization; 3.685889s wall, 4.390625s user + 0.015625s system = 4.406250s CPU (119.5%) +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 111 cells processed and 15600 slack improved +OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 3350 slack improved +OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 2850 slack improved +OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 300 slack improved +OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 600 slack improved +OPT-1001 : End bottleneck based optimization; 3.821868s wall, 4.453125s user + 0.031250s system = 4.484375s CPU (117.3%) -OPT-1001 : Current memory(MB): used = 718, reserve = 708, peak = 759. +OPT-1001 : Current memory(MB): used = 702, reserve = 693, peak = 740. OPT-1001 : Start path based optimization ... OPT-1001 : Start congestion update ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 17073/21182. +PHY-1001 : Reuse net number 16732/20547. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 869152, over cnt = 117(0%), over = 155, worst = 5 -PHY-1002 : len = 868936, over cnt = 77(0%), over = 92, worst = 4 -PHY-1002 : len = 869448, over cnt = 28(0%), over = 29, worst = 2 -PHY-1002 : len = 869560, over cnt = 17(0%), over = 17, worst = 1 -PHY-1002 : len = 870112, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.740435s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.4%) +PHY-1002 : len = 896176, over cnt = 90(0%), over = 123, worst = 4 +PHY-1002 : len = 895912, over cnt = 56(0%), over = 66, worst = 3 +PHY-1002 : len = 896008, over cnt = 6(0%), over = 6, worst = 1 +PHY-1002 : len = 896072, over cnt = 4(0%), over = 4, worst = 1 +PHY-1002 : len = 896248, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.741561s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.2%) -PHY-1001 : Congestion index: top1 = 56.85, top5 = 50.10, top10 = 46.58, top15 = 44.41. -OPT-1001 : End congestion update; 1.011846s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (103.5%) +PHY-1001 : Congestion index: top1 = 58.62, top5 = 51.34, top10 = 47.68, top15 = 45.38. +OPT-1001 : End congestion update; 1.009068s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (102.2%) OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 21004 nets completely. +TMR-2504 : Update delay of 20369 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.823754s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.6%) +OPT-1001 : End timing update; 0.793360s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%) OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 -OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 7500 slack improved +OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 4050 slack improved OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved -OPT-1001 : End path based optimization; 1.954227s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (101.5%) +OPT-1001 : End path based optimization; 1.917433s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (101.0%) -OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 759. -OPT-1001 : End physical optimization; 16.200395s wall, 17.875000s user + 0.296875s system = 18.171875s CPU (112.2%) +OPT-1001 : Current memory(MB): used = 710, reserve = 697, peak = 740. +OPT-1001 : End physical optimization; 15.654895s wall, 17.265625s user + 0.421875s system = 17.687500s CPU (113.0%) PHY-3001 : Start packing ... SYN-4007 : Packing 0 MUX to BLE ... SYN-4008 : Packed 0 MUX and 0 SEQ to BLE. -SYN-4007 : Packing 7580 LUT to BLE ... -SYN-4008 : Packed 7580 LUT and 3158 SEQ to BLE. -SYN-4003 : Packing 6643 remaining SEQ's ... -SYN-4005 : Packed 3910 SEQ with LUT/SLICE -SYN-4006 : 811 single LUT's are left -SYN-4006 : 2733 single SEQ's are left -SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10313/15192 primitive instances ... -PHY-3001 : End packing; 1.740255s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.7%) +SYN-4007 : Packing 7448 LUT to BLE ... +SYN-4008 : Packed 7448 LUT and 3135 SEQ to BLE. +SYN-4003 : Packing 6163 remaining SEQ's ... +SYN-4005 : Packed 3681 SEQ with LUT/SLICE +SYN-4006 : 927 single LUT's are left +SYN-4006 : 2482 single SEQ's are left +SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9930/13785 primitive instances ... +PHY-3001 : End packing; 1.602062s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.5%) PHY-1001 : Populate physical database on model huagao_mipi_top. -RUN-1001 : There are total 7112 instances -RUN-1001 : 3482 mslices, 3482 lslices, 75 pads, 58 brams, 3 dsps -RUN-1001 : There are total 18155 nets +RUN-1001 : There are total 6896 instances +RUN-1001 : 3374 mslices, 3374 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17545 nets RUN-6004 WARNING: There are 20 nets with only 1 pin. -RUN-1001 : 10478 nets have 2 pins -RUN-1001 : 5820 nets have [3 - 5] pins -RUN-1001 : 1171 nets have [6 - 10] pins -RUN-1001 : 318 nets have [11 - 20] pins -RUN-1001 : 336 nets have [21 - 99] pins +RUN-1001 : 9851 nets have 2 pins +RUN-1001 : 6027 nets have [3 - 5] pins +RUN-1001 : 967 nets have [6 - 10] pins +RUN-1001 : 327 nets have [11 - 20] pins +RUN-1001 : 341 nets have [21 - 99] pins RUN-1001 : 12 nets have 100+ pins -PHY-3001 : design contains 7110 instances, 6964 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3890 pins -PHY-3001 : Found 481 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : After packing: Len = 658208, Over = 310.5 +PHY-3001 : design contains 6894 instances, 6748 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3610 pins +PHY-3001 : Found 501 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : After packing: Len = 682532, Over = 287.5 PHY-3001 : Run with size of 2 -PHY-3001 : Cell area utilization is 76% +PHY-3001 : Cell area utilization is 74% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 7633/18155. +PHY-1001 : Reuse net number 7667/17545. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 812144, over cnt = 2024(5%), over = 3420, worst = 9 -PHY-1002 : len = 820920, over cnt = 1386(3%), over = 2044, worst = 7 -PHY-1002 : len = 830728, over cnt = 842(2%), over = 1233, worst = 6 -PHY-1002 : len = 843928, over cnt = 332(0%), over = 466, worst = 6 -PHY-1002 : len = 852432, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 1.661414s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (135.4%) +PHY-1002 : len = 840296, over cnt = 1918(5%), over = 3183, worst = 8 +PHY-1002 : len = 848552, over cnt = 1237(3%), over = 1777, worst = 7 +PHY-1002 : len = 859040, over cnt = 629(1%), over = 897, worst = 7 +PHY-1002 : len = 867864, over cnt = 283(0%), over = 378, worst = 7 +PHY-1002 : len = 874280, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 1.605348s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (145.0%) -PHY-1001 : Congestion index: top1 = 59.09, top5 = 50.37, top10 = 46.64, top15 = 44.09. -PHY-3001 : End congestion estimation; 2.063662s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (128.7%) +PHY-1001 : Congestion index: top1 = 58.90, top5 = 50.94, top10 = 47.01, top15 = 44.61. +PHY-3001 : End congestion estimation; 1.995014s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (137.1%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7110, tnode num: 99613, tedge num: 127314. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73662, tnet num: 17367, tinst num: 6894, tnode num: 96251, tedge num: 123708. TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.666912s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.3%) +RUN-1003 : finish command "start_timer -report" in 1.617917s wall, 1.562500s user + 0.046875s system = 1.609375s CPU (99.5%) -RUN-1004 : used memory is 639 MB, reserved memory is 634 MB, peak memory is 759 MB +RUN-1004 : used memory is 622 MB, reserved memory is 612 MB, peak memory is 740 MB TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 17977 nets completely. +TMR-2504 : Update delay of 17367 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 2.574225s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (100.2%) +PHY-3001 : End timing update; 2.530576s wall, 2.468750s user + 0.062500s system = 2.531250s CPU (100.0%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.15623e-05 -PHY-3002 : Step(296): len = 644818, overlap = 308.5 -PHY-3002 : Step(297): len = 638418, overlap = 308.25 -PHY-3002 : Step(298): len = 634474, overlap = 314.25 -PHY-3002 : Step(299): len = 632259, overlap = 317 -PHY-3002 : Step(300): len = 630446, overlap = 318.25 -PHY-3002 : Step(301): len = 628888, overlap = 310.25 -PHY-3002 : Step(302): len = 627240, overlap = 304.5 -PHY-3002 : Step(303): len = 625948, overlap = 300 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.31246e-05 -PHY-3002 : Step(304): len = 630038, overlap = 294.25 -PHY-3002 : Step(305): len = 633929, overlap = 286.75 -PHY-3002 : Step(306): len = 633553, overlap = 288.5 -PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000166249 -PHY-3002 : Step(307): len = 644507, overlap = 273.25 -PHY-3002 : Step(308): len = 652926, overlap = 259 -PHY-3002 : Step(309): len = 651075, overlap = 265.75 -PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000332498 -PHY-3002 : Step(310): len = 659753, overlap = 252.75 -PHY-3002 : Step(311): len = 674197, overlap = 230 -PHY-3002 : Step(312): len = 672323, overlap = 229.5 -PHY-3002 : Step(313): len = 670444, overlap = 225.25 -PHY-3002 : Step(314): len = 670963, overlap = 218.75 +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.53163e-05 +PHY-3002 : Step(293): len = 672031, overlap = 281.5 +PHY-3002 : Step(294): len = 665879, overlap = 283.75 +PHY-3002 : Step(295): len = 661339, overlap = 284.25 +PHY-3002 : Step(296): len = 657755, overlap = 275.5 +PHY-3002 : Step(297): len = 655544, overlap = 272.25 +PHY-3002 : Step(298): len = 653398, overlap = 277.75 +PHY-3002 : Step(299): len = 651231, overlap = 279.75 +PHY-3002 : Step(300): len = 649348, overlap = 278.5 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.06325e-05 +PHY-3002 : Step(301): len = 652932, overlap = 268 +PHY-3002 : Step(302): len = 657516, overlap = 255 +PHY-3002 : Step(303): len = 658296, overlap = 254 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000181265 +PHY-3002 : Step(304): len = 669665, overlap = 239.25 +PHY-3002 : Step(305): len = 678322, overlap = 229.75 +PHY-3002 : Step(306): len = 677223, overlap = 229 PHY-3001 : Legalization ... -PHY-3001 : End legalization; 0.377444s wall, 0.421875s user + 0.546875s system = 0.968750s CPU (256.7%) +PHY-3001 : End legalization; 0.330318s wall, 0.234375s user + 0.578125s system = 0.812500s CPU (246.0%) -PHY-3001 : Trial Legalized: Len = 754658 +PHY-3001 : Trial Legalized: Len = 757736 PHY-3001 : Run with size of 2 -PHY-3001 : Cell area utilization is 76% +PHY-3001 : Cell area utilization is 73% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 690/18155. +PHY-1001 : Reuse net number 793/17545. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 872960, over cnt = 2762(7%), over = 4649, worst = 6 -PHY-1002 : len = 890384, over cnt = 1683(4%), over = 2460, worst = 6 -PHY-1002 : len = 911080, over cnt = 619(1%), over = 883, worst = 6 -PHY-1002 : len = 920896, over cnt = 198(0%), over = 280, worst = 4 -PHY-1002 : len = 925576, over cnt = 6(0%), over = 6, worst = 1 -PHY-1001 : End global iterations; 2.382388s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (146.9%) +PHY-1002 : len = 877440, over cnt = 2744(7%), over = 4613, worst = 8 +PHY-1002 : len = 893744, over cnt = 1693(4%), over = 2544, worst = 8 +PHY-1002 : len = 917680, over cnt = 558(1%), over = 770, worst = 8 +PHY-1002 : len = 925560, over cnt = 213(0%), over = 305, worst = 4 +PHY-1002 : len = 929944, over cnt = 17(0%), over = 22, worst = 3 +PHY-1001 : End global iterations; 2.288810s wall, 3.515625s user + 0.046875s system = 3.562500s CPU (155.6%) -PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.39, top10 = 47.39, top15 = 45.29. -PHY-3001 : End congestion estimation; 2.843501s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (139.0%) +PHY-1001 : Congestion index: top1 = 57.26, top5 = 50.76, top10 = 47.63, top15 = 45.52. +PHY-3001 : End congestion estimation; 2.745855s wall, 3.984375s user + 0.046875s system = 4.031250s CPU (146.8%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 17977 nets completely. +TMR-2504 : Update delay of 17367 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 1.050007s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (99.7%) +PHY-3001 : End timing update; 0.856888s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.3%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155905 -PHY-3002 : Step(315): len = 726001, overlap = 47 -PHY-3002 : Step(316): len = 708939, overlap = 79 -PHY-3002 : Step(317): len = 693934, overlap = 107 -PHY-3002 : Step(318): len = 682022, overlap = 134.25 -PHY-3002 : Step(319): len = 675303, overlap = 153.75 -PHY-3002 : Step(320): len = 670910, overlap = 166.75 -PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000311809 -PHY-3002 : Step(321): len = 675899, overlap = 161 -PHY-3002 : Step(322): len = 680411, overlap = 157.25 -PHY-3002 : Step(323): len = 680703, overlap = 159 -PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000623619 -PHY-3002 : Step(324): len = 685248, overlap = 162 -PHY-3002 : Step(325): len = 694537, overlap = 157.25 +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140758 +PHY-3002 : Step(307): len = 731886, overlap = 40 +PHY-3002 : Step(308): len = 715385, overlap = 69.75 +PHY-3002 : Step(309): len = 702138, overlap = 103.25 +PHY-3002 : Step(310): len = 694199, overlap = 126.5 +PHY-3002 : Step(311): len = 689561, overlap = 142.25 +PHY-3002 : Step(312): len = 686302, overlap = 161 +PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000281517 +PHY-3002 : Step(313): len = 691059, overlap = 155.75 +PHY-3002 : Step(314): len = 696867, overlap = 151.5 +PHY-3002 : Step(315): len = 700207, overlap = 154.75 +PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000563034 +PHY-3002 : Step(316): len = 704208, overlap = 152 +PHY-3002 : Step(317): len = 716769, overlap = 142.75 +PHY-3002 : Step(318): len = 726097, overlap = 147.5 +PHY-3002 : Step(319): len = 724477, overlap = 152.25 +PHY-3002 : Step(320): len = 722958, overlap = 150.75 PHY-3001 : Legalization ... -PHY-3001 : End legalization; 0.036878s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.1%) +PHY-3001 : End legalization; 0.035588s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (87.8%) -PHY-3001 : Legalized: Len = 726660, Over = 0 -PHY-3001 : Spreading special nets. 535 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.122626s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.9%) +PHY-3001 : Legalized: Len = 753230, Over = 0 +PHY-3001 : Spreading special nets. 502 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.117334s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (93.2%) -PHY-3001 : 792 instances has been re-located, deltaX = 311, deltaY = 496, maxDist = 3. -PHY-3001 : Final: Len = 740432, Over = 0 +PHY-3001 : 763 instances has been re-located, deltaX = 218, deltaY = 480, maxDist = 4. +PHY-3001 : Final: Len = 763732, Over = 0 PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2 PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2 PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2 OPT-1001 : Start physical optimization ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7113, tnode num: 99613, tedge num: 127314. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73662, tnet num: 17367, tinst num: 6897, tnode num: 96251, tedge num: 123708. TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.912544s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (99.7%) +RUN-1003 : finish command "start_timer -report" in 1.925068s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.8%) -RUN-1004 : used memory is 659 MB, reserved memory is 669 MB, peak memory is 759 MB +RUN-1004 : used memory is 644 MB, reserved memory is 656 MB, peak memory is 740 MB OPT-1001 : Total overflow 0.00 peak overflow 0.00 OPT-1001 : Start high-fanout net optimization ... OPT-1001 : Update timing in global mode PHY-1001 : Start incremental global routing, caller is place ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 4601/18155. +PHY-1001 : Reuse net number 3147/17545. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 875920, over cnt = 2595(7%), over = 4177, worst = 7 -PHY-1002 : len = 892216, over cnt = 1474(4%), over = 2070, worst = 7 -PHY-1002 : len = 907184, over cnt = 609(1%), over = 815, worst = 7 -PHY-1002 : len = 916400, over cnt = 215(0%), over = 283, worst = 6 -PHY-1002 : len = 920760, over cnt = 2(0%), over = 2, worst = 1 -PHY-1001 : End global iterations; 2.048733s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (139.6%) +PHY-1002 : len = 892688, over cnt = 2553(7%), over = 4249, worst = 7 +PHY-1002 : len = 906992, over cnt = 1650(4%), over = 2401, worst = 6 +PHY-1002 : len = 922168, over cnt = 838(2%), over = 1189, worst = 5 +PHY-1002 : len = 932744, over cnt = 349(0%), over = 472, worst = 4 +PHY-1002 : len = 941992, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 2.055849s wall, 2.984375s user + 0.046875s system = 3.031250s CPU (147.4%) -PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.76, top10 = 46.25, top15 = 44.51. -PHY-1001 : End incremental global routing; 2.414312s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (133.3%) +PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.40, top10 = 46.57, top15 = 44.78. +PHY-1001 : End incremental global routing; 2.432615s wall, 3.359375s user + 0.046875s system = 3.406250s CPU (140.0%) TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 17977 nets completely. +TMR-2504 : Update delay of 17367 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ]. -TMR-6513 WARNING: No path found for constraint(s): set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ]. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.934980s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.3%) +OPT-1001 : End timing update; 0.878006s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.7%) -OPT-1001 : 6 high-fanout net processed. +OPT-1001 : 5 high-fanout net processed. PHY-3001 : Start incremental placement ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7019 has valid locations, 30 needs to be replaced -PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins -PHY-3001 : Found 487 cells with 2 region constraints. +PHY-3001 : eco cells: 6804 has valid locations, 26 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. PHY-3001 : Global placement ... -PHY-3001 : Initial: Len = 744753 +PHY-3001 : Initial: Len = 766643 PHY-3001 : Run with size of 4 -PHY-3001 : Cell area utilization is 76% +PHY-3001 : Cell area utilization is 74% PHY-3001 : Analyzing congestion ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16430/18187. +PHY-1001 : Reuse net number 16088/17575. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 926080, over cnt = 136(0%), over = 159, worst = 4 -PHY-1002 : len = 926352, over cnt = 49(0%), over = 50, worst = 2 -PHY-1002 : len = 926744, over cnt = 7(0%), over = 7, worst = 1 -PHY-1002 : len = 926864, over cnt = 3(0%), over = 3, worst = 1 -PHY-1002 : len = 926928, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 1.030650s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (83.4%) +PHY-1002 : len = 945112, over cnt = 91(0%), over = 106, worst = 5 +PHY-1002 : len = 945224, over cnt = 45(0%), over = 49, worst = 4 +PHY-1002 : len = 945592, over cnt = 12(0%), over = 12, worst = 1 +PHY-1002 : len = 945792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.605416s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (103.2%) -PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.91, top10 = 46.39, top15 = 44.65. -PHY-3001 : End congestion estimation; 1.349627s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (86.8%) +PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.46, top10 = 46.63, top15 = 44.85. +PHY-3001 : End congestion estimation; 0.922613s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (103.3%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76272, tnet num: 18009, tinst num: 7137, tnode num: 99971, tedge num: 127701. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73870, tnet num: 17397, tinst num: 6918, tnode num: 96518, tedge num: 123998. TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.886720s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.2%) +RUN-1003 : finish command "start_timer -report" in 1.866370s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.5%) -RUN-1004 : used memory is 685 MB, reserved memory is 685 MB, peak memory is 759 MB +RUN-1004 : used memory is 653 MB, reserved memory is 642 MB, peak memory is 740 MB TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 18009 nets completely. +TMR-2504 : Update delay of 17397 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. -TMR-6513 Similar messages will be suppressed. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 2.797503s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (100.0%) +PHY-3001 : End timing update; 2.760902s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (100.2%) PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0 -PHY-3002 : Step(326): len = 743867, overlap = 0 -PHY-3002 : Step(327): len = 743305, overlap = 0 +PHY-3002 : Step(321): len = 766643, overlap = 0.25 +PHY-3002 : Step(322): len = 766643, overlap = 0.25 PHY-3001 : Run with size of 2 -PHY-3001 : Cell area utilization is 76% +PHY-3001 : Cell area utilization is 74% PHY-3001 : Analyzing congestion ... PHY-1001 : Generate routing nets ... PHY-1001 : Incremental mode ON -PHY-1001 : Reuse net number 16418/18187. +PHY-1001 : Reuse net number 16108/17575. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 924720, over cnt = 82(0%), over = 103, worst = 5 -PHY-1002 : len = 924960, over cnt = 35(0%), over = 37, worst = 2 -PHY-1002 : len = 925400, over cnt = 6(0%), over = 6, worst = 1 -PHY-1002 : len = 925448, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.595471s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.0%) +PHY-1002 : len = 945792, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.141181s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%) -PHY-1001 : Congestion index: top1 = 54.44, top5 = 48.92, top10 = 46.35, top15 = 44.58. -PHY-3001 : End congestion estimation; 0.911954s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (102.8%) +PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.46, top10 = 46.63, top15 = 44.85. +PHY-3001 : End congestion estimation; 0.479341s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.1%) PHY-3001 : Update density targets... PHY-3001 : Update congestion history... PHY-3001 : Update timing in global mode ... TMR-2503 : Start to update net delay, extr mode = 5. -TMR-2504 : Update delay of 18009 nets completely. +TMR-2504 : Update delay of 17397 nets completely. TMR-2502 : Annotate delay completely, extr mode = 5. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -PHY-3001 : End timing update; 0.887492s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%) +PHY-3001 : End timing update; 0.876138s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%) -PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000923339 -PHY-3002 : Step(328): len = 743215, overlap = 2.75 -PHY-3002 : Step(329): len = 743191, overlap = 2.25 +PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000660531 +PHY-3002 : Step(323): len = 766351, overlap = 0.5 +PHY-3002 : Step(324): len = 766411, overlap = 1 PHY-3001 : Legalization ... -PHY-3001 : End legalization; 0.005560s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) +PHY-3001 : End legalization; 0.005803s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%) -PHY-3001 : Legalized: Len = 743458, Over = 0 -PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.062842s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%) +PHY-3001 : Legalized: Len = 766540, Over = 0 +PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059511s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.0%) -PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 1, maxDist = 1. -PHY-3001 : Final: Len = 743452, Over = 0 -PHY-3001 : End incremental placement; 6.439997s wall, 6.546875s user + 0.109375s system = 6.656250s CPU (103.4%) +PHY-3001 : 2 instances has been re-located, deltaX = 6, deltaY = 0, maxDist = 3. +PHY-3001 : Final: Len = 766658, Over = 0 +PHY-3001 : End incremental placement; 5.508754s wall, 5.671875s user + 0.031250s system = 5.703125s CPU (103.5%) OPT-1001 : Total overflow 0.00 peak overflow 0.00 -OPT-1001 : End high-fanout net optimization; 10.287435s wall, 11.187500s user + 0.125000s system = 11.312500s CPU (110.0%) +OPT-1001 : End high-fanout net optimization; 9.492859s wall, 10.562500s user + 0.093750s system = 10.656250s CPU (112.3%) -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. +OPT-1001 : Current memory(MB): used = 745, reserve = 741, peak = 751. OPT-1001 : Start bottleneck based optimization ... OPT-1001 : Start congestion update ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16399/18187. +PHY-1001 : Reuse net number 16078/17575. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 925280, over cnt = 75(0%), over = 98, worst = 6 -PHY-1002 : len = 925352, over cnt = 34(0%), over = 38, worst = 3 -PHY-1002 : len = 925488, over cnt = 7(0%), over = 7, worst = 1 -PHY-1002 : len = 925616, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.595918s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (107.5%) +PHY-1002 : len = 945224, over cnt = 95(0%), over = 106, worst = 5 +PHY-1002 : len = 945368, over cnt = 50(0%), over = 54, worst = 4 +PHY-1002 : len = 945840, over cnt = 17(0%), over = 17, worst = 1 +PHY-1002 : len = 946056, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.622496s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (107.9%) -PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.82, top10 = 46.31, top15 = 44.55. -OPT-1001 : End congestion update; 0.906222s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.2%) +PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.41, top10 = 46.58, top15 = 44.81. +OPT-1001 : End congestion update; 0.938541s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (104.9%) OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18009 nets completely. +TMR-2504 : Update delay of 17397 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.751194s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.8%) +OPT-1001 : End timing update; 0.718193s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%) -OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0 +OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1 PHY-3001 : Start incremental legalization ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins -PHY-3001 : Found 487 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 747310, Over = 0 -PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.070216s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.3%) +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 772964, Over = 0 +PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062103s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%) -PHY-3001 : 32 instances has been re-located, deltaX = 22, deltaY = 14, maxDist = 2. -PHY-3001 : Final: Len = 747890, Over = 0 -PHY-3001 : End incremental legalization; 0.441613s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.1%) +PHY-3001 : 32 instances has been re-located, deltaX = 16, deltaY = 24, maxDist = 3. +PHY-3001 : Final: Len = 773674, Over = 0 +PHY-3001 : End incremental legalization; 0.426299s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.6%) -OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 48 cells processed and 14898 slack improved +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 53 cells processed and 16636 slack improved PHY-3001 : Start incremental legalization ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins -PHY-3001 : Found 487 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 749174, Over = 0 -PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.062913s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%) +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 776062, Over = 0 +PHY-3001 : Spreading special nets. 22 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.062992s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.2%) -PHY-3001 : 21 instances has been re-located, deltaX = 8, deltaY = 19, maxDist = 3. -PHY-3001 : Final: Len = 749554, Over = 0 -PHY-3001 : End incremental legalization; 0.438820s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (124.6%) +PHY-3001 : 29 instances has been re-located, deltaX = 23, deltaY = 20, maxDist = 3. +PHY-3001 : Final: Len = 776308, Over = 0 +PHY-3001 : End incremental legalization; 0.381739s wall, 0.531250s user + 0.031250s system = 0.562500s CPU (147.4%) -OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 30 cells processed and 4936 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 29 cells processed and 8130 slack improved PHY-3001 : Start incremental legalization ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins -PHY-3001 : Found 487 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 749714, Over = 0 -PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.064612s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.7%) +PHY-3001 : eco cells: 6830 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6918 instances, 6769 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins +PHY-3001 : Found 504 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 776400, Over = 0 +PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.059385s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.2%) -PHY-3001 : 13 instances has been re-located, deltaX = 4, deltaY = 11, maxDist = 3. -PHY-3001 : Final: Len = 750026, Over = 0 -PHY-3001 : End incremental legalization; 0.396699s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.5%) +PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 7, maxDist = 2. +PHY-3001 : Final: Len = 776724, Over = 0 +PHY-3001 : End incremental legalization; 0.381257s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (110.7%) -OPT-0007 : Iter 3: improved WNS 21 TNS 0 NUM_FEPS 0 with 13 cells processed and 800 slack improved +OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 913 slack improved PHY-3001 : Start incremental legalization ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins -PHY-3001 : Found 489 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 750160, Over = 0 +PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6921 instances, 6772 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 777060, Over = 0 PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.062460s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%) +PHY-3001 : End spreading; 0.060879s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.7%) -PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 8, maxDist = 3. -PHY-3001 : Final: Len = 750268, Over = 0 -PHY-3001 : End incremental legalization; 0.395010s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.6%) +PHY-3001 : 6 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 2. +PHY-3001 : Final: Len = 777170, Over = 0 +PHY-3001 : End incremental legalization; 0.380412s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (123.2%) -OPT-0007 : Iter 4: improved WNS 21 TNS 0 NUM_FEPS 0 with 3 cells processed and 571 slack improved -OPT-1001 : End bottleneck based optimization; 3.925253s wall, 4.437500s user + 0.000000s system = 4.437500s CPU (113.1%) +OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 350 slack improved +OPT-1001 : End bottleneck based optimization; 3.782100s wall, 4.171875s user + 0.062500s system = 4.234375s CPU (112.0%) -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. +OPT-1001 : Current memory(MB): used = 744, reserve = 740, peak = 751. OPT-1001 : Start path based optimization ... OPT-1001 : Start congestion update ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16033/18189. +PHY-1001 : Reuse net number 15628/17578. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 932256, over cnt = 182(0%), over = 245, worst = 5 -PHY-1002 : len = 932488, over cnt = 90(0%), over = 102, worst = 4 -PHY-1002 : len = 933096, over cnt = 43(0%), over = 46, worst = 2 -PHY-1002 : len = 933736, over cnt = 4(0%), over = 4, worst = 1 -PHY-1002 : len = 933800, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.865332s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (106.5%) +PHY-1002 : len = 955952, over cnt = 203(0%), over = 264, worst = 4 +PHY-1002 : len = 955872, over cnt = 112(0%), over = 128, worst = 4 +PHY-1002 : len = 956728, over cnt = 49(0%), over = 51, worst = 2 +PHY-1002 : len = 957264, over cnt = 5(0%), over = 6, worst = 2 +PHY-1002 : len = 957432, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.903488s wall, 0.984375s user + 0.046875s system = 1.031250s CPU (114.1%) -PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.78, top10 = 46.37, top15 = 44.62. -OPT-1001 : End congestion update; 1.186710s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (105.3%) +PHY-1001 : Congestion index: top1 = 55.75, top5 = 49.94, top10 = 46.93, top15 = 45.03. +OPT-1001 : End congestion update; 1.223481s wall, 1.296875s user + 0.046875s system = 1.343750s CPU (109.8%) OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. +TMR-2504 : Update delay of 17400 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.765806s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%) +OPT-1001 : End timing update; 0.735771s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%) -OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0 +OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0 PHY-3001 : Start incremental legalization ... PHY-1001 : Populate physical database on model huagao_mipi_top. PHY-3001 : Initial placement ... PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins -PHY-3001 : Found 489 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 750488, Over = 0 -PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.063977s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%) +PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced +PHY-3001 : design contains 6921 instances, 6772 slices, 222 macros(1075 instances: 704 mslices 371 lslices) +PHY-3001 : Huge net sys_initial_done_dup_1163 with 3690 pins +PHY-3001 : Found 505 cells with 2 region constraints. +PHY-3001 : Cell area utilization is 74% +PHY-3001 : Initial: Len = 777382, Over = 0 +PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles. +PHY-3001 : End spreading; 0.060935s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%) -PHY-3001 : 11 instances has been re-located, deltaX = 4, deltaY = 9, maxDist = 3. -PHY-3001 : Final: Len = 750544, Over = 0 -PHY-3001 : End incremental legalization; 0.397794s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%) +PHY-3001 : 15 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2. +PHY-3001 : Final: Len = 777438, Over = 0 +PHY-3001 : End incremental legalization; 0.379118s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (94.8%) -OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 15 cells processed and 1500 slack improved -OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved -OPT-1001 : End path based optimization; 2.477193s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (102.8%) +OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 1850 slack improved +OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved +OPT-1001 : End path based optimization; 2.473393s wall, 2.515625s user + 0.046875s system = 2.562500s CPU (103.6%) -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. +OPT-1001 : Current memory(MB): used = 745, reserve = 740, peak = 751. OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. +TMR-2504 : Update delay of 17400 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.744515s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%) +OPT-1001 : End timing update; 0.721478s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%) OPT-1001 : Start pin optimization... OPT-1001 : skip pin optimization... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16404/18189. +PHY-1001 : Reuse net number 16047/17578. PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 933968, over cnt = 17(0%), over = 20, worst = 2 -PHY-1002 : len = 933984, over cnt = 5(0%), over = 6, worst = 2 -PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.430153s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.1%) +PHY-1002 : len = 957536, over cnt = 65(0%), over = 68, worst = 2 +PHY-1002 : len = 957520, over cnt = 34(0%), over = 35, worst = 2 +PHY-1002 : len = 957720, over cnt = 13(0%), over = 13, worst = 1 +PHY-1002 : len = 957808, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 957856, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 0.771293s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.3%) -PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61. +PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.90, top10 = 46.89, top15 = 45.00. OPT-1001 : Update timing in Manhattan mode TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. +TMR-2504 : Update delay of 17400 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.746601s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%) +OPT-1001 : End timing update; 0.743694s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.7%) RUN-1001 : QoR Analysis: -OPT-0007 : WNS 71 TNS 0 NUM_FEPS 0 -RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.310345 +OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0 +RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.379310 RUN-1001 : Top critical paths -RUN-1001 : #1 path slack 71ps with logic level 1 -RUN-1001 : extra opt step will be enabled to improve QoR -PHY-3001 : Start incremental legalization ... -PHY-1001 : Populate physical database on model huagao_mipi_top. -PHY-3001 : Initial placement ... -PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced -PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins -PHY-3001 : Found 489 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 750544, Over = 0 -PHY-3001 : End spreading; 0.060422s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%) +RUN-1001 : #1 path slack 171ps with logic level 1 +OPT-1001 : End physical optimization; 20.502210s wall, 21.984375s user + 0.234375s system = 22.218750s CPU (108.4%) -PHY-3001 : Final: Len = 750544, Over = 0 -PHY-3001 : End incremental legalization; 0.393231s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.4%) +RUN-1003 : finish command "place" in 65.321814s wall, 93.562500s user + 6.406250s system = 99.968750s CPU (153.0%) -OPT-1001 : Update timing in Manhattan mode -TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. -TMR-2502 : Annotate delay completely, extr mode = 3. -TMR-3501 : Forward propagation: start to calculate arrival time... -TMR-3502 : Backward propagation: start to calculate required time... -TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.745243s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%) - -OPT-1001 : Start path based optimization ... -OPT-1001 : Start congestion update ... -RUN-1001 : Generating global routing grids ... -PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16457/18189. -PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.130621s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.7%) - -PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61. -OPT-1001 : End congestion update; 0.445948s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.1%) - -OPT-1001 : Update timing in Manhattan mode -TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. -TMR-2502 : Annotate delay completely, extr mode = 3. -TMR-3501 : Forward propagation: start to calculate arrival time... -TMR-3502 : Backward propagation: start to calculate required time... -TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.739271s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.5%) - -OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 -PHY-3001 : Start incremental legalization ... -PHY-1001 : Populate physical database on model huagao_mipi_top. -PHY-3001 : Initial placement ... -PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced -PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced -PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced -PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices) -PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins -PHY-3001 : Found 489 cells with 2 region constraints. -PHY-3001 : Cell area utilization is 76% -PHY-3001 : Initial: Len = 750502, Over = 0 -PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles. -PHY-3001 : End spreading; 0.061781s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%) - -PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 2. -PHY-3001 : Final: Len = 750544, Over = 0 -PHY-3001 : End incremental legalization; 0.390925s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.9%) - -OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 2 cells processed and 150 slack improved -OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved -OPT-1001 : End path based optimization; 1.698525s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (104.9%) - -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. -OPT-1001 : Start bottleneck based optimization ... -OPT-1001 : Start congestion update ... -RUN-1001 : Generating global routing grids ... -PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16457/18189. -PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.135864s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%) - -PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61. -OPT-1001 : End congestion update; 0.479069s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.1%) - -OPT-1001 : Update timing in Manhattan mode -TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. -TMR-2502 : Annotate delay completely, extr mode = 3. -TMR-3501 : Forward propagation: start to calculate arrival time... -TMR-3502 : Backward propagation: start to calculate required time... -TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.770251s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%) - -OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0 -OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved -OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved -OPT-1001 : End bottleneck based optimization; 1.412098s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.7%) - -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. -OPT-1001 : Update timing in Manhattan mode -TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. -TMR-2502 : Annotate delay completely, extr mode = 3. -TMR-3501 : Forward propagation: start to calculate arrival time... -TMR-3502 : Backward propagation: start to calculate required time... -TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.756289s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.2%) - -OPT-1001 : Start pin optimization... -OPT-1001 : skip pin optimization... -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. -OPT-1001 : Start congestion recovery ... -RUN-1002 : start command "set_param place ofv 80" -OPT-1001 : Update timing in Manhattan mode -TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18010 nets completely. -TMR-2502 : Annotate delay completely, extr mode = 3. -TMR-3501 : Forward propagation: start to calculate arrival time... -TMR-3502 : Backward propagation: start to calculate required time... -TMR-3503 : Timing propagation completes. -OPT-1001 : End timing update; 0.770803s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%) - -RUN-1001 : Start congestion update ... -RUN-1001 : Generating global routing grids ... -PHY-1001 : Generate routing nets ... -PHY-1001 : Reuse net number 16457/18189. -PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 0.132917s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%) - -PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61. -RUN-1001 : End congestion update; 0.453021s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%) - -RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952 -OPT-1001 : End congestion recovery; 1.227344s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.6%) - -OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771. -OPT-1001 : End physical optimization; 27.483302s wall, 29.062500s user + 0.140625s system = 29.203125s CPU (106.3%) - -RUN-1003 : finish command "place" in 73.177550s wall, 102.531250s user + 6.625000s system = 109.156250s CPU (149.2%) - -RUN-1004 : used memory is 659 MB, reserved memory is 660 MB, peak memory is 771 MB +RUN-1004 : used memory is 619 MB, reserved memory is 620 MB, peak memory is 751 MB RUN-1002 : start command "export_db hg_anlogic_place.db" RUN-1001 : Exported / RUN-1001 : Exported flow parameters @@ -1619,9 +1429,9 @@ RUN-1001 : Exported violations RUN-1001 : Exported timing constraints RUN-1001 : Exported IO constraints RUN-1001 : Exported Inst constraints -RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.736455s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (172.8%) +RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.688800s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (173.9%) -RUN-1004 : used memory is 659 MB, reserved memory is 661 MB, peak memory is 771 MB +RUN-1004 : used memory is 619 MB, reserved memory is 620 MB, peak memory is 751 MB RUN-1002 : start command "route" RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic RUN-1001 : Print Global Property @@ -1646,30 +1456,30 @@ RUN-1001 : priority | timing | timing | RUN-1001 : swap_pin | on | on | RUN-1001 : ------------------------------------------------------- PHY-1001 : Route runs in 8 thread(s) -RUN-1001 : There are total 7142 instances -RUN-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps -RUN-1001 : There are total 18189 nets +RUN-1001 : There are total 6923 instances +RUN-1001 : 3390 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps +RUN-1001 : There are total 17578 nets RUN-6004 WARNING: There are 20 nets with only 1 pin. -RUN-1001 : 10477 nets have 2 pins -RUN-1001 : 5822 nets have [3 - 5] pins -RUN-1001 : 1180 nets have [6 - 10] pins -RUN-1001 : 327 nets have [11 - 20] pins -RUN-1001 : 355 nets have [21 - 99] pins +RUN-1001 : 9863 nets have 2 pins +RUN-1001 : 6029 nets have [3 - 5] pins +RUN-1001 : 968 nets have [6 - 10] pins +RUN-1001 : 331 nets have [11 - 20] pins +RUN-1001 : 359 nets have [21 - 99] pins RUN-1001 : 8 nets have 100+ pins RUN-1002 : start command "start_timer -report" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73898, tnet num: 17400, tinst num: 6921, tnode num: 96556, tedge num: 124038. TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -report" in 1.669688s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.2%) +RUN-1003 : finish command "start_timer -report" in 1.613675s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (99.7%) -RUN-1004 : used memory is 644 MB, reserved memory is 632 MB, peak memory is 771 MB -PHY-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps +RUN-1004 : used memory is 612 MB, reserved memory is 603 MB, peak memory is 751 MB +PHY-1001 : 3390 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps TMR-2503 : Start to update net delay, extr mode = 3. -TMR-2504 : Update delay of 18011 nets completely. +TMR-2504 : Update delay of 17400 nets completely. TMR-2502 : Annotate delay completely, extr mode = 3. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... @@ -1678,18 +1488,18 @@ PHY-1001 : Start global routing, caller is route ... RUN-1001 : Generating global routing grids ... PHY-1001 : Generate routing nets ... PHY-1001 : Global iterations in 8 thread ... -PHY-1002 : len = 860440, over cnt = 2807(7%), over = 4694, worst = 8 -PHY-1002 : len = 878304, over cnt = 1769(5%), over = 2646, worst = 7 -PHY-1002 : len = 899936, over cnt = 722(2%), over = 1043, worst = 6 -PHY-1002 : len = 914928, over cnt = 24(0%), over = 33, worst = 5 -PHY-1002 : len = 915672, over cnt = 0(0%), over = 0, worst = 0 -PHY-1001 : End global iterations; 3.062873s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (133.1%) +PHY-1002 : len = 886744, over cnt = 2771(7%), over = 4543, worst = 7 +PHY-1002 : len = 906680, over cnt = 1612(4%), over = 2237, worst = 7 +PHY-1002 : len = 927336, over cnt = 465(1%), over = 635, worst = 6 +PHY-1002 : len = 938064, over cnt = 2(0%), over = 2, worst = 1 +PHY-1002 : len = 938224, over cnt = 0(0%), over = 0, worst = 0 +PHY-1001 : End global iterations; 3.112924s wall, 4.328125s user + 0.062500s system = 4.390625s CPU (141.0%) -PHY-1001 : Congestion index: top1 = 53.77, top5 = 48.72, top10 = 45.99, top15 = 44.26. -PHY-1001 : End global routing; 3.394154s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (130.3%) +PHY-1001 : Congestion index: top1 = 55.43, top5 = 49.50, top10 = 46.60, top15 = 44.64. +PHY-1001 : End global routing; 3.440037s wall, 4.656250s user + 0.062500s system = 4.718750s CPU (137.2%) PHY-1001 : Start detail routing ... -PHY-1001 : Current memory(MB): used = 734, reserve = 732, peak = 771. +PHY-1001 : Current memory(MB): used = 719, reserve = 714, peak = 751. PHY-1001 : Detailed router is running in normal mode. PHY-1001 : Generate detailed routing grids ... PHY-1001 : Generate nets ... @@ -1719,147 +1529,167 @@ PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock me PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh -PHY-1001 : Current memory(MB): used = 1009, reserve = 1011, peak = 1009. -PHY-1001 : End build detailed router design. 4.123919s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (100.0%) +PHY-1001 : Current memory(MB): used = 991, reserve = 986, peak = 991. +PHY-1001 : End build detailed router design. 3.984718s wall, 3.906250s user + 0.062500s system = 3.968750s CPU (99.6%) PHY-1001 : Detail Route ... PHY-1001 : ===== Detail Route Phase 1 ===== PHY-1001 : Clock net routing..... PHY-1001 : Routed 0% nets. -PHY-1022 : len = 271128, over cnt = 4(0%), over = 4, worst = 1, crit = 0 -PHY-1001 : End initial clock net routed; 5.303886s wall, 5.312500s user + 0.000000s system = 5.312500s CPU (100.2%) +PHY-1022 : len = 274696, over cnt = 4(0%), over = 4, worst = 1, crit = 0 +PHY-1001 : End initial clock net routed; 4.987476s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (100.3%) PHY-1001 : Ripup-reroute..... PHY-1001 : ===== DR Iter 1 ===== -PHY-1022 : len = 271184, over cnt = 0(0%), over = 0, worst = 0, crit = 0 -PHY-1001 : End DR Iter 1; 0.432936s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.4%) +PHY-1022 : len = 274752, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 1; 0.428174s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.5%) -PHY-1001 : Current memory(MB): used = 1044, reserve = 1047, peak = 1044. -PHY-1001 : End phase 1; 5.749378s wall, 5.750000s user + 0.000000s system = 5.750000s CPU (100.0%) +PHY-1001 : Current memory(MB): used = 1027, reserve = 1023, peak = 1027. +PHY-1001 : End phase 1; 5.429324s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (100.2%) PHY-1001 : ===== Detail Route Phase 2 ===== PHY-1001 : Initial routing..... -PHY-1001 : Routed 45% nets. -PHY-1001 : Routed 53% nets. -PHY-1001 : Routed 62% nets. -PHY-1001 : Routed 74% nets. -PHY-1001 : Routed 94% nets. -PHY-1022 : len = 2.35174e+06, over cnt = 1913(0%), over = 1916, worst = 2, crit = 0 -PHY-1001 : Current memory(MB): used = 1063, reserve = 1062, peak = 1063. -PHY-1001 : End initial routed; 30.566888s wall, 61.609375s user + 0.359375s system = 61.968750s CPU (202.7%) +PHY-1001 : Routed 44% nets. +PHY-1001 : Routed 50% nets. +PHY-1001 : Routed 60% nets. +PHY-1001 : Routed 72% nets. +PHY-1001 : Routed 93% nets. +PHY-1022 : len = 2.37878e+06, over cnt = 1768(0%), over = 1777, worst = 2, crit = 0 +PHY-1001 : Current memory(MB): used = 1046, reserve = 1042, peak = 1046. +PHY-1001 : End initial routed; 26.947337s wall, 64.171875s user + 0.281250s system = 64.453125s CPU (239.2%) PHY-1001 : Update timing..... -PHY-1001 : 3/17112(0%) critical/total net(s). +PHY-1001 : 1/16501(0%) critical/total net(s). RUN-1001 : -------------------------------------- RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP RUN-1001 : -------------------------------------- -RUN-1001 : Setup | -0.821 | -1.201 | 5 +RUN-1001 : Setup | -0.512 | -0.512 | 1 RUN-1001 : Hold | 0.067 | 0.000 | 0 RUN-1001 : -------------------------------------- -PHY-1001 : End update timing; 3.373019s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (100.1%) +PHY-1001 : End update timing; 3.271242s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.3%) -PHY-1001 : Current memory(MB): used = 1071, reserve = 1069, peak = 1071. -PHY-1001 : End phase 2; 33.939995s wall, 64.984375s user + 0.359375s system = 65.343750s CPU (192.5%) +PHY-1001 : Current memory(MB): used = 1066, reserve = 1063, peak = 1066. +PHY-1001 : End phase 2; 30.218646s wall, 67.453125s user + 0.281250s system = 67.734375s CPU (224.1%) PHY-1001 : ===== Detail Route Phase 3 ===== PHY-1001 : Optimize timing..... PHY-1001 : ===== OPT Iter 1 ===== -PHY-1001 : Processed 3 pins with SWNS -0.811ns STNS -0.811ns FEP 1. -PHY-1001 : End OPT Iter 1; 0.152328s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%) +PHY-1001 : Processed 1 pins with SWNS -0.512ns STNS -0.512ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.135394s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%) -PHY-1022 : len = 2.35176e+06, over cnt = 1914(0%), over = 1917, worst = 2, crit = 0 -PHY-1001 : End optimize timing; 0.447400s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.8%) +PHY-1022 : len = 2.37878e+06, over cnt = 1768(0%), over = 1777, worst = 2, crit = 0 +PHY-1001 : End optimize timing; 0.403136s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%) PHY-1001 : Ripup-reroute..... PHY-1001 : ===== DR Iter 1 ===== -PHY-1022 : len = 2.32276e+06, over cnt = 783(0%), over = 786, worst = 2, crit = 0 -PHY-1001 : End DR Iter 1; 1.138908s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (189.3%) +PHY-1022 : len = 2.35112e+06, over cnt = 741(0%), over = 741, worst = 1, crit = 0 +PHY-1001 : End DR Iter 1; 1.141622s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (190.2%) PHY-1001 : ===== DR Iter 2 ===== -PHY-1022 : len = 2.31824e+06, over cnt = 149(0%), over = 150, worst = 2, crit = 0 -PHY-1001 : End DR Iter 2; 0.829325s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (147.0%) +PHY-1022 : len = 2.34766e+06, over cnt = 186(0%), over = 186, worst = 1, crit = 0 +PHY-1001 : End DR Iter 2; 0.787219s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (152.8%) PHY-1001 : ===== DR Iter 3 ===== -PHY-1022 : len = 2.31907e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0 -PHY-1001 : End DR Iter 3; 0.450179s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (118.0%) +PHY-1022 : len = 2.34914e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0 +PHY-1001 : End DR Iter 3; 0.439321s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (113.8%) PHY-1001 : ===== DR Iter 4 ===== -PHY-1022 : len = 2.31944e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0 -PHY-1001 : End DR Iter 4; 0.278370s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (117.9%) +PHY-1022 : len = 2.34927e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 +PHY-1001 : End DR Iter 4; 0.228050s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.6%) PHY-1001 : ===== DR Iter 5 ===== -PHY-1022 : len = 2.31957e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0 -PHY-1001 : End DR Iter 5; 0.272769s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (114.6%) +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 5; 0.200645s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.2%) PHY-1001 : ===== DR Iter 6 ===== -PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 -PHY-1001 : End DR Iter 6; 0.299020s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.3%) +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 6; 0.244432s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.9%) PHY-1001 : ===== DR Iter 7 ===== -PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 -PHY-1001 : End DR Iter 7; 0.291461s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.9%) +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 7; 0.339440s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (96.7%) PHY-1001 : ===== DR Iter 8 ===== -PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 -PHY-1001 : End DR Iter 8; 0.177934s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (114.2%) +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 8; 0.174811s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.3%) PHY-1001 : ==== DR Iter 9 ==== -PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 -PHY-1001 : End DR Iter 9; 0.177859s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (131.8%) +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 9; 0.171525s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.2%) + +PHY-1001 : ==== DR Iter 10 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 10; 0.197391s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.9%) + +PHY-1001 : ==== DR Iter 11 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 11; 0.238155s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%) + +PHY-1001 : ==== DR Iter 12 ==== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 12; 0.420331s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%) + +PHY-1001 : ===== DR Iter 13 ===== +PHY-1022 : len = 2.3493e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0 +PHY-1001 : End DR Iter 13; 0.186551s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.5%) + +PHY-1001 : ==== DR Iter 14 ==== +PHY-1022 : len = 2.34933e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End DR Iter 14; 0.166296s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.4%) PHY-1001 : Update timing..... -PHY-1001 : 1/17112(0%) critical/total net(s). +PHY-1001 : 1/16501(0%) critical/total net(s). RUN-1001 : -------------------------------------- RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP RUN-1001 : -------------------------------------- -RUN-1001 : Setup | -0.811 | -0.811 | 1 +RUN-1001 : Setup | -0.512 | -0.512 | 1 RUN-1001 : Hold | 0.067 | 0.000 | 0 RUN-1001 : -------------------------------------- -PHY-1001 : End update timing; 3.385904s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%) +PHY-1001 : End update timing; 3.263322s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%) PHY-1001 : Commit to database..... -PHY-1001 : 604 feed throughs used by 440 nets -PHY-1001 : End commit to database; 2.263587s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.1%) +PHY-1001 : 539 feed throughs used by 407 nets +PHY-1001 : End commit to database; 2.244404s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (99.6%) -PHY-1001 : Current memory(MB): used = 1178, reserve = 1182, peak = 1178. -PHY-1001 : End phase 3; 10.447954s wall, 12.000000s user + 0.078125s system = 12.078125s CPU (115.6%) +PHY-1001 : Current memory(MB): used = 1167, reserve = 1166, peak = 1167. +PHY-1001 : End phase 3; 11.268225s wall, 12.765625s user + 0.015625s system = 12.781250s CPU (113.4%) PHY-1001 : ===== Detail Route Phase 4 ===== PHY-1001 : Optimize timing..... PHY-1001 : ===== OPT Iter 1 ===== -PHY-1001 : Processed 1 pins with SWNS -0.811ns STNS -0.811ns FEP 1. -PHY-1001 : End OPT Iter 1; 0.140792s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%) +PHY-1001 : Processed 1 pins with SWNS -0.512ns STNS -0.512ns FEP 1. +PHY-1001 : End OPT Iter 1; 0.134571s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.5%) -PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 -PHY-1001 : End optimize timing; 0.389031s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.4%) +PHY-1022 : len = 2.34933e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0 +PHY-1001 : End optimize timing; 0.375858s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%) -PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.811ns, -0.811ns, 1} +PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.512ns, -0.512ns, 1} PHY-1001 : Update timing..... -PHY-1001 : 1/17112(0%) critical/total net(s). +PHY-1001 : 1/16501(0%) critical/total net(s). RUN-1001 : -------------------------------------- RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP RUN-1001 : -------------------------------------- -RUN-1001 : Setup | -0.811 | -0.811 | 1 +RUN-1001 : Setup | -0.512 | -0.512 | 1 RUN-1001 : Hold | 0.067 | 0.000 | 0 RUN-1001 : -------------------------------------- -PHY-1001 : End update timing; 3.348725s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.9%) +PHY-1001 : End update timing; 3.302470s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%) PHY-1001 : Commit to database..... -PHY-1001 : 604 feed throughs used by 440 nets -PHY-1001 : End commit to database; 2.386680s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.2%) +PHY-1001 : 539 feed throughs used by 407 nets +PHY-1001 : End commit to database; 2.338182s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (99.6%) -PHY-1001 : Current memory(MB): used = 1188, reserve = 1191, peak = 1188. -PHY-1001 : End phase 4; 6.151776s wall, 6.140625s user + 0.000000s system = 6.140625s CPU (99.8%) +PHY-1001 : Current memory(MB): used = 1175, reserve = 1175, peak = 1175. +PHY-1001 : End phase 4; 6.043345s wall, 6.046875s user + 0.000000s system = 6.046875s CPU (100.1%) -PHY-1003 : Routed, final wirelength = 2.3196e+06 -PHY-1001 : Current memory(MB): used = 1189, reserve = 1193, peak = 1189. -PHY-1001 : End export database. 0.062610s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%) +PHY-1003 : Routed, final wirelength = 2.34933e+06 +PHY-1001 : Current memory(MB): used = 1177, reserve = 1178, peak = 1177. +PHY-1001 : End export database. 0.063897s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.8%) -PHY-1001 : End detail routing; 60.875243s wall, 93.437500s user + 0.468750s system = 93.906250s CPU (154.3%) +PHY-1001 : End detail routing; 57.404755s wall, 96.062500s user + 0.359375s system = 96.421875s CPU (168.0%) -RUN-1003 : finish command "route" in 67.053396s wall, 100.609375s user + 0.484375s system = 101.093750s CPU (150.8%) +RUN-1003 : finish command "route" in 63.537357s wall, 103.375000s user + 0.468750s system = 103.843750s CPU (163.4%) -RUN-1004 : used memory is 1116 MB, reserved memory is 1113 MB, peak memory is 1189 MB +RUN-1004 : used memory is 1100 MB, reserved memory is 1098 MB, peak memory is 1177 MB RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area" RUN-1001 : standard ***Report Model: huagao_mipi_top Device: EG4D20EG176*** @@ -1871,12 +1701,12 @@ IO Statistics #inout 0 Utilization Statistics -#lut 10421 out of 19600 53.17% -#reg 9955 out of 19600 50.79% -#le 13076 - #lut only 3121 out of 13076 23.87% - #reg only 2655 out of 13076 20.30% - #lut® 7300 out of 13076 55.83% +#lut 10230 out of 19600 52.19% +#reg 9451 out of 19600 48.22% +#le 12649 + #lut only 3198 out of 12649 25.28% + #reg only 2419 out of 12649 19.12% + #lut® 7032 out of 12649 55.59% #dsp 3 out of 29 10.34% #bram 54 out of 64 84.38% #bram9k 50 @@ -1884,24 +1714,24 @@ Utilization Statistics #bram32k 4 out of 16 25.00% #pad 75 out of 130 57.69% #ireg 13 - #oreg 19 + #oreg 21 #treg 0 #pll 3 out of 4 75.00% #gclk 6 out of 16 37.50% Clock Resource Statistics Index ClockNet Type DriverType Driver Fanout -#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1825 -#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1432 -#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1342 -#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1235 -#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 140 -#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71 -#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70 +#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798 +#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1415 +#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1345 +#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 989 +#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 141 +#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72 +#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70 #8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26 #9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4 -#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_299.f1 3 -#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0 3 +#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_272.f1 3 +#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/en_adc_cfg_all_d1_reg_syn_8.f1 2 #12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1 #13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1 #14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1 @@ -1940,7 +1770,7 @@ Detailed IO Report clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE onoff_in INPUT P141 LVCMOS33 N/A N/A NONE - paper_in INPUT P16 LVCMOS25 N/A N/A NONE + paper_in INPUT P17 LVCMOS25 N/A N/A NONE rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L @@ -1966,7 +1796,7 @@ Detailed IO Report a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG - a_sp_sampling OUTPUT P25 LVCMOS25 8 N/A OREG + a_sp_sampling OUTPUT P133 LVCMOS33 8 N/A OREG b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE @@ -1976,114 +1806,59 @@ Detailed IO Report debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG - debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE - debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE + debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG + debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE - fan_pwm OUTPUT P139 LVCMOS33 8 N/A NONE + fan_pwm OUTPUT P143 LVCMOS33 8 N/A NONE frame_indicator OUTPUT P107 LVCMOS25 8 N/A OREG - onoff_out OUTPUT P111 LVCMOS25 8 N/A NONE + onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE paper_out OUTPUT P106 LVCMOS25 8 N/A NONE - scan_out OUTPUT P84 LVCMOS25 8 N/A NONE - sys_initial_done OUTPUT P71 LVCMOS25 8 N/A NONE + scan_out OUTPUT P91 LVCMOS25 8 N/A NONE + sys_initial_done OUTPUT P83 LVCMOS25 8 N/A NONE txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG Report Hierarchy Area: +---------------------------------------------------------------------------------------------------------+ |Instance |Module |le |lut |ripple |seq |bram |dsp | +---------------------------------------------------------------------------------------------------------+ -|top |huagao_mipi_top |13076 |9394 |1027 |9987 |58 |3 | -| U_rgb_to_csi_pakage |rgb_to_csi_pakage |544 |438 |23 |443 |4 |1 | -| U_fifo_w32_d8192 |fifo_w32_d8192 |100 |80 |4 |87 |4 |0 | -| U_crc16_24b |crc16_24b |35 |35 |0 |24 |0 |0 | -| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 | -| exdev_ctl_a |exdev_ctl |779 |386 |96 |580 |0 |0 | -| u_ADconfig |AD_config |204 |138 |25 |151 |0 |0 | -| u_gen_sp |gen_sp |263 |160 |71 |117 |0 |0 | -| exdev_ctl_b |exdev_ctl |739 |378 |96 |562 |0 |0 | -| u_ADconfig |AD_config |167 |122 |25 |125 |0 |0 | -| u_gen_sp |gen_sp |255 |147 |71 |120 |0 |0 | -| sampling_fe_a |sampling_fe |3214 |2625 |306 |2077 |25 |0 | -| u0_soft_n |cdc_sync |7 |2 |0 |7 |0 |0 | -| u_ad_sampling |ad_sampling |184 |145 |17 |136 |0 |0 | -| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 | -| u_sort |sort |2998 |2468 |289 |1909 |25 |0 | -| rddpram_ctl |rddpram_ctl |5 |4 |0 |5 |0 |0 | -| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | -| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 | -| u0_wrsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | -| u_data_prebuffer |data_prebuffer |2596 |2148 |253 |1582 |22 |0 | -| channelPart |channel_part_8478 |160 |155 |3 |126 |0 |0 | -| fifo_adc |fifo_adc |56 |47 |9 |39 |0 |0 | -| ram_switch |ram_switch |2024 |1637 |197 |1169 |0 |0 | -| adc_addr_gen |adc_addr_gen |255 |227 |27 |113 |0 |0 | -| [0]$ch_addr_gen |ch_addr_gen |11 |7 |3 |5 |0 |0 | -| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 | -| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 | -| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 | -| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 | -| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 | -| [6]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | -| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 | -| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |10 |0 |0 | -| insert |insert |987 |628 |170 |682 |0 |0 | -| ram_switch_state |ram_switch_state |782 |782 |0 |374 |0 |0 | -| read_ram_i |read_ram |313 |266 |44 |209 |0 |0 | -| read_ram_addr |read_ram_addr |251 |211 |40 |166 |0 |0 | -| read_ram_data |read_ram_data |57 |51 |4 |38 |0 |0 | -| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 | -| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 | -| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | -| u_transfer_300_to_200 |transfer_300_to_200 |326 |252 |36 |271 |3 |0 | -| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 | -| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | -| sampling_fe_b |sampling_fe_rev |3165 |2462 |349 |2109 |25 |1 | -| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 | -| u_ad_sampling |ad_sampling |187 |105 |17 |148 |0 |0 | -| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 | -| u_sort |sort_rev |2946 |2342 |332 |1929 |25 |1 | -| rddpram_ctl |rddpram_ctl_rev |6 |5 |0 |6 |0 |0 | -| u0_rdsoft_n |cdc_sync |6 |5 |0 |6 |0 |0 | -| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 | -| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | -| u_data_prebuffer_rev |data_prebuffer_rev |2485 |1993 |290 |1576 |22 |1 | -| channelPart |channel_part_8478 |275 |272 |3 |151 |0 |0 | -| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 | -| ram_switch |ram_switch |1756 |1391 |197 |1140 |0 |0 | -| adc_addr_gen |adc_addr_gen |198 |169 |27 |122 |0 |0 | -| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |9 |0 |0 | -| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |18 |0 |0 | -| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 | -| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |18 |0 |0 | -| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 | -| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 | -| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 | -| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 | -| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 | -| insert |insert |1012 |680 |170 |674 |0 |0 | -| ram_switch_state |ram_switch_state |546 |542 |0 |344 |0 |0 | -| read_ram_i |read_ram_rev |363 |258 |81 |213 |0 |0 | -| read_ram_addr |read_ram_addr_rev |298 |218 |73 |166 |0 |0 | -| read_ram_data |read_ram_data_rev |65 |40 |8 |47 |0 |0 | +|top |huagao_mipi_top |12649 |9203 |1027 |9485 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |559 |475 |23 |441 |4 |1 | +| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |89 |4 |90 |4 |0 | +| U_crc16_24b |crc16_24b |52 |52 |0 |23 |0 |0 | +| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 | +| exdev_ctl_a |exdev_ctl |761 |324 |96 |573 |0 |0 | +| u_ADconfig |AD_config |189 |120 |25 |143 |0 |0 | +| u_gen_sp |gen_sp |265 |152 |71 |123 |0 |0 | +| exdev_ctl_b |exdev_ctl |766 |382 |96 |571 |0 |0 | +| u_ADconfig |AD_config |184 |125 |25 |132 |0 |0 | +| u_gen_sp |gen_sp |262 |156 |71 |119 |0 |0 | +| sampling_fe_a |sampling_fe |2990 |2397 |306 |2064 |25 |0 | +| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 | +| u_ad_sampling |ad_sampling |184 |114 |17 |146 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort |2777 |2276 |289 |1889 |25 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | +| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u_data_prebuffer |data_prebuffer |2369 |2001 |253 |1552 |22 |0 | +| channelPart |channel_part_8478 |179 |175 |3 |146 |0 |0 | +| fifo_adc |fifo_adc |58 |49 |9 |42 |0 |0 | +| ram_switch |ram_switch |1838 |1538 |197 |1145 |0 |0 | +| adc_addr_gen |adc_addr_gen |234 |206 |27 |125 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |9 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| insert |insert |955 |683 |170 |644 |0 |0 | +| ram_switch_state |ram_switch_state |649 |649 |0 |376 |0 |0 | +| read_ram_i |read_ram |265 |213 |44 |190 |0 |0 | +| read_ram_addr |read_ram_addr |215 |175 |40 |154 |0 |0 | +| read_ram_data |read_ram_data |48 |37 |4 |34 |0 |0 | +| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | @@ -2092,22 +1867,77 @@ Report Hierarchy Area: | u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | | u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u_transfer_300_to_200 |transfer_300_to_200 |295 |175 |36 |264 |3 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 | +| sampling_fe_b |sampling_fe_rev |3425 |2768 |349 |2117 |25 |1 | +| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_ad_sampling |ad_sampling |186 |118 |17 |151 |0 |0 | +| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 | +| u_sort |sort_rev |3208 |2632 |332 |1935 |25 |1 | +| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 | +| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 | +| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 | +| u_data_prebuffer_rev |data_prebuffer_rev |2742 |2267 |290 |1583 |22 |1 | +| channelPart |channel_part_8478 |263 |250 |3 |149 |0 |0 | +| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |1 | +| ram_switch |ram_switch |1999 |1658 |197 |1136 |0 |0 | +| adc_addr_gen |adc_addr_gen |221 |194 |27 |106 |0 |0 | +| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 | +| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 | +| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 | +| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 | +| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 | +| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 | +| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 | +| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 | +| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 | +| insert |insert |972 |659 |170 |667 |0 |0 | +| ram_switch_state |ram_switch_state |806 |805 |0 |363 |0 |0 | +| read_ram_i |read_ram_rev |376 |267 |81 |214 |0 |0 | +| read_ram_addr |read_ram_addr_rev |307 |222 |73 |162 |0 |0 | +| read_ram_data |read_ram_data_rev |69 |45 |8 |52 |0 |0 | +| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | +| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 | |...... |...... |- |- |- |- |- |- | +---------------------------------------------------------------------------------------------------------+ DataNet Average Fanout: - Index Fanout Nets - #1 1 10415 - #2 2 3902 - #3 3 1365 - #4 4 552 - #5 5-10 1241 - #6 11-50 592 - #7 51-100 26 - #8 >500 1 - Average 2.89 + Index Fanout Nets + #1 1 9801 + #2 2 3950 + #3 3 1453 + #4 4 623 + #5 5-10 1031 + #6 11-50 602 + #7 51-100 22 + #8 >500 1 + Average 2.91 RUN-1002 : start command "export_db hg_anlogic_pr.db" RUN-1001 : Exported / @@ -2125,23 +1955,23 @@ RUN-1001 : Exported violations RUN-1001 : Exported timing constraints RUN-1001 : Exported IO constraints RUN-1001 : Exported Inst constraints -RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.122784s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (172.2%) +RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.081133s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (173.4%) -RUN-1004 : used memory is 1117 MB, reserved memory is 1115 MB, peak memory is 1189 MB +RUN-1004 : used memory is 1101 MB, reserved memory is 1100 MB, peak memory is 1177 MB RUN-1002 : start command "start_timer" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73898, tnet num: 17400, tinst num: 6921, tnode num: 96556, tedge num: 124038. TMR-2508 : Levelizing timing graph completed, there are 23 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer" in 1.647971s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%) +RUN-1003 : finish command "start_timer" in 1.622712s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (98.2%) -RUN-1004 : used memory is 1123 MB, reserved memory is 1121 MB, peak memory is 1189 MB +RUN-1004 : used memory is 1106 MB, reserved memory is 1105 MB, peak memory is 1177 MB RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" TMR-2503 : Start to update net delay, extr mode = 6. -TMR-2504 : Update delay of 18011 nets completely. +TMR-2504 : Update delay of 17400 nets completely. TMR-2502 : Annotate delay completely, extr mode = 6. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... @@ -2154,27 +1984,27 @@ TMR-5009 WARNING: No clock constraint on 3 clock net(s): exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 TMR-3508 : Export timing summary. TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm. -RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.560815s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.1%) +RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.496224s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (100.3%) -RUN-1004 : used memory is 1126 MB, reserved memory is 1123 MB, peak memory is 1189 MB +RUN-1004 : used memory is 1109 MB, reserved memory is 1107 MB, peak memory is 1177 MB RUN-1002 : start command "export_bid hg_anlogic_inst.bid" PRG-1000 : RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" BIT-1003 : Start to generate bitstream. BIT-1002 : Init instances with 8 threads. -BIT-1002 : Init instances completely, inst num: 7140 +BIT-1002 : Init instances completely, inst num: 6921 BIT-1002 : Init pips with 8 threads. -BIT-1002 : Init pips completely, net num: 18189, pip num: 175850 +BIT-1002 : Init pips completely, net num: 17578, pip num: 173874 BIT-1002 : Init feedthrough with 8 threads. -BIT-1002 : Init feedthrough completely, num: 604 +BIT-1002 : Init feedthrough completely, num: 539 BIT-1003 : Multithreading accelaration with 8 threads. -BIT-1003 : Generate bitstream completely, there are 3263 valid insts, and 489276 bits set as '1'. +BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 481518 bits set as '1'. BIT-1004 : the usercode register value: 00000000101110110000000000000000 BIT-1004 : PLL setting string = 1011 BIT-1004 : Generate bits file hg_anlogic.bit. BIT-1004 : Generate bin file hg_anlogic.bin. -RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.457605s wall, 62.250000s user + 0.156250s system = 62.406250s CPU (659.9%) +RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.230834s wall, 69.484375s user + 0.203125s system = 69.687500s CPU (681.2%) -RUN-1004 : used memory is 1297 MB, reserved memory is 1293 MB, peak memory is 1412 MB -RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_145210.log" +RUN-1004 : used memory is 1269 MB, reserved memory is 1265 MB, peak memory is 1384 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_164001.log" RUN-1001 : Backing up run's log file succeed. diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f index 399fe85..51b4ac0 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f index 399fe85..51b4ac0 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f index 399fe85..51b4ac0 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f @@ -1,5 +1,5 @@ - + diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj index 1ea84cb..e9e8842 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj @@ -1,5 +1,5 @@ - + UTF-8 5.6.71036 diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db index a517400..1958d87 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db differ diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area index e2707b8..b974005 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area @@ -8,16 +8,16 @@ IO Statistics #inout 0 LUT Statistics -#Total_luts 10030 - #lut4 5343 - #lut5 2132 +#Total_luts 9912 + #lut4 5066 + #lut5 2291 #lut6 0 #lut5_mx41 0 #lut4_alu1b 2555 Utilization Statistics -#lut 10030 out of 19600 51.17% -#reg 9745 out of 19600 49.72% +#lut 9912 out of 19600 50.57% +#reg 9232 out of 19600 47.10% #le 0 #dsp 3 out of 29 10.34% #bram 54 out of 64 84.38% @@ -27,7 +27,7 @@ Utilization Statistics #dram 16 #pad 75 out of 130 57.69% #ireg 13 - #oreg 19 + #oreg 21 #treg 0 #pll 3 out of 4 75.00% @@ -35,30 +35,30 @@ Report Hierarchy Area: +-------------------------------------------------------------------------------------------------+ |Instance |Module |lut |ripple |seq |bram |dsp | +-------------------------------------------------------------------------------------------------+ -|top |huagao_mipi_top |7475 |2555 |9777 |58 |3 | -| U_rgb_to_csi_pakage |rgb_to_csi_pakage |336 |81 |441 |4 |1 | +|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 | | U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | | U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | | U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | -| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 | -| u_ADconfig |AD_config |98 |49 |138 |0 |0 | -| u_gen_sp |gen_sp |127 |185 |104 |0 |0 | -| exdev_ctl_b |exdev_ctl |277 |234 |546 |0 |0 | -| u_ADconfig |AD_config |93 |49 |125 |0 |0 | +| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 | +| u_ADconfig |AD_config |102 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | | u_gen_sp |gen_sp |126 |185 |104 |0 |0 | -| sampling_fe_a |sampling_fe |2334 |738 |1919 |25 |0 | +| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_sort |sort |2264 |691 |1737 |25 |0 | +| u_sort |sort |2207 |691 |1737 |25 |0 | | rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_data_prebuffer |data_prebuffer |1922 |615 |1391 |22 |0 | +| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 | | channelPart |channel_part_8478 |146 |11 |144 |0 |0 | | fifo_adc |fifo_adc |51 |24 |41 |0 |0 | -| ram_switch |ram_switch |1483 |422 |1023 |0 |0 | +| ram_switch |ram_switch |1444 |422 |1023 |0 |0 | | adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | | [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | | [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | @@ -70,10 +70,10 @@ Report Hierarchy Area: | [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | insert |insert |265 |323 |692 |0 |0 | -| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 | -| read_ram_i |read_ram |206 |158 |164 |0 |0 | -| read_ram_addr |read_ram_addr |173 |145 |127 |0 |0 | -| read_ram_data |read_ram_data |32 |13 |32 |0 |0 | +| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 | +| read_ram_i |read_ram |189 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |27 |13 |32 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | @@ -100,19 +100,19 @@ Report Hierarchy Area: | u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | -| sampling_fe_b |sampling_fe_rev |2334 |751 |1936 |25 |1 | +| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_sort |sort_rev |2264 |704 |1754 |25 |1 | +| u_sort |sort_rev |2227 |704 |1754 |25 |1 | | rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_data_prebuffer_rev |data_prebuffer_rev |1925 |628 |1408 |22 |1 | +| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 | | channelPart |channel_part_8478 |146 |11 |144 |0 |0 | | fifo_adc |fifo_adc |51 |24 |41 |0 |1 | -| ram_switch |ram_switch |1484 |422 |1023 |0 |0 | +| ram_switch |ram_switch |1443 |422 |1023 |0 |0 | | adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | | [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | | [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | @@ -124,10 +124,10 @@ Report Hierarchy Area: | [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | insert |insert |265 |323 |692 |0 |0 | -| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 | -| read_ram_i |read_ram_rev |206 |171 |181 |0 |0 | -| read_ram_addr |read_ram_addr_rev |180 |145 |139 |0 |0 | -| read_ram_data |read_ram_data_rev |26 |26 |42 |0 |0 | +| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | @@ -155,10 +155,11 @@ Report Hierarchy Area: | u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | | scan_start_diff |scan_start_diff |30 |0 |12 |0 |0 | | u0_test_en |cdc_sync |1 |0 |5 |0 |0 | +| u1_BUSY_MIPI |cdc_sync |1 |0 |15 |0 |0 | | u1_test_en |cdc_sync |1 |0 |5 |0 |0 | | u2_test_en |cdc_sync |1 |0 |5 |0 |0 | -| u_O_clk_lp_n |cdc_sync |20 |0 |286 |0 |0 | -| u_O_clk_lp_p |cdc_sync |20 |0 |286 |0 |0 | +| u_O_clk_lp_n |cdc_sync |1 |0 |22 |0 |0 | +| u_O_clk_lp_p |cdc_sync |1 |0 |22 |0 |0 | | u_a_pclk |cdc_sync |1 |0 |5 |0 |0 | | u_a_sp_sampling |cdc_sync |1 |0 |5 |0 |0 | | u_a_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 | @@ -167,14 +168,14 @@ Report Hierarchy Area: | u_b_sp_sampling |cdc_sync |1 |0 |5 |0 |0 | | u_b_sp_sampling_cam |cdc_sync |1 |0 |5 |0 |0 | | u_b_sp_sampling_last |cdc_sync |1 |0 |5 |0 |0 | -| u_bus_top |ubus_top |817 |50 |1248 |0 |0 | -| u_local_bus_slve_cis |local_bus_slve_cis |723 |50 |721 |0 |0 | -| u_uart_2dsp |uart_2dsp |120 |31 |52 |0 |0 | +| u_bus_top |ubus_top |811 |50 |1248 |0 |0 | +| u_local_bus_slve_cis |local_bus_slve_cis |717 |50 |721 |0 |0 | +| u_uart_2dsp |uart_2dsp |123 |31 |52 |0 |0 | | u_dpi_mode |cdc_sync |2 |0 |10 |0 |0 | | u_eot |cdc_sync |1 |0 |5 |0 |0 | | u_lv_en_flag |cdc_sync |1 |0 |5 |0 |0 | -| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |167 |61 |226 |4 |0 | -| u_hs_tx_wrapper |hs_tx_wrapper |111 |61 |198 |4 |0 | +| u_mipi_dphy_tx_wrapper |mipi_dphy_tx_wrapper |172 |61 |226 |4 |0 | +| u_hs_tx_wrapper |hs_tx_wrapper |112 |61 |198 |4 |0 | | [0]$u_data_lane_wrapper |data_lane_wrapper |54 |52 |93 |1 |0 | | u_data_hs_generate |data_hs_generate |50 |52 |87 |1 |0 | | u_dphy_tx_fifo |dphy_tx_fifo |2 |0 |0 |1 |0 | @@ -195,7 +196,7 @@ Report Hierarchy Area: | u_clk_lane_wrapper |clk_lane_wrapper |3 |0 |8 |0 |0 | | u_clk_hs_generate |clk_hs_generate |3 |0 |4 |0 |0 | | u_clk_lp_generate |clk_lp_generate |0 |0 |4 |0 |0 | -| u_hs_tx_controler |hs_tx_controler |24 |9 |12 |0 |0 | +| u_hs_tx_controler |hs_tx_controler |25 |9 |12 |0 |0 | | u_mipi_eot_min |cdc_sync |20 |0 |65 |0 |0 | | u_mipi_sot_min |cdc_sync |20 |0 |65 |0 |0 | | u_pic_cnt |cdc_sync |38 |0 |120 |0 |0 | @@ -211,7 +212,7 @@ Report Hierarchy Area: | u_pll_lvds |pll_lvds |0 |0 |0 |0 |0 | | u_softrst_done |cdc_sync |1 |0 |5 |0 |0 | | u_softrst_fan_ctrl |cdc_sync |0 |0 |0 |0 |0 | -| ua_lvds_rx |lvds_rx |96 |67 |209 |0 |0 | -| ub_lvds_rx |lvds_rx |96 |67 |209 |0 |0 | +| ua_lvds_rx |lvds_rx |97 |67 |209 |0 |0 | +| ub_lvds_rx |lvds_rx |97 |67 |209 |0 |0 | | uu_pll_lvds |pll_lvds |0 |0 |0 |0 |0 | +-------------------------------------------------------------------------------------------------+ diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db index d780163..0f2b7b6 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db differ diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area index feb218a..527cea9 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area @@ -8,31 +8,31 @@ IO Statistics #inout 0 Gate Statistics -#Basic gates 14522 +#Basic gates 14015 #and 2480 #nand 0 #or 1078 #nor 0 - #xor 204 + #xor 207 #xnor 0 #buf 0 #not 469 #bufif1 5 - #MX21 615 + #MX21 618 #FADD 0 - #DFF 9665 + #DFF 9152 #LATCH 6 #MACRO_ADD 497 -#MACRO_EQ 227 +#MACRO_EQ 225 #MACRO_MULT 4 -#MACRO_MUX 4839 +#MACRO_MUX 4813 #MACRO_OTHERS 73 Report Hierarchy Area: +----------------------------------------------------------------------------+ |Instance |Module |gates |seq |macros | +----------------------------------------------------------------------------+ -|top |huagao_mipi_top |4851 |9671 |801 | +|top |huagao_mipi_top |4857 |9158 |799 | | U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | | U_crc16_24b |crc16_24b |67 |16 |0 | | U_ecc_gen |ecc_gen |37 |6 |0 | @@ -162,10 +162,11 @@ Report Hierarchy Area: | u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 | | scan_start_diff |scan_start_diff |8 |12 |0 | | u0_test_en |cdc_sync |2 |5 |0 | +| u1_BUSY_MIPI |cdc_sync |2 |15 |0 | | u1_test_en |cdc_sync |2 |5 |0 | | u2_test_en |cdc_sync |2 |5 |0 | -| u_O_clk_lp_n |cdc_sync |0 |286 |1 | -| u_O_clk_lp_p |cdc_sync |0 |286 |1 | +| u_O_clk_lp_n |cdc_sync |2 |22 |0 | +| u_O_clk_lp_p |cdc_sync |2 |22 |0 | | u_a_pclk |cdc_sync |2 |5 |0 | | u_a_sp_sampling |cdc_sync |2 |5 |0 | | u_a_sp_sampling_cam |cdc_sync |2 |5 |0 | diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db index 671666e..41d1729 100644 Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db differ diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log index 16f8d0b..efe9eb0 100644 --- a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log +++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log @@ -4,7 +4,7 @@ Executable = D:/Anlogic/TD5.6.2/bin/td.exe Built at = 20:34:38 Mar 21 2023 Run by = holdtecs - Run Date = Tue Mar 12 14:50:44 2024 + Run Date = Tue Mar 12 16:38:38 2024 Run on = DESKTOP-5MQL5VE ============================================================ @@ -97,19 +97,19 @@ HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in . HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150) HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158) HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159) -HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720) -HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729) -HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753) -HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755) -HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761) -HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) -HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935) -HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024) -HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325) -HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) -HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354) -HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) -HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v @@ -269,16 +269,16 @@ RUN-1001 : infer_shifter | on | on | RUN-1001 : -------------------------------------------------------------- HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126) HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142) -HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596) -HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734) -HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959) -HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) -HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607) +HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745) +HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970) +HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) +HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3) HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26) HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8) @@ -292,12 +292,9 @@ HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0) HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261) HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76) HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) -HDL-1007 : elaborate module cdc_sync(DEPTH=20,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(356) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(357) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(366) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(367) +HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1) HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1) +HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1) HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1) HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1) HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1) @@ -381,14 +378,14 @@ HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1 HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3) HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7) HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347) HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1) HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16) HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3) HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14) HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793) HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12) -HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415) +HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426) HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3) HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1) HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3) @@ -405,24 +402,24 @@ HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEP HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117) HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2) HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1) -HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498) +HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509) HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1) HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1) HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1) -HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547) HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1) HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1) HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102) -HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932) -HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298) +HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943) +HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309) HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed HDL-1200 : Current top model is huagao_mipi_top HDL-1100 : Inferred 1 RAMs. -RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.071047s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.7%) +RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.113594s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (99.6%) -RUN-1004 : used memory is 202 MB, reserved memory is 177 MB, peak memory is 243 MB +RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB RUN-1002 : start command "export_db hg_anlogic_elaborate.db" RUN-1001 : Exported / RUN-1001 : Exported flow parameters @@ -603,7 +600,8 @@ SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBU SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)" SYN-1012 : SanityCheck: Model "scan_start_diff" -SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20,WIDTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)" +SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)" SYN-1012 : SanityCheck: Model "ubus_top" SYN-1012 : SanityCheck: Model "local_bus_slve_cis" SYN-1012 : SanityCheck: Model "CRC4_D16" @@ -653,17 +651,17 @@ RUN-1001 : ua_lvds_rx | false | lvds_rx | RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t... RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t... -RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20,WIDTH... | ../../../../hg_mp/drx_t... -RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20,WIDTH... | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... +RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t... RUN-1001 : ------------------------------------------------------------------------------------------------ -SYN-1032 : 55777/19243 useful/useless nets, 21967/1798 useful/useless insts +SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts SYN-1001 : Optimize 156 less-than instances -SYN-1016 : Merged 38316 instances. +SYN-1016 : Merged 38319 instances. SYN-1025 : Merged 24 RAM ports. SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35 SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs. -SYN-1032 : 44304/8976 useful/useless nets, 12214/4743 useful/useless insts +SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts SYN-1016 : Merged 1876 instances. SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203) SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203) @@ -1175,7 +1173,7 @@ SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16 SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19) SYN-5014 Similar messages will be suppressed. SYN-5025 WARNING: Using 0 for all undriven pins and nets -SYN-1032 : 41977/363 useful/useless nets, 39174/558 useful/useless insts +SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts SYN-1014 : Optimize round 1 SYN-1017 : Remove 16 const input seq instances SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12 @@ -1201,10 +1199,10 @@ SYN-1020 : Optimized 3951 distributor mux. SYN-1001 : Optimize 12 less-than instances SYN-1019 : Optimized 39 mux instances. SYN-1016 : Merged 6256 instances. -SYN-1015 : Optimize round 1, 30452 better +SYN-1015 : Optimize round 1, 29939 better SYN-1014 : Optimize round 2 SYN-1044 : Optimized 15 inv instances. -SYN-1032 : 27603/1547 useful/useless nets, 24892/7583 useful/useless insts +SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts SYN-1017 : Remove 29 const input seq instances SYN-1002 : reg18_syn_2 SYN-1002 : reg22_syn_2 @@ -1239,7 +1237,7 @@ SYN-1019 : Optimized 24 mux instances. SYN-1020 : Optimized 43 distributor mux. SYN-1016 : Merged 118 instances. SYN-1015 : Optimize round 2, 9427 better -SYN-1032 : 27354/80 useful/useless nets, 24675/112 useful/useless insts +SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts SYN-3004 : Optimized 2 const0 DFF(s) SYN-3004 : Optimized 8 const0 DFF(s) SYN-3008 : Optimized 1 const1 DFF(s) @@ -1306,20 +1304,20 @@ SYN-3003 : Optimized 1 equivalent DFF(s) SYN-3003 : Optimized 1 equivalent DFF(s) SYN-3003 : Optimized 1 equivalent DFF(s) SYN-3004 : Optimized 2 const0 DFF(s) -SYN-1032 : 27261/93 useful/useless nets, 24593/6 useful/useless insts +SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts SYN-1014 : Optimize round 1 SYN-1019 : Optimized 228 mux instances. SYN-1020 : Optimized 2 distributor mux. SYN-1016 : Merged 3 instances. SYN-1015 : Optimize round 1, 279 better SYN-1014 : Optimize round 2 -SYN-1032 : 26983/20 useful/useless nets, 24331/2 useful/useless insts +SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts SYN-1015 : Optimize round 2, 2 better SYN-1014 : Optimize round 3 SYN-1015 : Optimize round 3, 0 better -RUN-1003 : finish command "optimize_rtl" in 19.481519s wall, 16.921875s user + 2.562500s system = 19.484375s CPU (100.0%) +RUN-1003 : finish command "optimize_rtl" in 18.914664s wall, 16.640625s user + 2.218750s system = 18.859375s CPU (99.7%) -RUN-1004 : used memory is 340 MB, reserved memory is 308 MB, peak memory is 359 MB +RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB RUN-1002 : start command "report_area -file hg_anlogic_rtl.area" RUN-1001 : standard ***Report Model: huagao_mipi_top Device: EG4D20EG176*** @@ -1331,31 +1329,31 @@ IO Statistics #inout 0 Gate Statistics -#Basic gates 14522 +#Basic gates 14015 #and 2480 #nand 0 #or 1078 #nor 0 - #xor 204 + #xor 207 #xnor 0 #buf 0 #not 469 #bufif1 5 - #MX21 615 + #MX21 618 #FADD 0 - #DFF 9665 + #DFF 9152 #LATCH 6 #MACRO_ADD 497 -#MACRO_EQ 227 +#MACRO_EQ 225 #MACRO_MULT 4 -#MACRO_MUX 4839 +#MACRO_MUX 4813 #MACRO_OTHERS 73 Report Hierarchy Area: +----------------------------------------------------------------------------+ |Instance |Module |gates |seq |macros | +----------------------------------------------------------------------------+ -|top |huagao_mipi_top |4851 |9671 |801 | +|top |huagao_mipi_top |4857 |9158 |799 | | U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 | | U_crc16_24b |crc16_24b |67 |16 |0 | | U_ecc_gen |ecc_gen |37 |6 |0 | @@ -1474,9 +1472,9 @@ RUN-1001 : Exported congestions RUN-1001 : Exported violations RUN-1001 : Exported IO constraints RUN-1001 : Exported Inst constraints -RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.122930s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (157.2%) +RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.112412s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (155.9%) -RUN-1004 : used memory is 336 MB, reserved memory is 306 MB, peak memory is 410 MB +RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 404 MB RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc" RUN-1002 : start command "get_ports clock_source" RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 " @@ -1514,42 +1512,6 @@ RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_c RUN-1002 : start command "get_ports clock_source" RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]" RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]" -RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]" -RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d" -RUN-1002 : start command "set_false_path -setup -from -to " -RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]" -RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2" -RUN-1002 : start command "set_false_path -setup -from -to " -RUN-1002 : start command "get_regs BUSY_MIPI" -RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_regs clkubus_rstn" -RUN-1002 : start command "get_nets a_pclk_rstn" -RUN-1002 : start command "set_false_path -from -to " -RUN-1002 : start command "get_regs clkubus_rstn" -RUN-1002 : start command "get_nets b_pclk_rstn" -RUN-1002 : start command "set_false_path -from -to " RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]" RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]" RUN-1002 : start command "set_false_path -from -to " @@ -1590,7 +1552,7 @@ RUN-1001 : report | standard | standard | RUN-1001 : retiming | off | off | RUN-1001 : ------------------------------------------------------------------ SYN-2001 : Map 61 IOs to PADs -SYN-1032 : 27017/24 useful/useless nets, 24380/26 useful/useless insts +SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts RUN-1002 : start command "update_pll_param -module huagao_mipi_top" SYN-2501 : Processed 0 LOGIC_BUF instances. SYN-2501 : 3 BUFG to GCLK @@ -1654,7 +1616,7 @@ SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35 SYN-2571 : Map 4 macro multiplier SYN-2571 : Optimize after map_dsp, round 1 -SYN-1032 : 27335/670 useful/useless nets, 24714/580 useful/useless insts +SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts SYN-1016 : Merged 11 instances. SYN-2571 : Optimize after map_dsp, round 1, 1181 better SYN-2571 : Optimize after map_dsp, round 2 @@ -1662,7 +1624,7 @@ SYN-2571 : Optimize after map_dsp, round 2, 0 better SYN-1001 : Throwback 317 control mux instances SYN-1001 : Convert 12 adder SYN-2501 : Optimize round 1 -SYN-1032 : 30821/338 useful/useless nets, 28201/38 useful/useless insts +SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts SYN-1016 : Merged 396 instances. SYN-2501 : Optimize round 1, 1774 better SYN-2501 : Optimize round 2 @@ -1693,30 +1655,30 @@ SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%. SYN-2501 : Inferred 22 ROM instances SYN-1019 : Optimized 9690 mux instances. SYN-1016 : Merged 12105 instances. -SYN-1032 : 38365/296 useful/useless nets, 35639/0 useful/useless insts +SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts RUN-1002 : start command "start_timer -prepack" TMR-2505 : Start building timing graph for model huagao_mipi_top. -TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 126687, tnet num: 38367, tinst num: 35639, tnode num: 164251, tedge num: 187234. +TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011. TMR-2508 : Levelizing timing graph completed, there are 89 levels in total. TMR-2501 : Timing graph initialized successfully. -RUN-1003 : finish command "start_timer -prepack" in 1.326087s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (100.2%) +RUN-1003 : finish command "start_timer -prepack" in 1.289776s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.3%) -RUN-1004 : used memory is 536 MB, reserved memory is 512 MB, peak memory is 536 MB +RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB TMR-2503 : Start to update net delay, extr mode = 2. -TMR-2504 : Update delay of 38367 nets completely. +TMR-2504 : Update delay of 36686 nets completely. TMR-2502 : Annotate delay completely, extr mode = 2. TMR-3001 : Initiate 12 clocks from SDC. -TMR-3004 : Map sdc constraints, there are 14 constraints in total. +TMR-3004 : Map sdc constraints, there are 2 constraints in total. TMR-3003 : Constraints initiated successfully. TMR-3501 : Forward propagation: start to calculate arrival time... TMR-3502 : Backward propagation: start to calculate required time... TMR-3503 : Timing propagation completes. SYN-3001 : Running gate level optimization. -SYN-2581 : Mapping with K=5, #lut = 7521 (3.86), #lev = 9 (3.15) +SYN-2581 : Mapping with K=5, #lut = 7492 (3.85), #lev = 9 (3.15) SYN-2551 : Post LUT mapping optimization. -SYN-2581 : Mapping with K=5, #lut = 7427 (3.95), #lev = 7 (3.06) -SYN-3001 : Logic optimization runtime opt = 1.25 sec, map = 0.00 sec -SYN-3001 : Mapper mapped 18994 instances into 7455 LUTs, name keeping = 58%. +SYN-2581 : Mapping with K=5, #lut = 7309 (3.95), #lev = 7 (3.04) +SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec +SYN-3001 : Mapper mapped 18922 instances into 7337 LUTs, name keeping = 61%. SYN-3001 : Mapper removed 2 lut buffers RUN-1002 : start command "report_area -file hg_anlogic_gate.area" RUN-1001 : standard @@ -1729,16 +1691,16 @@ IO Statistics #inout 0 LUT Statistics -#Total_luts 10030 - #lut4 5343 - #lut5 2132 +#Total_luts 9912 + #lut4 5066 + #lut5 2291 #lut6 0 #lut5_mx41 0 #lut4_alu1b 2555 Utilization Statistics -#lut 10030 out of 19600 51.17% -#reg 9745 out of 19600 49.72% +#lut 9912 out of 19600 50.57% +#reg 9232 out of 19600 47.10% #le 0 #dsp 3 out of 29 10.34% #bram 54 out of 64 84.38% @@ -1748,7 +1710,7 @@ Utilization Statistics #dram 16 #pad 75 out of 130 57.69% #ireg 13 - #oreg 19 + #oreg 21 #treg 0 #pll 3 out of 4 75.00% @@ -1756,30 +1718,30 @@ Report Hierarchy Area: +-------------------------------------------------------------------------------------------------+ |Instance |Module |lut |ripple |seq |bram |dsp | +-------------------------------------------------------------------------------------------------+ -|top |huagao_mipi_top |7475 |2555 |9777 |58 |3 | -| U_rgb_to_csi_pakage |rgb_to_csi_pakage |336 |81 |441 |4 |1 | +|top |huagao_mipi_top |7357 |2555 |9266 |58 |3 | +| U_rgb_to_csi_pakage |rgb_to_csi_pakage |343 |81 |441 |4 |1 | | U_crc16_24b |crc16_24b |50 |0 |16 |0 |0 | | U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 | | U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 | -| exdev_ctl_a |exdev_ctl |283 |234 |559 |0 |0 | -| u_ADconfig |AD_config |98 |49 |138 |0 |0 | -| u_gen_sp |gen_sp |127 |185 |104 |0 |0 | -| exdev_ctl_b |exdev_ctl |277 |234 |546 |0 |0 | -| u_ADconfig |AD_config |93 |49 |125 |0 |0 | +| exdev_ctl_a |exdev_ctl |288 |234 |559 |0 |0 | +| u_ADconfig |AD_config |102 |49 |138 |0 |0 | +| u_gen_sp |gen_sp |128 |185 |104 |0 |0 | +| exdev_ctl_b |exdev_ctl |276 |234 |546 |0 |0 | +| u_ADconfig |AD_config |92 |49 |125 |0 |0 | | u_gen_sp |gen_sp |126 |185 |104 |0 |0 | -| sampling_fe_a |sampling_fe |2334 |738 |1919 |25 |0 | +| sampling_fe_a |sampling_fe |2277 |738 |1919 |25 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_sort |sort |2264 |691 |1737 |25 |0 | +| u_sort |sort |2207 |691 |1737 |25 |0 | | rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_data_prebuffer |data_prebuffer |1922 |615 |1391 |22 |0 | +| u_data_prebuffer |data_prebuffer |1866 |615 |1391 |22 |0 | | channelPart |channel_part_8478 |146 |11 |144 |0 |0 | | fifo_adc |fifo_adc |51 |24 |41 |0 |0 | -| ram_switch |ram_switch |1483 |422 |1023 |0 |0 | +| ram_switch |ram_switch |1444 |422 |1023 |0 |0 | | adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | | [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | | [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | @@ -1791,10 +1753,10 @@ Report Hierarchy Area: | [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | insert |insert |265 |323 |692 |0 |0 | -| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 | -| read_ram_i |read_ram |206 |158 |164 |0 |0 | -| read_ram_addr |read_ram_addr |173 |145 |127 |0 |0 | -| read_ram_data |read_ram_data |32 |13 |32 |0 |0 | +| ram_switch_state |ram_switch_state |1050 |0 |216 |0 |0 | +| read_ram_i |read_ram |189 |158 |164 |0 |0 | +| read_ram_addr |read_ram_addr |161 |145 |127 |0 |0 | +| read_ram_data |read_ram_data |27 |13 |32 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | @@ -1821,19 +1783,19 @@ Report Hierarchy Area: | u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 | -| sampling_fe_b |sampling_fe_rev |2334 |751 |1936 |25 |1 | +| sampling_fe_b |sampling_fe_rev |2297 |751 |1936 |25 |1 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | | u_ad_sampling |ad_sampling |39 |47 |147 |0 |0 | | u0_soft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_sort |sort_rev |2264 |704 |1754 |25 |1 | +| u_sort |sort_rev |2227 |704 |1754 |25 |1 | | rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 | | u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 | -| u_data_prebuffer_rev |data_prebuffer_rev |1925 |628 |1408 |22 |1 | +| u_data_prebuffer_rev |data_prebuffer_rev |1888 |628 |1408 |22 |1 | | channelPart |channel_part_8478 |146 |11 |144 |0 |0 | | fifo_adc |fifo_adc |51 |24 |41 |0 |1 | -| ram_switch |ram_switch |1484 |422 |1023 |0 |0 | +| ram_switch |ram_switch |1443 |422 |1023 |0 |0 | | adc_addr_gen |adc_addr_gen |129 |99 |115 |0 |0 | | [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 | | [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | @@ -1845,10 +1807,10 @@ Report Hierarchy Area: | [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 | | insert |insert |265 |323 |692 |0 |0 | -| ram_switch_state |ram_switch_state |1090 |0 |216 |0 |0 | -| read_ram_i |read_ram_rev |206 |171 |181 |0 |0 | -| read_ram_addr |read_ram_addr_rev |180 |145 |139 |0 |0 | -| read_ram_data |read_ram_data_rev |26 |26 |42 |0 |0 | +| ram_switch_state |ram_switch_state |1049 |0 |216 |0 |0 | +| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 | +| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 | +| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 | | u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 | | u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 | @@ -1864,7 +1826,7 @@ SYN-1001 : Packing model "huagao_mipi_top" ... SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks SYN-1014 : Optimize round 1 SYN-1015 : Optimize round 1, 0 better -SYN-4002 : Packing 9745 DFF/LATCH to SEQ ... +SYN-4002 : Packing 9232 DFF/LATCH to SEQ ... SYN-4009 : Pack 83 carry chain into lslice SYN-4007 : Packing 1278 adder to BLE ... SYN-4008 : Packed 1278 adder and 126 SEQ to BLE. @@ -1872,9 +1834,9 @@ SYN-4007 : Packing 0 gate4 to BLE ... SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE. SYN-4012 : Packed 0 FxMUX SYN-4013 : Packed 16 DRAM and 4 SEQ. -RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 60.377693s wall, 59.921875s user + 0.453125s system = 60.375000s CPU (100.0%) +RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 58.555008s wall, 58.328125s user + 0.187500s system = 58.515625s CPU (99.9%) -RUN-1004 : used memory is 399 MB, reserved memory is 376 MB, peak memory is 726 MB +RUN-1004 : used memory is 399 MB, reserved memory is 388 MB, peak memory is 704 MB RUN-1002 : start command "legalize_phy_inst" SYN-1011 : Flatten model huagao_mipi_top SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0" @@ -1894,8 +1856,8 @@ RUN-1001 : Exported violations RUN-1001 : Exported timing constraints RUN-1001 : Exported IO constraints RUN-1001 : Exported Inst constraints -RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.605917s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (174.2%) +RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.568878s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (173.3%) -RUN-1004 : used memory is 415 MB, reserved memory is 399 MB, peak memory is 726 MB -RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_145044.log" +RUN-1004 : used memory is 406 MB, reserved memory is 382 MB, peak memory is 704 MB +RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_163838.log" RUN-1001 : Backing up run's log file succeed. diff --git a/src/prj/td_project/td_2024-03-11_09-44-52.log b/src/prj/td_project/td_2024-03-11_09-44-52.log index 62d1649..87063cd 100644 --- a/src/prj/td_project/td_2024-03-11_09-44-52.log +++ b/src/prj/td_project/td_2024-03-11_09-44-52.log @@ -4394,3 +4394,238 @@ RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_m RUN-1004 : used memory is 2212 MB, reserved memory is 2214 MB, peak memory is 2314 MB RUN-1001 : reset_run syn_1 phy_1. RUN-1001 : launch_runs syn_1 phy_1 -jobs 6. +RUN-1001 : stop_run syn_1. +RUN-1001 : reset_run syn_1 -step opt_gate. +RUN-1001 : syn_1: run complete. +RUN-1001 : open_run syn_1. +RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db" in 1.717677s wall, 1.390625s user + 0.125000s system = 1.515625s CPU (88.2%) + +RUN-1004 : used memory is 2225 MB, reserved memory is 2227 MB, peak memory is 2314 MB +HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v +RUN-1001 : reset_run syn_1 phy_1. +RUN-1001 : launch_runs syn_1 phy_1 -jobs 6. +RUN-1001 : syn_1: run complete. +RUN-1001 : phy_1: run complete. +RUN-1001 : open_run phy_1. +RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : eco open net = 0 +PHY-1001 : 475 feed throughs used by 371 nets +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 8.883825s wall, 8.921875s user + 0.296875s system = 9.218750s CPU (103.8%) + +RUN-1004 : used memory is 2322 MB, reserved memory is 2326 MB, peak memory is 2338 MB +TMR-3509 : Import timing summary. +RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" +PRG-2014 : Chip validation success: EAGLE_S20_EG176 +RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" +RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p" +RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.733013s wall, 0.265625s user + 0.250000s system = 0.515625s CPU (2.9%) + +RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB +RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.948798s wall, 0.375000s user + 0.265625s system = 0.640625s CPU (3.6%) + +RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB +GUI-1001 : Downloading succeeded! +RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" +PRG-2014 : Chip validation success: EAGLE_S20_EG176 +RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" +RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p" +RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.766793s wall, 0.062500s user + 0.093750s system = 0.156250s CPU (0.9%) + +RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB +RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.984587s wall, 0.187500s user + 0.109375s system = 0.296875s CPU (1.7%) + +RUN-1004 : used memory is 2330 MB, reserved memory is 2332 MB, peak memory is 2349 MB +GUI-1001 : Downloading succeeded! +TMR-3509 : Import timing summary. +HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v +HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118) +HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134) +HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150) +HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158) +HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159) +HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(720) +HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(729) +HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(753) +HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(755) +HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(761) +HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(764) +HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(935) +HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1024) +HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1325) +HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1336) +HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1354) +HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1536) +HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1932) +RUN-1001 : reset_run syn_1 phy_1. +GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist! +RUN-1001 : launch_runs syn_1 phy_1 -jobs 6. +RUN-1001 : syn_1: run complete. +RUN-1001 : phy_1: run complete. +RUN-1001 : open_run phy_1. +RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : eco open net = 0 +PHY-1001 : 588 feed throughs used by 440 nets +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.152214s wall, 9.234375s user + 0.296875s system = 9.531250s CPU (104.1%) + +RUN-1004 : used memory is 2375 MB, reserved memory is 2376 MB, peak memory is 2386 MB +TMR-3509 : Import timing summary. +RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" +PRG-2014 : Chip validation success: EAGLE_S20_EG176 +RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" +RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p" +RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.713168s wall, 0.734375s user + 0.593750s system = 1.328125s CPU (7.5%) + +RUN-1004 : used memory is 2380 MB, reserved memory is 2381 MB, peak memory is 2399 MB +RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.931766s wall, 0.859375s user + 0.609375s system = 1.468750s CPU (8.2%) + +RUN-1004 : used memory is 2380 MB, reserved memory is 2381 MB, peak memory is 2399 MB +GUI-1001 : Downloading succeeded! +RUN-1001 : reset_run phy_1 -step opt_place. +RUN-8001 ERROR: Run syn_1 should be up to date. +GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist! +RUN-1001 : reset_run syn_1 phy_1. +RUN-1001 : launch_runs syn_1 phy_1 -jobs 6. +RUN-1001 : syn_1: run complete. +RUN-1001 : phy_1: run complete. +RUN-1001 : open_run phy_1. +RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" +RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036. +RUN-1001 : Database version number 46146. +RUN-1001 : Import flow parameters +PHY-1001 : Generate detailed routing grids ... +PHY-1001 : Generate nets ... +PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh +PHY-1001 : net clock_source_dup_1 will be routed on clock mesh +PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output +PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output +PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf +PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config +PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n +PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n +PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh +PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf +PHY-5010 Similar messages will be suppressed. +PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh +PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh +PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh +PHY-1001 : eco open net = 0 +PHY-1001 : 604 feed throughs used by 440 nets +RUN-1001 : Import timing constraints +RUN-1001 : Import IO constraints +RUN-1001 : Import Inst constraints +RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146 +RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in 9.117688s wall, 9.171875s user + 0.296875s system = 9.468750s CPU (103.9%) + +RUN-1004 : used memory is 2398 MB, reserved memory is 2398 MB, peak memory is 2412 MB +TMR-3509 : Import timing summary. +RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" +PRG-2014 : Chip validation success: EAGLE_S20_EG176 +RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" +RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p" +RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.801503s wall, 0.156250s user + 0.078125s system = 0.234375s CPU (1.3%) + +RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB +RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 18.014165s wall, 0.296875s user + 0.093750s system = 0.390625s CPU (2.2%) + +RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB +GUI-1001 : Downloading succeeded! +RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" +PRG-2014 : Chip validation success: EAGLE_S20_EG176 +RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" +RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p" +RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in 17.758777s wall, 0.296875s user + 0.703125s system = 1.000000s CPU (5.6%) + +RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB +RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in 17.970594s wall, 0.421875s user + 0.718750s system = 1.140625s CPU (6.3%) + +RUN-1004 : used memory is 2402 MB, reserved memory is 2403 MB, peak memory is 2421 MB +GUI-1001 : Downloading succeeded!