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lvds-mono-16m
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1 Commit 1 Branch 0 Tags 221 MiB
Verilog 87.4%
VHDL 9.6%
Tcl 1.4%
Perl 1%
Stata 0.3%
Other 0.2%
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17828169534 146453b2fe origin projec 2024-01-23 17:01:09 +08:00
src origin projec 2024-01-23 17:01:09 +08:00