361 lines
7.8 KiB
C++
361 lines
7.8 KiB
C++
|
//
|
||
|
// Created by Nick on 2019/4/7.
|
||
|
//
|
||
|
#include "FpgaComm.h"
|
||
|
#include <thread>
|
||
|
#include "uartregsaccess.h"
|
||
|
#include "config.h"
|
||
|
#include <iostream>
|
||
|
|
||
|
#define Reg(x) (fpgaParams.x)
|
||
|
#define RegIndex(x) (std::distance((unsigned int*)&fpgaParams, (unsigned int*)&fpgaParams.x))
|
||
|
#define ReadReg(x) read(RegIndex(x), *((unsigned int*)&fpgaParams.x))
|
||
|
#define WriteReg(x) write(RegIndex(x), *((unsigned int*)&fpgaParams.x))
|
||
|
#define WR_Reg(x) (WriteReg(x),ReadReg(x))
|
||
|
|
||
|
#define CO(x) std::cout << #x << " : "<< RegIndex(x) << std::endl
|
||
|
|
||
|
FpgaComm::FpgaComm()
|
||
|
{
|
||
|
m_regsAccess.reset(new UartRegsAccess(FPGA_UART, 921600, 0x03, 0x83));
|
||
|
update();
|
||
|
|
||
|
Reg(AledR).sample = 256;
|
||
|
WR_Reg(AledR);
|
||
|
}
|
||
|
|
||
|
bool FpgaComm::read(unsigned int addr, unsigned int& val) {
|
||
|
return m_regsAccess->read(addr, val);
|
||
|
}
|
||
|
|
||
|
bool FpgaComm::write(unsigned int addr, unsigned int val) {
|
||
|
return m_regsAccess->write(addr, val);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::regsAccess_reset(bool enable){
|
||
|
if(enable)
|
||
|
{
|
||
|
if(!m_regsAccess.get())
|
||
|
m_regsAccess.reset(new UartRegsAccess(FPGA_UART, 921600, 0x03, 0x83));
|
||
|
update();
|
||
|
return;
|
||
|
}
|
||
|
if(m_regsAccess.get())
|
||
|
m_regsAccess.reset();
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setFrameHeight(int height){
|
||
|
Reg(frame).height = height;
|
||
|
WR_Reg(frame);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getFrameHeight()
|
||
|
{
|
||
|
return Reg(frame).height;
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setFrameNum(int num){
|
||
|
Reg(frame).num = num;
|
||
|
WR_Reg(frame);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::enableLed(bool bEnable) {
|
||
|
Reg(AledR).ledEnable = bEnable;
|
||
|
WR_Reg(AledR);
|
||
|
#ifdef HAS_UV
|
||
|
Reg(BledR).ledEnable = bEnable;
|
||
|
WR_Reg(BledR);
|
||
|
#else
|
||
|
Reg(BledR).ledEnable = bEnable;
|
||
|
WR_Reg(BledR);
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
void FpgaComm::enableUV(bool enable){
|
||
|
#ifdef HAS_UV
|
||
|
isUVEnable = enable;
|
||
|
Reg(BledR).ledEnable = isUVEnable;
|
||
|
WR_Reg(BledR);
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
void FpgaComm::capture() {
|
||
|
Reg(cmd).cmd = 0;
|
||
|
WriteReg(cmd);
|
||
|
Reg(cmd).cmd = 1;
|
||
|
WriteReg(cmd);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getRegs(int addr) {
|
||
|
return fpgaParams.regs[addr];
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setRegs(int addr, int value) {
|
||
|
fpgaParams.regs[addr] = value;
|
||
|
write(addr, value);
|
||
|
read(addr, fpgaParams.regs[addr]);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAGain(int indexGain, int value) {
|
||
|
int index = indexGain;
|
||
|
int val;// = value
|
||
|
value>=511?val=511:val=value;
|
||
|
index++;
|
||
|
fpgaParams.Aad.ad0_addr = index*2;
|
||
|
fpgaParams.Aad.ad1_addr = fpgaParams.Aad.ad0_addr + 1;
|
||
|
fpgaParams.Aad.ad0_value = val;
|
||
|
fpgaParams.Aad.ad1_value = val>255?1:0;
|
||
|
fpgaParams.Aad.ad0_rw = 0;
|
||
|
fpgaParams.Aad.ad1_rw = 0;
|
||
|
write(0x04,*(int*)&fpgaParams.Aad);
|
||
|
Reg(mode).adcA = 1;
|
||
|
WriteReg(mode);
|
||
|
Reg(mode).adcA = 0;
|
||
|
WriteReg(mode);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBGain(int indexGain, int value) {
|
||
|
int index = indexGain;
|
||
|
int val;// = value
|
||
|
value>=511?val=511:val=value;
|
||
|
index++;
|
||
|
fpgaParams.Bad.ad0_addr = index*2;
|
||
|
fpgaParams.Bad.ad1_addr = index*2 + 1;
|
||
|
fpgaParams.Bad.ad0_value = val;
|
||
|
fpgaParams.Bad.ad1_value = val>255?1:0;
|
||
|
fpgaParams.Bad.ad0_rw = 0;
|
||
|
fpgaParams.Bad.ad1_rw = 0;
|
||
|
write(0x07,*(int*)&fpgaParams.Bad);
|
||
|
Reg(mode).adcB = 1;
|
||
|
WriteReg(mode);
|
||
|
Reg(mode).adcB = 0;
|
||
|
WriteReg(mode);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAOffset(int indexOffset, int value) {
|
||
|
Reg(Aad).ad0_rw = 0;
|
||
|
Reg(Aad).ad1_rw = 0;
|
||
|
Reg(Aad).ad0_addr = indexOffset + 0x0e;
|
||
|
Reg(Aad).ad1_addr = 0x14;
|
||
|
Reg(Aad).ad0_value = value;
|
||
|
WriteReg(Aad);
|
||
|
Reg(mode).adcA = 1;
|
||
|
WriteReg(mode);
|
||
|
Reg(mode).adcA = 0;
|
||
|
WriteReg(mode);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBOffset(int indexOffset, int value) {
|
||
|
Reg(Bad).ad0_rw = 0;
|
||
|
Reg(Bad).ad1_rw = 0;
|
||
|
Reg(Bad).ad0_addr = indexOffset + 0x0e;
|
||
|
Reg(Bad).ad1_addr = 0x14;
|
||
|
Reg(Bad).ad0_value = value;
|
||
|
WriteReg(Bad);
|
||
|
Reg(mode).adcB = 1;
|
||
|
WriteReg(mode);
|
||
|
Reg(mode).adcB = 0;
|
||
|
WriteReg(mode);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAExposureR(int value) {
|
||
|
Reg(AledR).ledR = value;
|
||
|
WR_Reg(AledR);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAExposureG(int value) {
|
||
|
Reg(AledGB).ledG = value;
|
||
|
WR_Reg(AledGB);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAExposureB(int value) {
|
||
|
Reg(AledGB).ledB = value;
|
||
|
WR_Reg(AledGB);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setAExposureUV(int value){
|
||
|
#ifdef HAS_UV
|
||
|
Reg(UVLed).ledASide = value;
|
||
|
WR_Reg(UVLed);
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBExposureR(int value) {
|
||
|
Reg(BledR).ledR = value;
|
||
|
WR_Reg(BledR);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBExposureG(int value) {
|
||
|
Reg(BledGB).ledG = value;
|
||
|
WR_Reg(BledGB);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBExposureB(int value) {
|
||
|
Reg(BledGB).ledB = value;
|
||
|
WR_Reg(BledGB);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setBExpousreUV(int value){
|
||
|
#ifdef HAS_UV
|
||
|
Reg(UVLed).ledBSide = value;
|
||
|
WR_Reg(UVLed);
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setSp(int value)
|
||
|
{
|
||
|
Reg(mode).sp = value;
|
||
|
WR_Reg(mode);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getSp()
|
||
|
{
|
||
|
return Reg(mode).sp;
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setColorMode(int mode)
|
||
|
{
|
||
|
Reg(mode).colorMode = mode;
|
||
|
WR_Reg(mode);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getColorMode()
|
||
|
{
|
||
|
return Reg(mode).colorMode;
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setSample(int sample)
|
||
|
{
|
||
|
Reg(mode).sample = sample;
|
||
|
WR_Reg(mode);
|
||
|
Reg(AledR).sample = sample;
|
||
|
WR_Reg(AledR);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::EnableTest(bool bTest)
|
||
|
{
|
||
|
Reg(mode).selftest = bTest;
|
||
|
WR_Reg(mode);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::IsTest()
|
||
|
{
|
||
|
return Reg(mode).selftest;
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getSample()
|
||
|
{
|
||
|
return Reg(mode).sample;
|
||
|
}
|
||
|
|
||
|
void FpgaComm::setDpi(int dpi)
|
||
|
{
|
||
|
Reg(mode).dpi = dpi;
|
||
|
WR_Reg(mode);
|
||
|
}
|
||
|
|
||
|
int FpgaComm::getDpi()
|
||
|
{
|
||
|
return Reg(mode).dpi;
|
||
|
}
|
||
|
|
||
|
//20190626 YHP autoTrig function
|
||
|
void FpgaComm::setTrigMode(bool isArmMode) {
|
||
|
unsigned int tmp;
|
||
|
read(0x0b, tmp);
|
||
|
if(!isArmMode){ //default value+ ARM MODE,bit27 =0;
|
||
|
fpgaParams.TrigMode = tmp & 0XFBFFFFFF;
|
||
|
}else{
|
||
|
fpgaParams.TrigMode = tmp |(1<<26);
|
||
|
}
|
||
|
WR_Reg(TrigMode);
|
||
|
}
|
||
|
void FpgaComm::setDelayTime(int value) {
|
||
|
Reg(DelayTime) = value;
|
||
|
WR_Reg(DelayTime);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::update()
|
||
|
{
|
||
|
for(int i = 0; i < MAX_REGS; i++)
|
||
|
{
|
||
|
read(i, fpgaParams.regs[i]);
|
||
|
printf("reg[%d] = 0x%08x \n",i,fpgaParams.regs[i]);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void FpgaComm::enableJamCheck(bool b){
|
||
|
//Reg(BledR).user_define.led_sample.jamEnable = b;
|
||
|
//WR_Regs(0x08);
|
||
|
}
|
||
|
|
||
|
void FpgaComm::resetADC() {
|
||
|
|
||
|
fpgaParams.Aad.ad0_rw = 0;
|
||
|
fpgaParams.Aad.ad0_addr = 0;
|
||
|
fpgaParams.Aad.ad0_value = 0;
|
||
|
fpgaParams.Aad.ad1_rw = 0;
|
||
|
fpgaParams.Aad.ad1_addr = 0;
|
||
|
fpgaParams.Aad.ad1_value = 0;
|
||
|
WR_Reg(Aad);
|
||
|
fpgaParams.mode.adcA = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcA = 0;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.Bad.ad0_rw = 0;
|
||
|
fpgaParams.Bad.ad0_addr = 0;
|
||
|
fpgaParams.Bad.ad0_value = 0;
|
||
|
fpgaParams.Bad.ad1_rw = 0;
|
||
|
fpgaParams.Bad.ad1_addr = 0;
|
||
|
fpgaParams.Bad.ad1_value = 0;
|
||
|
WR_Reg(Bad);
|
||
|
fpgaParams.mode.adcB = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcB = 0;
|
||
|
WR_Reg(mode);
|
||
|
std::this_thread::sleep_for(std::chrono::milliseconds(100));
|
||
|
fpgaParams.Aad.ad0_rw = 0;
|
||
|
fpgaParams.Aad.ad0_addr = 0;
|
||
|
fpgaParams.Aad.ad0_value = 7;
|
||
|
fpgaParams.Aad.ad1_rw = 0;
|
||
|
fpgaParams.Aad.ad1_addr = 0;
|
||
|
fpgaParams.Aad.ad1_value = 7;
|
||
|
WR_Reg(Aad);
|
||
|
fpgaParams.mode.adcA = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcA = 0;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.Bad.ad0_rw = 0;
|
||
|
fpgaParams.Bad.ad0_addr = 0;
|
||
|
fpgaParams.Bad.ad0_value = 7;
|
||
|
fpgaParams.Bad.ad1_rw = 0;
|
||
|
fpgaParams.Bad.ad1_addr = 0;
|
||
|
fpgaParams.Bad.ad1_value = 7;
|
||
|
WR_Reg(Bad);
|
||
|
fpgaParams.mode.adcB = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcB = 0;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.Aad.ad0_rw = 0;
|
||
|
fpgaParams.Aad.ad0_addr = 1;
|
||
|
fpgaParams.Aad.ad0_value = 0x50;
|
||
|
fpgaParams.Aad.ad1_rw = 0;
|
||
|
fpgaParams.Aad.ad1_addr = 1;
|
||
|
fpgaParams.Aad.ad1_value = 0x50;
|
||
|
WR_Reg(Aad);
|
||
|
fpgaParams.mode.adcA = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcA = 0;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.Bad.ad0_rw = 0;
|
||
|
fpgaParams.Bad.ad0_addr = 1;
|
||
|
fpgaParams.Bad.ad0_value = 0x50;
|
||
|
fpgaParams.Bad.ad1_rw = 0;
|
||
|
fpgaParams.Bad.ad1_addr = 1;
|
||
|
fpgaParams.Bad.ad1_value = 0x50;
|
||
|
WR_Reg(Bad);
|
||
|
fpgaParams.mode.adcB = 1;
|
||
|
WR_Reg(mode);
|
||
|
fpgaParams.mode.adcB = 0;
|
||
|
WR_Reg(mode);
|
||
|
}
|