/* * @Author: your name * @Date: 2022-01-19 17:27:51 * @LastEditTime: 2023-02-27 18:06:42 * @LastEditors: Zhaozhonmin 1656963645@qq.com * @Description: 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE * @FilePath: \zynq_MSS\capimage\Camparams.h */ #pragma once /****************************FPGA REG DEFINE*****************************************/ union CamZ_Reg_2Short { unsigned short NShort[2]; int value; }; union CamZ_Reg_2char { unsigned char NChar[2]; int value; }; union CamZ_Reg_4 { int value; struct { unsigned int unuse_0 : 2; unsigned int color_mode : 1; unsigned int unuse_1 : 2; unsigned int encode_divide : 3; unsigned int encode_divide_mode : 1; unsigned int unuse_2 : 5; unsigned int en_adc_cfg : 1; unsigned int clr_exp : 1; unsigned int soft_reset : 1; unsigned int en_pattern : 1; unsigned int line_enable : 1; //不使用 unsigned int byte_sync : 1; unsigned int adc_config_all : 1 ; unsigned int adc_select : 5 ; unsigned int test_pattern : 1; unsigned int gpio1 : 1 ; unsigned int gpio2 : 1 ; unsigned int reserved : 3; }; }; union CamZ_Reg_4_New { int value; struct { unsigned int unuse_0 : 2; unsigned int color_mode : 1; unsigned int en_frameset:1;//帧计数只能 unsigned int unuse_1 : 9; unsigned int en_adc1_cfg:1; //使能ADC 配置 脉冲有效(写低写高) unsigned int en_adc2_cfg:1; //使能ADC 配置 脉冲有效(写低写高) unsigned int clr_exp:1; //曝光清除 低电平 有效 unsigned int soft_rst_n:1; //软复位 拉高 关闭FPGA unsigned int en_pattern:1; //使能自测试数据 unsigned int en_line:1; //行计数 }; }; union CamZ_Reg_A_New { int value; struct { unsigned int start : 1; //上升沿触发 unsigned int stop : 1; //下降沿触发 unsigned int unuse_0 : 5; unsigned int finished : 1; //finished unsigned int psen: 1; //使能相移 写低写高 unsigned int psincdec : 1; //相移动反向 unsigned int clr_psedon : 1;//清除相完成 写低写高 unsigned int dpi: 2;//bit 12 //1: 300DPI 0: 600DPI unsigned int dpi_200: 1; //dpi=1的时候 dpi_200=1 200dpi dpi=1的时候 dpi_200=0 300dpi dpi=0的时候 dpi_200=0 600dpi }; }; union CamZ_Reg_11 { int value; struct { unsigned int div_reg:5; unsigned int samp_reg:10; unsigned int low_reg:10; }; }; union SCAN_PWM { int value; struct { unsigned int reserved_1:1; unsigned int scan_pwm_enble : 1; unsigned int scan_pwm_start : 1; unsigned int scan_pwm_timer_runs :1; unsigned int scan_pwm_enble_o : 1; unsigned int scan_pwm_input_clear :1; unsigned int reserved_2:1; unsigned int scan_pwm_reset :1 ; }bit; }; union CamZ_Reg_A { int value; struct { unsigned int user_in : 1; unsigned int not_use1 : 5; unsigned int trigger_mode : 1; unsigned int : 4; unsigned int DPI : 1; unsigned int not_use2 : 20; }; }; /****************************FPGA REG DEFINE*****************************************/ /****************************PS REG DEFINE*******************************************/ enum PSReg { PS_VERSION, IMG_WIDTH, IMG_HEIGHT, BUF_WIDTH, BUF_HEIGHT, BUF_NUM, CAM_STATUS, MOTOR_SPEED, CAM_DPI, CAM_INFO, RLS_CHECK_CODE, //软件发布版本校验码 ADC_INFO, HEARTBAT, DATA_STATUS, REG_NUM, };